[Stitch] move segment assignment into CreateStitchedIP

src/finn/custom_op/fpgadataflow/lookup.py

@@ -65,9 +65,6 @@ class Lookup(HLSCustomOp):
             # Width for AXI-MM interface
             # only relevant when mem_mode="external"
             "ext_mem_width": ("i", False, 32),
-            # allocated AXI-MM address range
-            # only relevant when mem_mode="external"
-            "ext_mem_addr_range": ("s", False, "16M"),
         }
         my_attrs.update(super().get_nodeattr_types())
         return my_attrs
@@ -446,21 +443,3 @@ class Lookup(HLSCustomOp):
         intf_names["axilite"] = ["s_axi_control"]
         intf_names["aximm"] = [("m_axi_gmem", self.get_nodeattr("ext_mem_width"))]
         return intf_names
-
-    def code_generation_ipi(self):
-        mem_mode = self.get_nodeattr("mem_mode")
-        ret = super().code_generation_ipi()
-        if mem_mode == "external":
-            node_name = self.onnx_node.name
-            # TODO does the base offset need customizability?
-            base_offset = 0
-            range_str = self.get_nodeattr("ext_mem_addr_range")
-            ifname = "%s/Data_m_axi_gmem/SEG_m_axi_gmem0_Reg" % (node_name)
-            ret.append("assign_bd_address")
-            ret.append(
-                "set_property offset %d [get_bd_addr_segs {%s}]" % (base_offset, ifname)
-            )
-            ret.append(
-                "set_property range %s [get_bd_addr_segs {%s}]" % (range_str, ifname)
-            )
-        return ret

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -160,6 +160,15 @@ class CreateStitchedIP(Transformation):
             self.connect_cmds.append(
                 "set_property name m_axi_gmem0 [get_bd_intf_ports m_axi_gmem_0]"
             )
+            seg_name = "%s/Data_m_axi_gmem/SEG_m_axi_gmem0_Reg" % (inst_name)
+            self.connect_cmds.append(
+                "set_property offset 0 [get_bd_addr_segs {%s}]" % (seg_name)
+            )
+            # TODO should propagate this information from the node instead of 64M
+            self.connect_cmds.append(
+                "set_property range 64M [get_bd_addr_segs {%s}]" % (seg_name)
+            )
+
             self.intf_names["aximm"] = [("m_axi_gmem0", aximm_intf_name[0][1])]
             assert self.has_aximm is False, "Currently limited to one AXI-MM interface"
             self.has_aximm = True