Merge pull request #811 from Xilinx/bugfix/memstream_addr_width
Have IPI recompute AXI-lite address width according to user-defined memory layout.
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- finn-rtllib/memstream/component.xml 97 additions, 60 deletionsfinn-rtllib/memstream/component.xml
- finn-rtllib/memstream/gui/memstream_v1_0.gtcl 2 additions, 0 deletionsfinn-rtllib/memstream/gui/memstream_v1_0.gtcl
- finn-rtllib/memstream/hdl/memstream_axi_wrapper.v 3 additions, 2 deletionsfinn-rtllib/memstream/hdl/memstream_axi_wrapper.v
- finn-rtllib/memstream/xgui/memstream_v1_0.tcl 21 additions, 3 deletionsfinn-rtllib/memstream/xgui/memstream_v1_0.tcl
- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py 1 addition, 1 deletionsrc/finn/custom_op/fpgadataflow/matrixvectoractivation.py
- src/finn/custom_op/fpgadataflow/thresholding_batch.py 1 addition, 1 deletionsrc/finn/custom_op/fpgadataflow/thresholding_batch.py
- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py 1 addition, 1 deletionsrc/finn/custom_op/fpgadataflow/vectorvectoractivation.py
- src/finn/transformation/fpgadataflow/create_stitched_ip.py 82 additions, 14 deletionssrc/finn/transformation/fpgadataflow/create_stitched_ip.py
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