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Commit 423c32aa authored by Yaman Umuroglu's avatar Yaman Umuroglu
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[DWC] always use hls mode during insertion for better compat

parent a1519ef8
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......@@ -81,15 +81,11 @@ class InsertDWC(Transformation):
dwc_in_width = n0.get_outstream_width()
# determine dwc outwidth
dwc_out_width = n1.get_instream_width()
larger_width = max(dwc_in_width, dwc_out_width)
smaller_width = min(dwc_in_width, dwc_out_width)
both_8bit_aligned = (larger_width % 8 == 0) and (
smaller_width % 8 == 0
)
if both_8bit_aligned:
impl_style = "vivado"
else:
impl_style = "hls"
# use hls mode by default since it supports more configs
# vivado mode can be manually enabled by user, but does not
# support e.g. node-by-node rtlsim neded for
# characterization-based FIFO sizing
impl_style = "hls"
# determine shape for dwc
dwc_shape = n0.get_normal_output_shape()
......
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