Revised control interface attributes.

30a0058f · Thomas B. Preußer · fa182865 · 30a0058f · 30a0058f · 30a0058f
Commit 30a0058f authored 1 year ago by Thomas B. Preußer
--- a/finn-rtllib/axi_info/component.xml
+++ b/finn-rtllib/axi_info/component.xml
@@ -197,6 +197,10 @@
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
+        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
  </spirit:busInterfaces>
@@ -228,7 +232,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7d682dfc</spirit:value>
+            <spirit:value>c9da9874</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@@ -244,7 +248,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7d682dfc</spirit:value>
+            <spirit:value>c9da9874</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@@ -258,7 +262,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e11f9727</spirit:value>
+            <spirit:value>1e654f67</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@@ -607,7 +611,7 @@
      <spirit:file>
        <spirit:name>hdl/axi_info_top.sv</spirit:name>
        <spirit:fileType>systemVerilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_ec9ff0da</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_db6ccc10</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
@@ -692,17 +696,22 @@
      </xilinx:taxonomies>
      <xilinx:displayName>axi_info_top_v1_0</xilinx:displayName>
      <xilinx:definitionSource>package_project</xilinx:definitionSource>
-      <xilinx:coreRevision>5</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2022-05-30T14:16:13Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>6</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2023-05-24T06:36:33Z</xilinx:coreCreationDateTime>
    </xilinx:coreExtensions>
    <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="919b2cd5"/>
+      <xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3233b5e1"/>
      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="c930e363"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5ec5459d"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="28f3ac69"/>
      <xilinx:checksum xilinx:scope="ports" xilinx:value="bd3646cb"/>
      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="eab94b69"/>
      <xilinx:checksum xilinx:scope="parameters" xilinx:value="ba692e87"/>
+      <xilinx:targetDRCs>
+        <xilinx:targetDRC xilinx:tool="ipi">
+          <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
+        </xilinx:targetDRC>
+      </xilinx:targetDRCs>
    </xilinx:packagingInfo>
  </spirit:vendorExtensions>
 </spirit:component>
--- a/finn-rtllib/axi_info/hdl/axi_info_top.sv
+++ b/finn-rtllib/axi_info/hdl/axi_info_top.sv
@@ -38,7 +38,10 @@ module axi_info_top #(
 	bit [31:0]  CHECKSUM_COUNT
 )(
 	//- Global Control ------------------
+	(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET ap_rst_n" *)
+	(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
 	input	logic  ap_clk,
+	(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
 	input	logic  ap_rst_n,

 	//- AXI Lite ------------------------

--- a/finn-rtllib/memstream/component.xml
+++ b/finn-rtllib/memstream/component.xml
@@ -280,7 +280,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4c694b82</spirit:value>
+            <spirit:value>04464096</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@@ -296,7 +296,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4728d76a</spirit:value>
+            <spirit:value>9e058959</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@@ -784,7 +784,7 @@
      <spirit:file>
        <spirit:name>hdl/memstream_axi_wrapper.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_1dcfa744</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_7caabca7</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
@@ -879,11 +879,11 @@
      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
      <xilinx:definitionSource>package_project</xilinx:definitionSource>
      <xilinx:vendorDisplayName>AMD</xilinx:vendorDisplayName>
-      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:coreRevision>5</xilinx:coreRevision>
      <xilinx:upgrades>
        <xilinx:canUpgradeFrom>user.org:user:memstream_axi_wrapper:1.0</xilinx:canUpgradeFrom>
      </xilinx:upgrades>
-      <xilinx:coreCreationDateTime>2023-05-23T19:59:11Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2023-05-24T06:34:57Z</xilinx:coreCreationDateTime>
      <xilinx:tags>
        <xilinx:tag xilinx:name="nopcore"/>
      </xilinx:tags>
@@ -892,7 +892,7 @@
      <xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="aace24af"/>
      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="b683eac1"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2ee03fec"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7304ec2c"/>
      <xilinx:checksum xilinx:scope="ports" xilinx:value="8c876e99"/>
      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6488ba6f"/>
      <xilinx:checksum xilinx:scope="parameters" xilinx:value="10eb550f"/>

--- a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v
+++ b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v
@@ -43,7 +43,7 @@ module memstream_axi_wrapper #(
 	(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0, ASSOCIATED_RESET ap_rst_n" *)
 	(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
 	input	ap_clk,
-	(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
+	(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
 	input	ap_rst_n,

 	// AXI-lite Write

--- a/finn-rtllib/swg/swg_template_wrapper.v
+++ b/finn-rtllib/swg/swg_template_wrapper.v
@@ -28,19 +28,19 @@
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *****************************************************************************/
-`timescale 1 ns / 1 ps

 module $TOP_MODULE_NAME$ (
-(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *)
-input  ap_clk,
-(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *)
-input  ap_rst_n,
-input  [BUF_IN_WIDTH-1:0] in0_V_TDATA,
-input  in0_V_TVALID,
-output in0_V_TREADY,
-output [BUF_OUT_WIDTH-1:0] out_V_TDATA,
-output out_V_TVALID,
-input  out_V_TREADY
+	(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *)
+	(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
+	input  ap_clk,
+	(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
+	input  ap_rst_n,
+	input  [BUF_IN_WIDTH-1:0] in0_V_TDATA,
+	input  in0_V_TVALID,
+	output in0_V_TREADY,
+	output [BUF_OUT_WIDTH-1:0] out_V_TDATA,
+	output out_V_TVALID,
+	input  out_V_TREADY
 );

 // top-level parameters (set via code-generation)
@@ -53,23 +53,20 @@ parameter MMV_OUT = $MMV_OUT$;
 parameter BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN;
 parameter BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT;

-$TOP_MODULE_NAME$_impl
-#(
-    .BIT_WIDTH(BIT_WIDTH),
-    .SIMD(SIMD),
-    .MMV_IN(MMV_IN),
-    .MMV_OUT(MMV_OUT)
-)
-impl
-(
-    .ap_clk(ap_clk),
-    .ap_rst_n(ap_rst_n),
-    .in0_V_V_TDATA(in0_V_TDATA),
-    .in0_V_V_TVALID(in0_V_TVALID),
-    .in0_V_V_TREADY(in0_V_TREADY),
-    .out_V_V_TDATA(out_V_TDATA),
-    .out_V_V_TVALID(out_V_TVALID),
-    .out_V_V_TREADY(out_V_TREADY)
+$TOP_MODULE_NAME$_impl #(
+	.BIT_WIDTH(BIT_WIDTH),
+	.SIMD(SIMD),
+	.MMV_IN(MMV_IN),
+	.MMV_OUT(MMV_OUT)
+) impl (
+	.ap_clk(ap_clk),
+	.ap_rst_n(ap_rst_n),
+	.in0_V_V_TDATA(in0_V_TDATA),
+	.in0_V_V_TVALID(in0_V_TVALID),
+	.in0_V_V_TREADY(in0_V_TREADY),
+	.out_V_V_TDATA(out_V_TDATA),
+	.out_V_V_TVALID(out_V_TVALID),
+	.out_V_V_TREADY(out_V_TREADY)
 );

-endmodule //TOP_MODULE_NAME
+endmodule : $TOP_MODULE_NAME$
--- a/finn-rtllib/swg/swg_template_wrapper_dynamic.v
+++ b/finn-rtllib/swg/swg_template_wrapper_dynamic.v
-`timescale 1 ns / 1 ps
+/******************************************************************************
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright notice,
+ *	 this list of conditions and the following disclaimer.
+ *
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *	 notice, this list of conditions and the following disclaimer in the
+ *	 documentation and/or other materials provided with the distribution.
+ *
+ *  3. Neither the name of the copyright holder nor the names of its
+ *	 contributors may be used to endorse or promote products derived from
+ *	 this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/

 module $TOP_MODULE_NAME$ #(
    // top-level parameters (set via code-generation)
@@ -18,9 +47,10 @@ module $TOP_MODULE_NAME$ #(
    parameter integer C_s_axilite_ADDR_WIDTH	= 6
 )
 (
-    (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
+    (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite, ASSOCIATED_RESET ap_rst_n" *)
+    (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
    input  ap_clk,
-    (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
+    (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
    input  ap_rst_n,
    input  [BUF_IN_WIDTH-1:0] in0_V_TDATA,
    input  in0_V_TVALID,
@@ -113,17 +143,14 @@ $TOP_MODULE_NAME$_axilite # (
    .cfg_reg15(cfg_last_write)
 );

-$TOP_MODULE_NAME$_impl
-#(
+$TOP_MODULE_NAME$_impl #(
    .BIT_WIDTH(BIT_WIDTH),
    .SIMD(SIMD),
    .MMV_IN(MMV_IN),
    .MMV_OUT(MMV_OUT),
    .CNTR_BITWIDTH(CNTR_BITWIDTH),
    .INCR_BITWIDTH(INCR_BITWIDTH)
-)
-impl
-(
+) impl (
    .ap_clk(ap_clk),
    .ap_rst_n(ap_rst_n),
    .in0_V_V_TDATA(in0_V_TDATA),
@@ -151,4 +178,4 @@ impl
    .cfg_last_write(cfg_last_write)
 );

-endmodule //TOP_MODULE_NAME
+endmodule : $TOP_MODULE_NAME$