[HLSCustomOp] comment new get_verilog_top_module_intf_names style

src/finn/custom_op/fpgadataflow/hlscustomop.py

@@ -123,9 +123,10 @@ class HLSCustomOp(CustomOp):
         """Return a dict of names of input and output interfaces.
         The keys reflect the protocols each interface implements:
         'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'.
-        Values are lists of names:
-        's_axis' names correspond to the list of node inputs in order,
-        'm_axis' names correspond to the list of node outputs in order'
+        Values are lists of tuples (axis, aximm) or names (axilite):
+        'axis' tuples correspond to the list of node inputs in order,
+        each tuple is (interface_name, interface_width_bits).
+        axilite always assumed to be 32 bits and is not tuple (name only).
         Each block must have at most one aximm and one axilite."""
         intf_names = {}
         intf_names["clk"] = ["ap_clk"]