Merge pull request #711 from Xilinx/fix/vitisbuild (1d60ec65) · Commits · streichg / Finn · GitLab

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1d60ec65

Unverified Commit 1d60ec65 authored 2 years ago by auphelia Committed by GitHub 2 years ago

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Merge pull request #711 from Xilinx/fix/vitisbuild

[Fix] VitisBuild

parents 2d63a2a5 b23f0eb9

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src/finn/transformation/fpgadataflow/floorplan.py 12 additions, 3 deletions

src/finn/transformation/fpgadataflow/floorplan.py
src/finn/transformation/fpgadataflow/hlssynth_ip.py 5 additions, 1 deletion

src/finn/transformation/fpgadataflow/hlssynth_ip.py
src/finn/transformation/fpgadataflow/prepare_ip.py 5 additions, 1 deletion

src/finn/transformation/fpgadataflow/prepare_ip.py

with 22 additions and 5 deletions

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