[ZYNQ] copy hwh and bitfile to root proj folder

src/finn/transformation/fpgadataflow/make_zynq_proj.py

@@ -52,6 +52,7 @@ from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
 from finn.transformation.fpgadataflow.floorplan import Floorplan
 from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
 from finn.transformation.infer_data_layouts import InferDataLayouts
+from shutil import copy
 
 from . import templates
 
@@ -238,6 +239,23 @@ class MakeZYNQProject(Transformation):
         bash_command = ["bash", synth_project_sh]
         process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
         process_compile.communicate()
+        bitfile_name = (
+            vivado_pynq_proj_dir + "/finn_zynq_link.runs/impl_1/top_wrapper.bit"
+        )
+        if not os.path.isfile(bitfile_name):
+            raise Exception("Synthesis failed, no bitfile found")
+        deploy_bitfile_name = vivado_pynq_proj_dir + "/top.bit"
+        copy(bitfile_name, deploy_bitfile_name)
+        # set bitfile attribute
+        model.set_metadata_prop("vivado_pynq_bitfile", deploy_bitfile_name)
+        hwh_name = (
+            vivado_pynq_proj_dir
+            + "/finn_zynq_link.srcs/sources_1/bd/top/hw_handoff/top.hwh"
+        )
+        if not os.path.isfile(hwh_name):
+            raise Exception("Synthesis failed, no hardware handoff file found")
+        deploy_hwh_name = vivado_pynq_proj_dir + "/top.hwh"
+        copy(hwh_name, deploy_hwh_name)
         return (model, False)
 
 

tests/fpgadataflow/test_fpgadataflow_ipstitch.py

@@ -447,7 +447,7 @@ def test_fpgadataflow_ipstitch_vitis(board, period_ns, extw):
 @pytest.mark.parametrize("board", ["Pynq-Z1"])
 @pytest.mark.slow
 @pytest.mark.vivado
-def test_fpgadataflow_ipstitch_zynq(board):
+def test_fpgadataflow_ipstitch_zynqbuild(board):
     model = create_two_fc_model()
     if model.graph.node[0].op_type == "StreamingDataflowPartition":
         sdp_node = getCustomOp(model.graph.node[0])
@@ -456,3 +456,5 @@ def test_fpgadataflow_ipstitch_zynq(board):
         model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model"))
     model.transform(ZynqBuild(board, 10))
     model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_customzynq.onnx")
+    bitfile_name = model.get_metadata_prop("vivado_pynq_bitfile")
+    assert os.path.isfile(bitfile_name)