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Commit 1b5dc9a1 authored by Georg Streich's avatar Georg Streich
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Add axilite interface

parent d6395400
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...@@ -59,7 +59,7 @@ cfg_splits = build.DataflowBuildConfig( ...@@ -59,7 +59,7 @@ cfg_splits = build.DataflowBuildConfig(
build_cfg.DataflowOutputType.ESTIMATE_REPORTS, build_cfg.DataflowOutputType.ESTIMATE_REPORTS,
build_cfg.DataflowOutputType.STITCHED_IP, build_cfg.DataflowOutputType.STITCHED_IP,
], ],
# verify_steps = [build_cfg.VerificationStepType.FOLDED_HLS_CPPSIM], verify_steps = [build_cfg.VerificationStepType.FOLDED_HLS_CPPSIM],
board = 'U250', board = 'U250',
num_boards = 3, num_boards = 3,
save_intermediate_models = True, save_intermediate_models = True,
......
...@@ -32,7 +32,7 @@ class ACCLOp(HLSCustomOp): ...@@ -32,7 +32,7 @@ class ACCLOp(HLSCustomOp):
"dataType": ("s", True, ""), "dataType": ("s", True, ""),
# shape describing input vecs per execution # shape describing input vecs per execution
"numInputVectors": ("ints", False, [1]), "numInputVectors": ("ints", False, [1]),
# accl specific attrs # ACCL specific attrs
"startPort": ("i", False, 5500), "startPort": ("i", False, 5500),
"worldSize": ("i", True, 0), "worldSize": ("i", True, 0),
"otherRank": ("i", True, 0), "otherRank": ("i", True, 0),
...@@ -221,6 +221,8 @@ class ACCLOut(ACCLOp): ...@@ -221,6 +221,8 @@ class ACCLOut(ACCLOp):
'#pragma HLS INTERFACE axis port=sts_from_cclo', '#pragma HLS INTERFACE axis port=sts_from_cclo',
'#pragma HLS INTERFACE axis port=data_to_cclo', '#pragma HLS INTERFACE axis port=data_to_cclo',
'#pragma HLS INTERFACE axis port=in0_{}'.format(self.hls_sname()), '#pragma HLS INTERFACE axis port=in0_{}'.format(self.hls_sname()),
"#pragma HLS INTERFACE s_axilite port=dpcfg_adr bundle=control",
"#pragma HLS INTERFACE s_axilite port=comm_adr bundle=control",
] ]
self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return")
...@@ -358,6 +360,7 @@ class ACCLOut(ACCLOp): ...@@ -358,6 +360,7 @@ class ACCLOut(ACCLOp):
intf_names["m_axis"] = [("data_to_cclo", accl_word_size), ("cmd_to_cclo", 32)] intf_names["m_axis"] = [("data_to_cclo", accl_word_size), ("cmd_to_cclo", 32)]
intf_names["s_axis"].append(("sts_from_cclo", 32)) intf_names["s_axis"].append(("sts_from_cclo", 32))
intf_names["axilite"] = ["s_axi_control"]
return intf_names return intf_names
......
...@@ -48,7 +48,7 @@ class SetupACCLInterface(Transformation): ...@@ -48,7 +48,7 @@ class SetupACCLInterface(Transformation):
accl_out_node.name, accl_out_node.name,
pin_name pin_name
) )
for pin_name in ["cmd_to_cclo", "sts_from_cclo"] for pin_name in ["cmd_to_cclo", "sts_from_cclo", "s_axi_control"]
] ]
tcl.append("create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0") tcl.append("create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0")
......
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