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Commit 100c57cb authored by auphelia's avatar auphelia
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[Test] Add exp_cycle calculation test to channelwise test

parent c97d0e88
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......@@ -46,6 +46,8 @@ from finn.util.basic import gen_finn_dt_tensor
from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
ReplaceVerilogRelPaths,
)
from finn.custom_op.registry import getCustomOp
from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer
def make_modelwrapper(C, pe, idt, odt, pdt, func, vecs):
......@@ -154,3 +156,9 @@ def test_fpgadataflow_channelwise_ops(idt, act, pdt, nf, ich, func, vecs, exec_m
if exec_mode == "rtlsim":
hls_synt_res_est = model.analysis(hls_synth_res_estimation)
assert "ChannelwiseOp_Batch_0" in hls_synt_res_est
inst = getCustomOp(model.graph.node[0])
sim_cycles = inst.get_nodeattr("sim_cycles")
exp_cycles_dict = model.analysis(exp_cycles_per_layer)
exp_cycles = exp_cycles_dict[str(model.graph.node[0])]
assert np.isclose(exp_cycles, sim_cycles, atol=10)
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