Fix linting

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -536,7 +536,7 @@ class CreateStitchedIP(Transformation):
         tcl.append(
             "set all_v_files [get_files -filter {USED_IN_SYNTHESIS == 1 "
             + "&& (FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog "
-            + "|| FILE_TYPE ==\"Verilog Header\")}]"
+            + '|| FILE_TYPE =="Verilog Header")}]'
         )
         v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
         tcl.append("set fp [open %s w]" % v_file_list)

src/finn/util/pyverilator.py

@@ -74,8 +74,9 @@ def pyverilate_stitched_ip(
     # are identical but in multiple directories (regslice_core.v)
 
     # remove duplicates from list by doing list -> set -> list
-    all_verilog_files = list(set(filter(lambda x: x.endswith(".v") or x.endswith(".sv"),
-                                        all_verilog_srcs)))
+    all_verilog_files = list(
+        set(filter(lambda x: x.endswith(".v") or x.endswith(".sv"), all_verilog_srcs))
+    )
 
     # remove all but one instances of regslice_core.v
     filtered_verilog_files = []