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Commit f3be43a5 authored by Joachim Krech's avatar Joachim Krech
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Merge branch 'develop' of https://github.com/ARM-software/CMSIS_5 into develop

parents 03609a3e b4c9aea6
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.gitignore
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− 0
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*.breadcrumb
*.junit
**/__pycache__
Local_Release/
CMSIS/Documentation/
CMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvguix.*
CMSIS/CoreValidation/Tests/build
CMSIS/CoreValidation/Tests/bootloader/build
CMSIS/CoreValidation/Tests/RTE_Components.h
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......@@ -27,6 +27,10 @@
#define CMSIS_device_header "ARMCM33_DSP_FP.h"
#elif defined(ARMCM33_DSP_FP_TZ)
#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
#elif defined(ARMCM35P)
#define CMSIS_device_header "ARMCM35P.h"
#elif defined(ARMCM35P_DSP_FP_TZ)
#define CMSIS_device_header "ARMCM35P_DSP_FP_TZ.h"
#elif defined(ARMCA5)
#define CMSIS_device_header "ARMCA5.h"
#elif defined(ARMCA7)
......
CMSIS/CoreValidation/Tests/armclang.rtebuild
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......@@ -104,6 +104,27 @@ targets:
fpu : FPv5-SP
float : hard
linkscript: "config/core_m/rtebuild_ns.sct"
armcm35p:
mcpu : cortex-m35p
cpu : cortex-m35p.no_dsp
features: "+nodsp"
mfpu : none
fpu : SoftVFP
float : soft
armcm35ps:
mcpu : cortex-m35p
cpu : cortex-m35p
mfpu : fpv5-sp-d16
fpu : FPv5-SP
float : hard
cflags : [ -mcmse ]
armcm35pns:
mcpu : cortex-m35p
cpu : cortex-m35p
mfpu : fpv5-sp-d16
fpu : FPv5-SP
float : hard
linkscript: "config/core_m/rtebuild_ns.sct"
armca:
cflags : [ -xc, -std=c99, -c, --target=arm-arm-none-eabi, "-mcpu=${cpu}", "-mfpu=${fpu}", "-mfloat-abi=${float}", -marm, "${csettings}", "${cwarnings}" ]
asmflags : [ -c, --target=arm-arm-none-eabi, "-mcpu=${cpu}", "-mfpu=${fpu}", "-mfloat-abi=${float}", -marm, "${csettings}", "${cwarnings}" ]
......
CMSIS/CoreValidation/Tests/bootloader/RTE_Components.h
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......@@ -5,6 +5,8 @@
#define CMSIS_device_header "ARMCM23_TZ.h"
#elif defined(ARMCM33_DSP_FP_TZ)
#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
#elif defined(ARMCM35P_DSP_FP_TZ)
#define CMSIS_device_header "ARMCM35P_DSP_FP_TZ.h"
#else
#error "Unknown device selection!"
#endif
......
CMSIS/CoreValidation/Tests/bootloader/armclang.rtebuild
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......@@ -25,3 +25,8 @@ targets:
fpu : fpv5-sp-d16
float : hard
cflags : [ -mcmse ]
armcm35pns:
cpu : cortex-m35p
fpu : fpv5-sp-d16
float : hard
cflags : [ -mcmse ]
CMSIS/CoreValidation/Tests/bootloader/bootloader.rtebuild
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− 0
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......@@ -18,6 +18,10 @@ targets:
extends: armcm
device : ARMCM33
dsuffix: "_DSP_FP_TZ"
armcm35pns:
extends: armcm
device : ARMCM35P
dsuffix: "_DSP_FP_TZ"
include:
- ./
- ../../../../Device/ARM/${device}/Include
......
CMSIS/CoreValidation/Tests/bootloader/config/core_m/partition_ARMCM35P.h 0 → 100644
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CMSIS/CoreValidation/Tests/bootloader/gcc.rtebuild
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......@@ -28,3 +28,11 @@ targets:
cflags : [ "-mfpu=${fpu}", -mcmse ]
asmflags : [ "-mfpu=${fpu}" ]
linkflags: [ "-mfpu=${fpu}" ]
armcm35pns:
arch : armv8-m.main
cpu : cortex-m33
fpu : fpv5-sp-d16
float : hard
cflags : [ "-mfpu=${fpu}", -mcmse ]
asmflags : [ "-mfpu=${fpu}" ]
linkflags: [ "-mfpu=${fpu}" ]
CMSIS/CoreValidation/Tests/builder.py
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......@@ -62,34 +62,41 @@ CORTEX_M = [
Device.CM33NS,
Device.CM23S,
Device.CM33S,
Device.CM35P,
Device.CM35PS,
Device.CM35PNS
]
BOOTLOADER = [
Device.CM23NS,
Device.CM33NS
Device.CM33NS,
Device.CM35PNS
]
FVP_MODELS = {
Device.CM0 : { 'cmd': "FVP_MPS2_Cortex-M0", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM0_config.txt" } },
Device.CM0PLUS : { 'cmd': "FVP_MPS2_Cortex-M0plus", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM0plus_config.txt" } },
Device.CM3 : { 'cmd': "FVP_MPS2_Cortex-M3", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM3_config.txt" } },
Device.CM4 : { 'cmd': "FVP_MPS2_Cortex-M4", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM4_config.txt" } },
Device.CM4FP : { 'cmd': "FVP_MPS2_Cortex-M4", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM4FP_config.txt" } },
Device.CM7 : { 'cmd': "FVP_MPS2_Cortex-M7", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM7_config.txt" } },
Device.CM7SP : { 'cmd': "FVP_MPS2_Cortex-M7", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM7SP_config.txt" } },
Device.CM7DP : { 'cmd': "FVP_MPS2_Cortex-M7", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM7DP_config.txt" } },
Device.CM23 : { 'cmd': "FVP_MPS2_Cortex-M23", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM23_config.txt", 'target': "cpu0" } },
Device.CM33 : { 'cmd': "FVP_MPS2_Cortex-M33", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM33_config.txt", 'target': "cpu0" } },
Device.CM23NS : { 'cmd': "FVP_MPS2_Cortex-M23", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM23_TZ_config.txt", 'target': "cpu0" } },
Device.CM33NS : { 'cmd': "FVP_MPS2_Cortex-M33", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
Device.CM23S : { 'cmd': "FVP_MPS2_Cortex-M23", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM23_TZ_config.txt", 'target': "cpu0" } },
Device.CM33S : { 'cmd': "FVP_MPS2_Cortex-M33", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
Device.CA5 : { 'cmd': "FVP_VE_Cortex-A5x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA5_config.txt" } },
Device.CA7 : { 'cmd': "FVP_VE_Cortex-A7x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA7_config.txt" } },
Device.CA9 : { 'cmd': "FVP_VE_Cortex-A9x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA9_config.txt" } },
Device.CA5NEON : { 'cmd': "FVP_VE_Cortex-A5x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA5neon_config.txt" } },
Device.CA7NEON : { 'cmd': "FVP_VE_Cortex-A7x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA7neon_config.txt" } },
Device.CA9NEON : { 'cmd': "FVP_VE_Cortex-A9x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA9neon_config.txt" } }
Device.CM0 : { 'cmd': "FVP_MPS2_Cortex-M0", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM0_config.txt" } },
Device.CM0PLUS : { 'cmd': "FVP_MPS2_Cortex-M0plus", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM0plus_config.txt" } },
Device.CM3 : { 'cmd': "FVP_MPS2_Cortex-M3", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM3_config.txt" } },
Device.CM4 : { 'cmd': "FVP_MPS2_Cortex-M4", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM4_config.txt" } },
Device.CM4FP : { 'cmd': "FVP_MPS2_Cortex-M4", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM4FP_config.txt" } },
Device.CM7 : { 'cmd': "FVP_MPS2_Cortex-M7", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM7_config.txt" } },
Device.CM7SP : { 'cmd': "FVP_MPS2_Cortex-M7", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM7SP_config.txt" } },
Device.CM7DP : { 'cmd': "FVP_MPS2_Cortex-M7", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM7DP_config.txt" } },
Device.CM23 : { 'cmd': "FVP_MPS2_Cortex-M23", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM23_config.txt", 'target': "cpu0" } },
Device.CM33 : { 'cmd': "FVP_MPS2_Cortex-M33", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM33_config.txt", 'target': "cpu0" } },
Device.CM23NS : { 'cmd': "FVP_MPS2_Cortex-M23", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM23_TZ_config.txt", 'target': "cpu0" } },
Device.CM33NS : { 'cmd': "FVP_MPS2_Cortex-M33", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
Device.CM23S : { 'cmd': "FVP_MPS2_Cortex-M23", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM23_TZ_config.txt", 'target': "cpu0" } },
Device.CM33S : { 'cmd': "FVP_MPS2_Cortex-M33", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
Device.CM35P : { 'cmd': "FVP_MPS2_Cortex-M35P", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM35P_config.txt", 'target': "cpu0" } },
Device.CM35PS : { 'cmd': "FVP_MPS2_Cortex-M35P", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM35P_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
Device.CM35PNS : { 'cmd': "FVP_MPS2_Cortex-M35P", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCM35P_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
Device.CA5 : { 'cmd': "FVP_VE_Cortex-A5x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA5_config.txt" } },
Device.CA7 : { 'cmd': "FVP_VE_Cortex-A7x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA7_config.txt" } },
Device.CA9 : { 'cmd': "FVP_VE_Cortex-A9x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA9_config.txt" } },
Device.CA5NEON : { 'cmd': "FVP_VE_Cortex-A5x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA5neon_config.txt" } },
Device.CA7NEON : { 'cmd': "FVP_VE_Cortex-A7x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA7neon_config.txt" } },
Device.CA9NEON : { 'cmd': "FVP_VE_Cortex-A9x1", 'args': { 'timeout': 60, 'limit': "1000000000", 'config': "config/ARMCA9neon_config.txt" } }
}
def projects(step, config):
......
CMSIS/CoreValidation/Tests/config/ARMCM35P_DSP_FP_TZ_config.txt 0 → 100644
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------
CMSIS/CoreValidation/Tests/config/ARMCM35P_config.txt 0 → 100644
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------
CMSIS/CoreValidation/Tests/config/core_m/partition_ARMCM35P.h 0 → 100644
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− 0
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CMSIS/CoreValidation/Tests/gcc.rtebuild
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......@@ -102,6 +102,28 @@ targets:
asmflags : [ "-mfpu=${fpu}" ]
linkflags: [ "-mfpu=${fpu}" ]
linkscript: "config/core_m/rtebuild_ns.ld"
armcm35p:
arch : armv8-m.main
cpu : cortex-m33
fpu : none
float : soft
armcm35ps:
arch : armv8-m.main
cpu : cortex-m33
fpu : fpv5-sp-d16
float : hard
cflags : [ "-mfpu=${fpu}", -mcmse ]
asmflags : [ "-mfpu=${fpu}" ]
linkflags: [ "-mfpu=${fpu}" ]
armcm35pns:
arch : armv8-m.main
cpu : cortex-m33
fpu : fpv5-sp-d16
float : hard
cflags : [ "-mfpu=${fpu}" ]
asmflags : [ "-mfpu=${fpu}" ]
linkflags: [ "-mfpu=${fpu}" ]
linkscript: "config/core_m/rtebuild_ns.ld"
armca:
csettings : [ -marm ]
cflags : [ -xc, -std=gnu99, -c, "-mcpu=${cpu}", "-mfpu=${fpu}", "-mfloat-abi=${float}", "${csettings}", "${cwarnings}" ]
......
CMSIS/CoreValidation/Tests/tests.rtebuild
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− 0
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......@@ -76,6 +76,18 @@ targets:
extends: armcm_v8
device : ARMCM33
dsuffix: "_DSP_FP_TZ"
armcm35p:
extends: armcm_v8
device : ARMCM35P
dsuffix: ""
armcm35ps:
extends: armcm_v8
device : ARMCM35P
dsuffix: "_DSP_FP_TZ"
armcm35pns:
extends: armcm_v8
device : ARMCM35P
dsuffix: "_DSP_FP_TZ"
armca:
extends : arm
include:
......
CMSIS/DoxyGen/Driver/src/Driver_WiFi.c
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CMSIS/DoxyGen/Driver/src/images/WiFi.png 0 → 100644
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