Verified Commit 7efdb487 authored by theova's avatar theova Committed by Theo von Arx
Browse files

Remove pagebreaks and columnbreaks

parent 44a20ce8
......@@ -3,7 +3,6 @@
\section{Hardware Software Interface(3-1)}
\subsection{Memory}
\begin{minipage}[b]{.5\linewidth} % [b] => Ausrichtung an \caption
\includegraphics[width=\linewidth]{images/s-ram.JPG}
\captionof{figure}{S-RAM}
......@@ -95,7 +94,6 @@ volatile uint8_t* ptr = (uint8_t*) 0x40004c02;
*ptr = 0x01; // Set bit 0 to 1
\end{lstlisting}
\newpage
\subsection{Device Communication}
\subsubsection{UART (3-30)}
A UART communication consists of a Receiver and a Transmitter. \\
......@@ -154,7 +152,6 @@ $\rightarrow$ See Code implementation in the Lab section\\
\item Deadline \textbf{D}: Maximal time between event arrival and finishing
\end{itemize}
\columnbreak
\textbf{Polling}\\
Average Utilization: $\underline{u} = \frac{c}{P}$ \\
Limitation: $2c \leq c + P \leq D \leq T $ \\
......
......@@ -19,26 +19,15 @@
\vspace{-0.1cm}
\input{chapters/introduction.tex} % zrene
\newpage
\input{chapters/Chapter2.tex}
\newpage
\input{chapters/Chapter3.tex} % zrene
\newpage
\input{chapters/Chapter4.tex} %homsm
\newpage
\input{chapters/Chapter3.tex} % zrene
\input{chapters/Chapter4.tex}
\input{chapters/05_operationSystem.tex} % kuenzlij
\newpage
\input{chapters/06_aperiodicAndPeriodicScheduling.tex} % kuenzlij
\newpage
\newpage
\input{chapters/Chapter7.tex} %homsm
\newpage
\input{chapters/Chapter7.tex}
\input{chapters/systemComponents.tex}
\newpage
\input{chapters/lowPowerDesign.tex} % rene
\newpage
\input{chapters/architectureModels.tex}
\newpage
\input{chapters/architectureSynthesis.tex}
\newpage
\input{chapters/labs.tex}
......
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