Verified Commit 3f969525 authored by Theo von Arx's avatar Theo von Arx
Browse files

Add 'calculations' to UART

parent 001b5879
% !TeX root = ../main.tex
\section{Hardware Software Interface(3-1)}
\subsection{Memory}
\subsection{Memory}
\begin{minipage}[b]{.5\linewidth} % [b] => Ausrichtung an \caption
......@@ -91,24 +91,31 @@ To light it up, we have to set it's value to 1: \\
\vspace{-5mm}
\begin{lstlisting}[style=CStyle]
// Get pointer to memory mapped device
volatile uint8_t* ptr = (uint8_t*) 0x40004c02;
volatile uint8_t* ptr = (uint8_t*) 0x40004c02;
*ptr = 0x01; // Set bit 0 to 1
\end{lstlisting}
\newpage
\subsection{Device Communication}
\textbf{UART} (3-30) \\
\subsubsection{UART (3-30)}
A UART communication consists of a Receiver and a Transmitter. \\
To comunicate between Receiver and Transmitter a single wire is used \\
\textbf{Transmitter}: Contains a internal clock that is set to a given communication frequency (Baud-Rate, often 9600 Bit/s). \\
Sends a start-bit, 6-9 Data Bits, (parity bits) and 1-2 Stop bits using single wire. \\
\textbf{Receiver} Contains an internal clock that is an exact multiple of the baud-rate (8-16 times). When the start bit is received, the receiver starts counting clock cycles and reads the bit during half it's transmission. \\
Receivers detect the baud-rate based on the length of the start bit and adjust their internal clock. \\
\textbf{Calculations:}
\begin{itemize}
\item It takes 16 clock ticks to sample 1 bit\\
$\rightarrow\textnormal{Clock frequency} =
\textnormal{Baud rate} \cdot 16/ \textnormal{bits}$
\end{itemize}
\includegraphics[width=\linewidth]{images/uart.JPG}\\
\textbf{implementation}: Slide 3-37 \\
\vspace{3mm}\\
\textbf{SPI} (3-40) \\
Used in short distance communication. Contains 4 lines:
\textbf{implementation}: Slide 3-37
\subsubsection{SPI (3-40)}
Used in short distance communication. Contains 4 lines:
\begin{itemize}
\item \textbf{SCLK} Clock signal, used to synchronize communcation with slaves.
\item \textbf{MOSI} Master out Slave int: Signal line for data coming from Master unit
......@@ -119,8 +126,8 @@ Master and Slave simply consist of two shift register, with every clock cycle fr
\includegraphics[width=\linewidth]{images/spi.JPG}
\subsection{Interrupts}
Different devices can send interrupt request to the processor. In order to ignore or react to them, a controller (NVIC - Nested Vector Interrupt Controller) is used. The NVIC can mask or dis-/enable interrupts.
\\
Different devices can send interrupt request to the processor. In order to ignore or react to them, a controller (NVIC - Nested Vector Interrupt Controller) is used. The NVIC can mask or dis-/enable interrupts.
\\
It also decides which interrupt has priority and what interrupt service routine should be executed. In order to do that, it contains a vector table with an entry for each interrupt type and pointer to the code that should be executed \\
\textbf{Interrupt Execution}:
\begin{enumerate}
......@@ -133,7 +140,7 @@ It also decides which interrupt has priority and what interrupt service routine
\end{enumerate}
\textbf{Interrupt VS Polling}
\textbf{Interrupt VS Polling}
\begin{itemize}
\item Utilization \textbf{u}: average percentage the processor is busy
\item Computation \textbf{c}: processing time for the event
......@@ -163,10 +170,10 @@ $ c + max(c,h) \leq D \rightarrow \texttt{Both possible with:} u_p = \frac{c}{D-
\textbf{Watchdog Timer (3-65)} \\
A Watchdog timer is a timer that runs in the background and as soon as it rolls over, it resets the state of the CPU. \\
These timer are often used for safety purposes since it makes sure that even if a program crashed or entered a infinity loop, the processor will recover. \\
A watchdog timer must continously be reset by the application as prrof that it is still working as expected.
A watchdog timer must continously be reset by the application as prrof that it is still working as expected.
\vspace{3mm}\\
\textbf{Timers} \\
Timers are used for:
Timers are used for:
\begin{itemize}
\item Capture the current time or time differences
\item Generate interrupts when certain limits are reached
......
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