| ... | ... | @@ -13,41 +13,18 @@ The Dual Processor Platform is (DPP) is a novel architecture template for networ |
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are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements. BOLT decouples application and communication processors with respect to time, power and clock domains. BOLT supports asynchronous message passing with predictable timing characteristics, and therefore making it possible for the system designer to construct highly-customized platforms that are easier to design, implement, debug, and maintain.
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## General DPP Information
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* [Publications](Publications)
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* [BOLT Software](https://github.com/ETHZ-TEC/BOLT) (Github)
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* [Docs](https://gitlab.ethz.ch/tec/public/dpp/tree/master/docs)
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* Implementations
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* DevBoard (APP)
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* [CC430 ComBoard](./DPP2CC430) (COM)
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* [SX1262 ComBoard](./DPP2Lora) (COM)
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### General DPP Information
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* [BOLT](./BOLT)
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* [Terminology](./Terminology)
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* [Docs](https://gitlab.ethz.ch/tec/public/dpp/tree/master/docs)
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## How to Cite
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> Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, and Lothar Thiele: [Bolt: A Stateful Processor Interconnect](https://www.tik.ee.ethz.ch/file/5acae22d79f04e0e9eb1022d089029d0/SZDLGGFBT2015a.pdf). In Proceedings of the 13th ACM Conference on Embedded Networked Sensor Systems (SenSys '15), ACM, New York, NY, USA, 267-280, 2015, https://doi.org/10.1145/2809695.2809706.
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[PDF Download](https://www.tik.ee.ethz.ch/file/5acae22d79f04e0e9eb1022d089029d0/SZDLGGFBT2015a.pdf)
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### BibTeX
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```
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@inproceedings{Sutton:2015:BSP:2809695.2809706,
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author = {Sutton, Felix and Zimmerling, Marco and Da Forno, Reto and Lim, Roman and Gsell, Tonio and Giannopoulou, Georgia and Ferrari, Federico and Beutel, Jan and Thiele, Lothar},
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title = {{Bolt: A Stateful Processor Interconnect}},
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booktitle = {Proceedings of the 13th ACM Conference on Embedded Networked Sensor Systems},
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series = {SenSys '15},
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year = {2015},
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isbn = {978-1-4503-3631-4},
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location = {Seoul, South Korea},
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pages = {267--280},
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numpages = {14},
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url = {http://doi.acm.org/10.1145/2809695.2809706},
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doi = {10.1145/2809695.2809706},
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acmid = {2809706},
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publisher = {ACM},
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address = {New York, NY, USA},
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keywords = {composability, cyber-physical systems, multi-processor, predictability, processor interconnect, resource interference},
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}
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```
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### Implementations
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* [DevBoard](./DevBoard) (APP)
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* [CC430 ComBoard](./DPP2CC430) (COM)
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* [SX1262 ComBoard](./DPP2Lora) (COM)
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* [BOLT Software](https://github.com/ETHZ-TEC/BOLT) (Github)
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### Publications
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* [Publications](Publications)
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* [How to Cite DPP](./Cite)
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