... | ... | @@ -2,11 +2,9 @@ |
|
|
|
|
|
Welcome to the Dual Processor Platform Wiki, your information source for building, configuring, using and extending this wireless sensor network platform.
|
|
|
|
|
|
The Dual Processor Platform is (DPP) is a novel architecture template for networked embedded systems based on a strictly asynchronous processor interconnect that allows to minimize interference with a proven predictable behavior. Contrary to traditional platforms DPP tries to mitigate interference by isolating different tasks and mapping them onto dedicated hardware resources. Typically, two different task sets -- (i) sensing/actuation/data processing and (ii) communication - are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements.
|
|
|
The Dual Processor Platform is (DPP) is a novel architecture template for networked embedded systems based on a strictly asynchronous processor interconnect that allows to minimize interference with a proven predictable behavior. Contrary to traditional platforms DPP tries to mitigate interference by isolating different tasks and mapping them onto dedicated hardware resources. Typically, two different task sets -- (i) sensing/actuation/data processing and (ii) communication - are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements. BOLT decouples application and communication processors with respect to time, power and clock domains. BOLT supports asynchronous message passing with predictable timing characteristics, and therefore making it possible for the system designer to construct highly-customized platforms that are easier to design, implement, debug, and maintain.
|
|
|
|
|
|
BOLT decouples application and communication processors with respect to time, power and clock domains. BOLT supports asynchronous message passing with predictable timing characteristics, and therefore making it possible for the system designer to construct highly-customized platforms that are easier to design, implement, debug, and maintain.
|
|
|
|
|
|
Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, and Lothar Thiele: Bolt: A Stateful Processor Interconnect. In Proceedings of the 13th ACM Conference on Embedded Networked Sensor Systems (SenSys '15), ACM, New York, NY, USA, 267-280, 2015, https://doi.org/10.1145/2809695.2809706.
|
|
|
Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, and Lothar Thiele: [Bolt: A Stateful Processor Interconnect](https://gitlab.ethz.ch/tec/research/dpp/wiki). In Proceedings of the 13th ACM Conference on Embedded Networked Sensor Systems (SenSys '15), ACM, New York, NY, USA, 267-280, 2015, https://doi.org/10.1145/2809695.2809706.
|
|
|
|
|
|
Get the BOLT Software
|
|
|
https://github.com/ETHZ-TEC/BOLT
|
... | ... | |