diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
index 69763fbea8a6079c7b0a61e14da37a3af69dfdfb..df9d1f1e70674f7bc91460e154f4e24af08df79c 100644
--- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
+++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
@@ -1227,20 +1227,6 @@ class MatrixVectorActivation(HLSCustomOp):
self.code_gen_dict["$PRAGMAS$"].append(
"#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname()
)
- # TODO can we deprecate this entirely? this looks like legacy code
- # that does not really serve a purpose - FIFO sizes are not typically
- # allocated at this point; at best they are set to 2 as the default
- in_fifo_depth = 2
- out_fifo_depth = 2
- # insert depth pragmas only if specified
- if in_fifo_depth != 0:
- self.code_gen_dict["$PRAGMAS$"].append(
- "#pragma HLS stream depth=%d variable=in0" % in_fifo_depth
- )
- if out_fifo_depth != 0:
- self.code_gen_dict["$PRAGMAS$"].append(
- "#pragma HLS stream depth=%d variable=out" % out_fifo_depth
- )
self.code_gen_dict["$PRAGMAS$"].append(
"#pragma HLS INTERFACE ap_ctrl_none port=return"
)
diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py
index 40d016de43820a37e8c7894a3e1f30146c667e59..c71e8ffe323b1f2bb459a0f982e63d881a7ae58d 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfifo.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py
@@ -46,32 +46,34 @@ class StreamingFIFO(HLSCustomOp):
self.strm_fifo_wrapper = templates.strm_fifo_wrapper
def get_nodeattr_types(self):
- my_attrs = {
- # FIFO depth
- "depth": ("i", True, 0),
- # folded shape of input/output
- "folded_shape": ("ints", True, []),
- # FINN DataTypes for inputs/outputs
- "dataType": ("s", True, ""),
- # Toggle between hls or IPI implementation
- # rtl - use the hls generated IP during stitching
- # vivado - use the AXI Infrastructure FIFO
- "impl_style": ("s", False, "rtl", {"rtl", "vivado"}),
- # FPGA resource type for FIFOs when impl_style is vivado
- # auto -- let Vivado decide
- # block -- use BRAM
- # distributed -- use LUTRAM
- # ultra -- use URAM (on UltraScale+)
- "ram_style": (
- "s",
- False,
- "auto",
- {"auto", "block", "distributed", "ultra"},
- ),
- # whether depth monitoring is enabled (impl_style=rtl only)
- "depth_monitor": ("i", False, 0),
- }
- my_attrs.update(super().get_nodeattr_types())
+ my_attrs = super().get_nodeattr_types()
+ my_attrs.update(
+ {
+ # FIFO depth
+ "depth": ("i", True, 0),
+ # folded shape of input/output
+ "folded_shape": ("ints", True, []),
+ # FINN DataTypes for inputs/outputs
+ "dataType": ("s", True, ""),
+ # Toggle between hls or IPI implementation
+ # rtl - use the hls generated IP during stitching
+ # vivado - use the AXI Infrastructure FIFO
+ "impl_style": ("s", False, "rtl", {"rtl", "vivado"}),
+ # FPGA resource type for FIFOs when impl_style is vivado
+ # auto -- let Vivado decide
+ # block -- use BRAM
+ # distributed -- use LUTRAM
+ # ultra -- use URAM (on UltraScale+)
+ "ram_style": (
+ "s",
+ False,
+ "auto",
+ {"auto", "block", "distributed", "ultra"},
+ ),
+ # whether depth monitoring is enabled (impl_style=rtl only)
+ "depth_monitor": ("i", False, 0),
+ }
+ )
return my_attrs
@@ -256,6 +258,12 @@ class StreamingFIFO(HLSCustomOp):
in_width = folded_shape[-1] * dtype.bitwidth()
return in_width
+ def get_input_datatype(self, ind=0):
+ return DataType[self.get_nodeattr("dataType")]
+
+ def get_output_datatype(self, ind=0):
+ return DataType[self.get_nodeattr("dataType")]
+
def execute_node(self, context, graph):
mode = self.get_nodeattr("exec_mode")
node = self.onnx_node
diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
index 16a51a3c909c76497bd8b60c372c589b441a1f01..da99da2e023eb364765339370850f9fa383dd1bc 100644
--- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
+++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
@@ -917,20 +917,6 @@ class VectorVectorActivation(HLSCustomOp):
self.code_gen_dict["$PRAGMAS$"].append(
"#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname()
)
- # TODO can we deprecate this entirely? this looks like legacy code
- # that does not really serve a purpose - FIFO sizes are not typically
- # allocated at this point; at best they are set to 2 as the default
- in_fifo_depth = 2
- out_fifo_depth = 2
- # insert depth pragmas only if specified
- if in_fifo_depth != 0:
- self.code_gen_dict["$PRAGMAS$"].append(
- "#pragma HLS stream depth=%d variable=in0" % in_fifo_depth
- )
- if out_fifo_depth != 0:
- self.code_gen_dict["$PRAGMAS$"].append(
- "#pragma HLS stream depth=%d variable=out" % out_fifo_depth
- )
self.code_gen_dict["$PRAGMAS$"].append(
"#pragma HLS INTERFACE ap_ctrl_none port=return"
)
diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py
index 4b4eb6362faf641def057afadfa7b5e019f54698..28bcd9598af34072cc854fdf23778bef778bd985 100644
--- a/src/finn/transformation/fpgadataflow/insert_iodma.py
+++ b/src/finn/transformation/fpgadataflow/insert_iodma.py
@@ -211,7 +211,8 @@ class InsertIODMA(Transformation):
# attached IODMA
fc_extw_nodes = list(
filter(
- lambda x: x.op_type == "MatrixVectorActivation"
+ lambda x: x.op_type
+ in ["MatrixVectorActivation", "VectorVectorActivation"]
and getCustomOp(x).get_nodeattr("mem_mode") == "external"
and model.find_producer(x.input[1]) is None,
all_nodes,
@@ -259,6 +260,10 @@ class InsertIODMA(Transformation):
)
fc_node.input[1] = fc_node_in.name
model.graph.node.insert(0, dma_node)
+ # expand inFIFODepths for new second input of node
+ infifo_depth = fc_inst.get_nodeattr("inFIFODepths")
+ infifo_depth.append(8)
+ fc_inst.set_nodeattr("inFIFODepths", infifo_depth)
modified = True
if modified:
model = model.transform(SortGraph())