From fbcd29c3fe553bc20ead1e854551a6540db1cf6c Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 29 Apr 2020 13:47:30 +0100
Subject: [PATCH] [Fclk] set default frequency to 100 MHz throughout the
project
this will be replaced by a metadata_prop in the near future
---
notebooks/end2end_example/tfc_end2end_example.ipynb | 2 +-
src/finn/transformation/fpgadataflow/codegen_ipstitch.py | 3 ++-
src/finn/transformation/fpgadataflow/make_pynq_proj.py | 2 +-
tests/end2end/test_end2end_cnv_w1a1.py | 2 +-
tests/end2end/test_end2end_tfc_w1a1_throughput_test.py | 2 +-
tests/end2end/test_end2end_tfc_w1a2.py | 2 +-
tests/end2end/test_end2end_tfc_w2a2.py | 2 +-
tests/fpgadataflow/test_fpgadataflow_fifo.py | 2 +-
8 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/notebooks/end2end_example/tfc_end2end_example.ipynb b/notebooks/end2end_example/tfc_end2end_example.ipynb
index 2f8e0207f..a976fb6f7 100644
--- a/notebooks/end2end_example/tfc_end2end_example.ipynb
+++ b/notebooks/end2end_example/tfc_end2end_example.ipynb
@@ -910,7 +910,7 @@
"# change this if you have a different PYNQ board, see list above\n",
"pynq_board = \"Pynq-Z1\"\n",
"fpga_part = pynq_part_map[pynq_board]\n",
- "target_clk_ns = 5"
+ "target_clk_ns = 10"
]
},
{
diff --git a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
index 388e1b364..bc1fce836 100644
--- a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
+++ b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
@@ -147,7 +147,8 @@ class CodeGen_ipstitch(Transformation):
tcl.append('create_bd_design "%s"' % block_name)
tcl.extend(create_cmds)
tcl.extend(connect_cmds)
- fclk_hz = 150 * 1000000
+ # TODO get from Transformation arg or metadata_prop
+ fclk_hz = 100 * 1000000
tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk_0]" % fclk_hz)
tcl.append("regenerate_bd_layout")
tcl.append("validate_bd_design")
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 981057b26..9fe5781ec 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -111,7 +111,7 @@ class MakePYNQProject(Transformation):
axi_lite_if_name = "s_axi_control_0"
vivado_ip_cache = os.getenv("VIVADO_IP_CACHE", default="")
# TODO get from Transformation arg or metadata_prop
- fclk_mhz = 150.0
+ fclk_mhz = 100.0
# create a temporary folder for the project
vivado_pynq_proj_dir = make_build_dir(prefix="vivado_pynq_proj_")
diff --git a/tests/end2end/test_end2end_cnv_w1a1.py b/tests/end2end/test_end2end_cnv_w1a1.py
index d0571aec4..ecde18e38 100644
--- a/tests/end2end/test_end2end_cnv_w1a1.py
+++ b/tests/end2end/test_end2end_cnv_w1a1.py
@@ -76,7 +76,7 @@ from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 5
+target_clk_ns = 10
mem_mode = "const"
diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index bed17ee85..0c912a137 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -78,7 +78,7 @@ from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 5
+target_clk_ns = 10
mem_mode = "decoupled"
diff --git a/tests/end2end/test_end2end_tfc_w1a2.py b/tests/end2end/test_end2end_tfc_w1a2.py
index f3dd83826..f4b5de21f 100644
--- a/tests/end2end/test_end2end_tfc_w1a2.py
+++ b/tests/end2end/test_end2end_tfc_w1a2.py
@@ -72,7 +72,7 @@ from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 5
+target_clk_ns = 10
mem_mode = "decoupled"
diff --git a/tests/end2end/test_end2end_tfc_w2a2.py b/tests/end2end/test_end2end_tfc_w2a2.py
index 3aa1fd031..10d4bcdf7 100644
--- a/tests/end2end/test_end2end_tfc_w2a2.py
+++ b/tests/end2end/test_end2end_tfc_w2a2.py
@@ -72,7 +72,7 @@ from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 5
+target_clk_ns = 10
mem_mode = "decoupled"
diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py
index ef456142d..ab628bd77 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fifo.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py
@@ -30,7 +30,7 @@ from finn.util.basic import pynq_part_map
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 5
+target_clk_ns = 10
def make_single_fifo_modelwrapper(Shape, Depth, fld_shape, finn_dtype):
--
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