From f7d38d7d84687fdd9e9be388992dc22389b8c1e5 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Tue, 12 May 2020 11:04:55 +0100
Subject: [PATCH] [Transformation] Change input argument from frequency in MHz
to clock period in ns
---
.../fpgadataflow/create_stitched_ip.py | 15 +++++++++++----
.../transformation/fpgadataflow/make_pynq_proj.py | 11 +++++++++--
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index df9700d71..9b0a387c5 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -27,6 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
+import warnings
import subprocess
from finn.transformation import Transformation
@@ -48,10 +49,15 @@ class CreateStitchedIP(Transformation):
The packaged block design IP can be found under the ip subdirectory.
"""
- def __init__(self, fpgapart, fclk_mhz):
+ def __init__(self, fpgapart, clk_ns):
super().__init__()
self.fpgapart = fpgapart
- self.fclk_mhz = fclk_mhz
+ self.clk_ns = clk_ns
+ if float(clk_ns) not in [5.0, 10.0, 20.0]:
+ warnings.warn(
+ """The chosen frequency may lead to failure due to clock divider
+ constraints."""
+ )
def apply(self, model):
ip_dirs = ["list"]
@@ -148,8 +154,9 @@ class CreateStitchedIP(Transformation):
tcl.append('create_bd_design "%s"' % block_name)
tcl.extend(create_cmds)
tcl.extend(connect_cmds)
- fclk_hz = self.fclk_mhz * 1000000
- model.set_metadata_prop("fclk_MHz", str(self.fclk_mhz))
+ fclk_mhz = 1 / (self.clk_ns * 0.001)
+ fclk_hz = fclk_mhz * 1000000
+ model.set_metadata_prop("clk_ns", str(self.clk_ns))
tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk_0]" % fclk_hz)
tcl.append("regenerate_bd_layout")
tcl.append("validate_bd_design")
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 4a0ab7121..91f6bd2c4 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -27,6 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
+import warnings
import subprocess
from finn.custom_op.registry import getCustomOp
@@ -118,8 +119,14 @@ class MakePYNQProject(Transformation):
synth_report_filename = vivado_pynq_proj_dir + "/synth_report.xml"
model.set_metadata_prop("vivado_synth_rpt", synth_report_filename)
- # get metadata property for clock frequency
- fclk_mhz = float(model.get_metadata_prop("fclk_MHz"))
+ # get metadata property clk_ns to calculate clock frequency
+ clk_ns = float(model.get_metadata_prop("clk_ns"))
+ if clk_ns not in [5.0, 10.0, 20.0]:
+ warnings.warn(
+ """The chosen frequency may lead to failure due to clock divider
+ constraints."""
+ )
+ fclk_mhz = 1 / (clk_ns * 0.001)
ip_config_tcl = templates.ip_config_tcl_template % (
vivado_pynq_proj_dir,
--
GitLab