diff --git a/finn-rtllib/axi_info/axi_info_tb.sv b/finn-rtllib/axi_info/axi_info_tb.sv
deleted file mode 100644
index 6b9442374a5c20671b1dff122c1566056183a2b0..0000000000000000000000000000000000000000
--- a/finn-rtllib/axi_info/axi_info_tb.sv
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2022, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * @brief Read-only exposure of compiled-in info data on AXI-lite.
- * @author Thomas B. Preußer <tpreusse@amd.com>
- *
- *******************************************************************************/
-module axi_info_tb #(
- int unsigned N = 9,
- int unsigned S_AXI_DATA_WIDTH = 32,
- bit [S_AXI_DATA_WIDTH-1:0] DATA[N] = '{
- 32'h2437_9827,
- 32'ha639_bf83,
- 32'haec2_3ab1,
- 32'h5ab3_2b97,
- 32'hff1c_4e78,
- 32'h10c2_4968,
- 32'h4537_a1ec,
- 32'h694b_63d1,
- 32'h7f77_9af9
- }
-)();
-
- //- Global Control ------------------
- logic ap_clk = 0;
- always #5ns ap_clk = !ap_clk;
- logic ap_rst_n = 1;
-
- //- AXI Lite ------------------------
- // Writing
- uwire s_axi_AWVALID = 0;
- uwire s_axi_AWREADY;
- uwire [$clog2(N)-1:0] s_axi_AWADDR = 'x;
-
- uwire s_axi_WVALID = 0;
- uwire s_axi_WREADY;
- uwire [S_AXI_DATA_WIDTH -1:0] s_axi_WDATA = 'x;
- uwire [S_AXI_DATA_WIDTH/8-1:0] s_axi_WSTRB = 'x;
-
- uwire s_axi_BVALID;
- uwire s_axi_BREADY = 0;
- uwire [1:0] s_axi_BRESP;
-
- // Reading
- logic s_axi_ARVALID;
- uwire s_axi_ARREADY;
- logic [$clog2(N)-1:0] s_axi_ARADDR;
-
- uwire s_axi_RVALID;
- logic s_axi_RREADY = 0;
- uwire [S_AXI_DATA_WIDTH-1:0] s_axi_RDATA;
- uwire [ 1:0] s_axi_RRESP;
-
- axi_info #(.N(N), .S_AXI_DATA_WIDTH(S_AXI_DATA_WIDTH), .DATA(DATA)) dut (
- .ap_clk, .ap_rst_n,
-
- .s_axi_AWVALID, .s_axi_AWREADY, .s_axi_AWADDR,
- .s_axi_WVALID, .s_axi_WREADY, .s_axi_WDATA, .s_axi_WSTRB,
- .s_axi_BVALID, .s_axi_BREADY, .s_axi_BRESP,
-
- .s_axi_ARVALID, .s_axi_ARREADY, .s_axi_ARADDR,
- .s_axi_RVALID, .s_axi_RREADY, .s_axi_RDATA, .s_axi_RRESP
- );
-
- //-----------------------------------------------------------------------
- // Read address feed
- initial begin
- s_axi_ARVALID = 0;
- s_axi_ARADDR = 'x;
- @(posedge ap_clk iff ap_rst_n);
- for(int unsigned i = 0; i < N; i++) begin
- repeat($urandom()%3 > 0);
- s_axi_ARVALID <= 1;
- s_axi_ARADDR <= i;
- @(posedge ap_clk iff s_axi_ARREADY);
- s_axi_ARVALID <= 0;
- s_axi_ARADDR <= 'x;
- end
- end
-
- //-----------------------------------------------------------------------
- // Read reply check
- always_ff @(posedge ap_clk) begin
- static int Cnt = 0;
- if(!ap_rst_n) begin
- s_axi_RREADY <= 0;
- Cnt = 0;
- end
- else begin
- if(s_axi_RVALID || !s_axi_RREADY) s_axi_RREADY <= $urandom()%7 > 2;
- if(s_axi_RVALID && s_axi_RREADY) begin
- assert(s_axi_RRESP === 2'b00) else begin
- $error("AXI read error indicator: %0d", s_axi_RRESP);
- $stop;
- end
- assert(s_axi_RDATA === DATA[Cnt]) else begin
- $error("Unexpected read reply: 0x%08x instead of 0x%08x", s_axi_RDATA, DATA[Cnt]);
- $stop;
- end
- if(++Cnt == N) $finish;
- end
- end
- end
-
-endmodule : axi_info_tb
diff --git a/finn-rtllib/axi_info/component.xml b/finn-rtllib/axi_info/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..73327a2c2ed2c6ca9d5653e8b829b98d684875fa
--- /dev/null
+++ b/finn-rtllib/axi_info/component.xml
@@ -0,0 +1,717 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>AMD</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>axi_info_top</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>s_axi</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_AWADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_AWVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_AWREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_WDATA</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_WSTRB</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_WVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_WREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_BRESP</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_BVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_BREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_ARADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_ARVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_ARREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_RDATA</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_RRESP</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_RVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_RREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ap_rst_n</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ap_rst_n</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ap_clk</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ap_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:memoryMaps>
+ <spirit:memoryMap>
+ <spirit:name>s_axi</spirit:name>
+ <spirit:displayName>s_axi</spirit:displayName>
+ <spirit:addressBlock>
+ <spirit:name>reg0</spirit:name>
+ <spirit:displayName>reg0</spirit:displayName>
+ <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
+ <spirit:range spirit:format="long" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
+ <spirit:width spirit:format="long">32</spirit:width>
+ <spirit:usage>register</spirit:usage>
+ </spirit:addressBlock>
+ </spirit:memoryMap>
+ </spirit:memoryMaps>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>SystemVerilog</spirit:language>
+ <spirit:modelName>axi_info_top</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>d5974301</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>SystemVerilog</spirit:language>
+ <spirit:modelName>axi_info_top</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>d5974301</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>e11f9727</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>ap_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ap_rst_n</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_AWVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_AWREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_AWADDR</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">4</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_WVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_WREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_WDATA</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_WSTRB</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_BVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_BREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_BRESP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_ARVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_ARREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_ARADDR</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">4</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_RVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_RREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_RDATA</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s_axi_RRESP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ <spirit:modelParameters>
+ <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="bit(31 0)">
+ <spirit:name>SIG_CUSTOMER</spirit:name>
+ <spirit:displayName>Sig Customer</spirit:displayName>
+ <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.SIG_CUSTOMER">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="bit(31 0)">
+ <spirit:name>SIG_APPLICATION</spirit:name>
+ <spirit:displayName>Sig Application</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.SIG_APPLICATION">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="bit(31 0)">
+ <spirit:name>VERSION</spirit:name>
+ <spirit:displayName>Version</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.VERSION">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="bit(31 0)">
+ <spirit:name>CHECKSUM_COUNT</spirit:name>
+ <spirit:displayName>Checksum Count</spirit:displayName>
+ <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.CHECKSUM_COUNT">0</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_9d8b0d81</spirit:name>
+ <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/axi_info.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/axi_info_top.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_ec9ff0da</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/axi_info.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/axi_info_top.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>xgui/axi_info_top_v1_0.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_e11f9727</spirit:userFileType>
+ <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>axi_info_top_v1_0</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>SIG_CUSTOMER</spirit:name>
+ <spirit:displayName>Sig Customer</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIG_CUSTOMER" spirit:bitStringLength="0" spirit:minimum="0" spirit:maximum="4294967295" spirit:rangeType="long">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:presence>required</xilinx:presence>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SIG_APPLICATION</spirit:name>
+ <spirit:displayName>Sig Application</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIG_APPLICATION" spirit:minimum="0" spirit:maximum="4294967295" spirit:rangeType="long">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>VERSION</spirit:name>
+ <spirit:displayName>Version</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VERSION" spirit:minimum="0" spirit:maximum="4294967295" spirit:rangeType="long">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CHECKSUM_COUNT</spirit:name>
+ <spirit:displayName>Checksum Count</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CHECKSUM_COUNT" spirit:minimum="0" spirit:maximum="4294967295" spirit:rangeType="long">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_info_top_v1_0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:supportedFamilies>
+ <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+ </xilinx:supportedFamilies>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>axi_info_top_v1_0</xilinx:displayName>
+ <xilinx:definitionSource>package_project</xilinx:definitionSource>
+ <xilinx:coreRevision>1</xilinx:coreRevision>
+ <xilinx:upgrades>
+ <xilinx:canUpgradeFrom>user.org:user:axi_info_top:1.0</xilinx:canUpgradeFrom>
+ </xilinx:upgrades>
+ <xilinx:coreCreationDateTime>2022-05-23T14:45:24Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="nopcore"/>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b801346c"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="035d612e"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a17a38ba"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="bd3646cb"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="45997f53"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="b2483324"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/finn-rtllib/axi_info/axi_info.sv b/finn-rtllib/axi_info/hdl/axi_info.sv
similarity index 96%
rename from finn-rtllib/axi_info/axi_info.sv
rename to finn-rtllib/axi_info/hdl/axi_info.sv
index e4bfc01011d4e39c50d3f39dfd2017bc632a27b4..d71877c46427151fa7b0b5313b3c257e3ab4f44d 100644
--- a/finn-rtllib/axi_info/axi_info.sv
+++ b/finn-rtllib/axi_info/hdl/axi_info.sv
@@ -45,7 +45,7 @@ module axi_info #(
// Writing
input logic s_axi_AWVALID,
output logic s_axi_AWREADY,
- input logic [$clog2(N)-1:0] s_axi_AWADDR,
+ input logic [$clog2(N)+1:0] s_axi_AWADDR,
input logic s_axi_WVALID,
output logic s_axi_WREADY,
@@ -59,7 +59,7 @@ module axi_info #(
// Reading
input logic s_axi_ARVALID,
output logic s_axi_ARREADY,
- input logic [$clog2(N)-1:0] s_axi_ARADDR,
+ input logic [$clog2(N)+1:0] s_axi_ARADDR,
output logic s_axi_RVALID,
input logic s_axi_RREADY,
@@ -108,7 +108,7 @@ module axi_info #(
else if(s_axi_ARREADY) begin
RValid <= s_axi_ARVALID;
if(s_axi_ARADDR < N) begin
- RData <= DATA[s_axi_ARADDR];
+ RData <= DATA[s_axi_ARADDR[$left(s_axi_ARADDR):2]];
RResp <= '0; // OKAY
end
else begin
diff --git a/finn-rtllib/axi_info/hdl/axi_info_top.sv b/finn-rtllib/axi_info/hdl/axi_info_top.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5d27bb0c032cf0f58b78f93e5d2da68a2614a710
--- /dev/null
+++ b/finn-rtllib/axi_info/hdl/axi_info_top.sv
@@ -0,0 +1,95 @@
+/******************************************************************************
+ * Copyright (c) 2022, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <tpreusse@amd.com>
+ *
+ *******************************************************************************/
+module axi_info_top #(
+ bit [31:0] SIG_CUSTOMER,
+ bit [31:0] SIG_APPLICATION,
+ bit [31:0] VERSION,
+ bit [31:0] CHECKSUM_COUNT
+)(
+ //- Global Control ------------------
+ input logic ap_clk,
+ input logic ap_rst_n,
+
+ //- AXI Lite ------------------------
+ // Writing
+ input logic s_axi_AWVALID,
+ output logic s_axi_AWREADY,
+ input logic [4:0] s_axi_AWADDR,
+
+ input logic s_axi_WVALID,
+ output logic s_axi_WREADY,
+ input logic [31:0] s_axi_WDATA,
+ input logic [ 3:0] s_axi_WSTRB,
+
+ output logic s_axi_BVALID,
+ input logic s_axi_BREADY,
+ output logic [1:0] s_axi_BRESP,
+
+ // Reading
+ input logic s_axi_ARVALID,
+ output logic s_axi_ARREADY,
+ input logic [4:0] s_axi_ARADDR,
+
+ output logic s_axi_RVALID,
+ input logic s_axi_RREADY,
+ output logic [31:0] s_axi_RDATA,
+ output logic [ 1:0] s_axi_RRESP
+);
+
+ axi_info #(
+ .N(6),
+ .S_AXI_DATA_WIDTH(32),
+ .DATA('{
+ 32'h4649_4E4E,
+ SIG_CUSTOMER,
+ SIG_CUSTOMER,
+ VERSION,
+ 32'h0,
+ CHECKSUM_COUNT
+ })
+ )(
+ //- Global Control ------------------
+ .ap_clk, .ap_rst_n,
+
+ //- AXI Lite ------------------------
+ // Writing
+ .s_axi_AWVALID, .s_axi_AWREADY, .s_axi_AWADDR,
+ .s_axi_WVALID, .s_axi_WREADY, .s_axi_WDATA, .s_axi_WSTRB,
+ .s_axi_BVALID, .s_axi_BREADY, .s_axi_BRESP,
+ // Reading
+ .s_axi_ARVALID, .s_axi_ARREADY, .s_axi_ARADDR,
+ .s_axi_RVALID, .s_axi_RREADY, .s_axi_RDATA, .s_axi_RRESP
+ );
+
+endmodule : axi_info_top
diff --git a/finn-rtllib/axi_info/xgui/axi_info_top_v1_0.tcl b/finn-rtllib/axi_info/xgui/axi_info_top_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..22ae5a71538ca0f5983ec0adf6f75d1bdfbd4f72
--- /dev/null
+++ b/finn-rtllib/axi_info/xgui/axi_info_top_v1_0.tcl
@@ -0,0 +1,70 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "CHECKSUM_COUNT" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "SIG_APPLICATION" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "SIG_CUSTOMER" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "VERSION" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.CHECKSUM_COUNT { PARAM_VALUE.CHECKSUM_COUNT } {
+ # Procedure called to update CHECKSUM_COUNT when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CHECKSUM_COUNT { PARAM_VALUE.CHECKSUM_COUNT } {
+ # Procedure called to validate CHECKSUM_COUNT
+ return true
+}
+
+proc update_PARAM_VALUE.SIG_APPLICATION { PARAM_VALUE.SIG_APPLICATION } {
+ # Procedure called to update SIG_APPLICATION when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SIG_APPLICATION { PARAM_VALUE.SIG_APPLICATION } {
+ # Procedure called to validate SIG_APPLICATION
+ return true
+}
+
+proc update_PARAM_VALUE.SIG_CUSTOMER { PARAM_VALUE.SIG_CUSTOMER } {
+ # Procedure called to update SIG_CUSTOMER when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SIG_CUSTOMER { PARAM_VALUE.SIG_CUSTOMER } {
+ # Procedure called to validate SIG_CUSTOMER
+ return true
+}
+
+proc update_PARAM_VALUE.VERSION { PARAM_VALUE.VERSION } {
+ # Procedure called to update VERSION when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.VERSION { PARAM_VALUE.VERSION } {
+ # Procedure called to validate VERSION
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.SIG_CUSTOMER { MODELPARAM_VALUE.SIG_CUSTOMER PARAM_VALUE.SIG_CUSTOMER } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.SIG_CUSTOMER}] ${MODELPARAM_VALUE.SIG_CUSTOMER}
+}
+
+proc update_MODELPARAM_VALUE.SIG_APPLICATION { MODELPARAM_VALUE.SIG_APPLICATION PARAM_VALUE.SIG_APPLICATION } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.SIG_APPLICATION}] ${MODELPARAM_VALUE.SIG_APPLICATION}
+}
+
+proc update_MODELPARAM_VALUE.VERSION { MODELPARAM_VALUE.VERSION PARAM_VALUE.VERSION } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.VERSION}] ${MODELPARAM_VALUE.VERSION}
+}
+
+proc update_MODELPARAM_VALUE.CHECKSUM_COUNT { MODELPARAM_VALUE.CHECKSUM_COUNT PARAM_VALUE.CHECKSUM_COUNT } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.CHECKSUM_COUNT}] ${MODELPARAM_VALUE.CHECKSUM_COUNT}
+}
+