From f673382030364a296c2748769376dc7f5ff954be Mon Sep 17 00:00:00 2001
From: patrickg <44997541+patrickgeel@users.noreply.github.com>
Date: Wed, 14 Sep 2022 17:12:09 +0200
Subject: [PATCH] Changes to make
---
fetch-repos.sh | 3 +++
src/finn/transformation/fpgadataflow/templates.py | 3 +++
src/finn/util/basic.py | 4 ++--
src/finn/util/platforms.py | 2 ++
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/fetch-repos.sh b/fetch-repos.sh
index 2dd5e5193..9130c183a 100755
--- a/fetch-repos.sh
+++ b/fetch-repos.sh
@@ -37,6 +37,7 @@ OMX_COMMIT="d1065a788219ca0eb54d5e57600b1f9d7f67d4cc"
AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b"
XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e"
EXP_BOARD_FILES_MD5="30eecc497c31050bd46d10ea20eba232"
+# TODO: KV260 ADD commit version
QONNX_URL="https://github.com/fastmachinelearning/qonnx.git"
FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git"
@@ -47,6 +48,8 @@ HLSLIB_URL="https://github.com/Xilinx/finn-hlslib.git"
OMX_URL="https://github.com/maltanar/oh-my-xilinx.git"
AVNET_BDF_URL="https://github.com/Avnet/bdf.git"
XIL_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git"
+# TODO: KV260 ADD KV260 board downloads
+
QONNX_DIR="qonnx"
FINN_EXP_DIR="finn-experimental"
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index 78bcdea0d..0554a9cc8 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -126,6 +126,9 @@ if {$BOARD == "ZCU104"} {
} elseif {$BOARD == "Pynq-Z1"} {
set ZYNQ_TYPE "zynq_7000"
set_property board_part www.digilentinc.com:pynq-z1:part0:1.0 [current_project]
+} elseif {$BOARD == "kv260_som"} {
+ set ZYNQ_TYPE "zynq_us+"
+ set_property board_part xilinx.com:kv260_som:part0:1.3 [current_project]
} else {
puts "Unrecognized board"
}
diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py
index 960b7f7c8..3bc5b803d 100644
--- a/src/finn/util/basic.py
+++ b/src/finn/util/basic.py
@@ -40,7 +40,7 @@ pynq_part_map["ZCU102"] = "xczu9eg-ffvb1156-2-e"
pynq_part_map["ZCU104"] = "xczu7ev-ffvc1156-2-e"
pynq_part_map["ZCU111"] = "xczu28dr-ffvg1517-2-e"
pynq_part_map["RFSoC2x2"] = "xczu28dr-ffvg1517-2-e"
-pynq_part_map["kv260_som"] = "SK-KV260-G"
+pynq_part_map["KV260_SOM"] = "xck26-sfvc784-2LV-c"
# native AXI HP port width (in bits) for PYNQ boards
@@ -52,7 +52,7 @@ pynq_native_port_width["ZCU102"] = 128
pynq_native_port_width["ZCU104"] = 128
pynq_native_port_width["ZCU111"] = 128
pynq_native_port_width["RFSoC2x2"] = 128
-pynq_native_port_width["kv260_som"] = 128
+pynq_native_port_width["KV260_SOM"] = 128
# Alveo device and platform mappings
alveo_part_map = dict()
diff --git a/src/finn/util/platforms.py b/src/finn/util/platforms.py
index 8212cb571..ad8604f46 100644
--- a/src/finn/util/platforms.py
+++ b/src/finn/util/platforms.py
@@ -467,6 +467,7 @@ class Alveo_NxU280_Platform(Platform):
]
+# TODO: ADD KV260 to platform list
platforms = dict()
platforms["U50"] = Alveo_NxU50_Platform
platforms["U200"] = Alveo_NxU200_Platform
@@ -478,3 +479,4 @@ platforms["Ultra96"] = ZU3EG_Platform
platforms["ZCU104"] = ZU7EV_Platform
platforms["ZCU102"] = ZU9EG_Platform
platforms["ZCU111"] = ZU28DR_Platform
+# platforms["kv260_som"] = # TODO kv260 platform... xck26_
\ No newline at end of file
--
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