From f1bd8ebf00f7468191e25ae25648512c2c7bc18c Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Tue, 6 Oct 2020 23:25:13 +0200
Subject: [PATCH] [Test] ensure impl_style=rtl for FIFOs before stitching
---
tests/end2end/test_end2end_bnn_pynq.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py
index 30bcddb28..c81e3f9e6 100644
--- a/tests/end2end/test_end2end_bnn_pynq.py
+++ b/tests/end2end/test_end2end_bnn_pynq.py
@@ -472,6 +472,9 @@ class TestEnd2End:
model = model.transform(AnnotateCycles())
perf = model.analysis(dataflow_performance)
latency = perf["critical_path_cycles"]
+ # rtlsim only supports impl_style=rtl for StreamingFIFO, ensure that
+ for fifo_layer in model.get_nodes_by_op_type("StreamingFIFO"):
+ getCustomOp(fifo_layer).set_nodeattr("impl_style", "rtl")
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynthIP())
model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
--
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