From ee57c98ce644585ee720f3d2a268f73ab92792c3 Mon Sep 17 00:00:00 2001
From: Lucian Petrica <lucianp@xilinx.com>
Date: Fri, 9 Oct 2020 16:53:38 +0100
Subject: [PATCH] Added AXILite interface for writing weights; tested in
behavioural sim with 1 stream
---
finn-rtllib/memstream/component.xml | 675 ++++++++++++++++--
finn-rtllib/memstream/hdl/axilite_if.v | 201 ++++++
finn-rtllib/memstream/hdl/memstream.v | 92 ++-
.../memstream/hdl/memstream_multiblock.v | 3 +
.../memstream/hdl/memstream_singleblock.v | 17 +-
.../memstream/sim/tb_memstream_writes.v | 497 +++++++++++++
finn-rtllib/memstream/sim/test.sh | 3 +-
finn-rtllib/memstream/xgui/memstream_v1_0.tcl | 28 +-
8 files changed, 1445 insertions(+), 71 deletions(-)
create mode 100644 finn-rtllib/memstream/hdl/axilite_if.v
create mode 100644 finn-rtllib/memstream/sim/tb_memstream_writes.v
mode change 100644 => 100755 finn-rtllib/memstream/sim/test.sh
diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml
index 14af16103..3d6767abf 100644
--- a/finn-rtllib/memstream/component.xml
+++ b/finn-rtllib/memstream/component.xml
@@ -68,6 +68,13 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_1" xilinx:dependency="$NSTREAMS>=2">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>m_axis_2</spirit:name>
@@ -100,6 +107,13 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_2" xilinx:dependency="$NSTREAMS>=3">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>m_axis_3</spirit:name>
@@ -132,6 +146,13 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_3" xilinx:dependency="$NSTREAMS>=4">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>m_axis_4</spirit:name>
@@ -164,6 +185,13 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_4" xilinx:dependency="$NSTREAMS>=5">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>m_axis_5</spirit:name>
@@ -196,6 +224,182 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_5" xilinx:dependency="$NSTREAMS = 6">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>s_axilite</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="interface_aximm"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>awprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>arprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axilite" xilinx:dependency="$CONFIG_EN = 1">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>aresetn</spirit:name>
@@ -237,7 +441,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis_0:m_axis_1:m_axis_2:m_axis_3:m_axis_4:m_axis_5</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis_0:m_axis_1:m_axis_2:m_axis_3:m_axis_4:m_axis_5:s_axilite</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
@@ -246,6 +450,18 @@
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
+ <spirit:memoryMaps>
+ <spirit:memoryMap>
+ <spirit:name>interface_aximm</spirit:name>
+ <spirit:addressBlock>
+ <spirit:name>reg0</spirit:name>
+ <spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
+ <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1) + 1)" spirit:minimum="4096" spirit:rangeType="long">65536</spirit:range>
+ <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
+ <spirit:usage>register</spirit:usage>
+ </spirit:addressBlock>
+ </spirit:memoryMap>
+ </spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
@@ -260,7 +476,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>3c30c4ac</spirit:value>
+ <spirit:value>1fc5a310</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -276,7 +492,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>00b5320e</spirit:value>
+ <spirit:value>d02d9990</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -290,7 +506,21 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>d714c73b</spirit:value>
+ <spirit:value>f960907f</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_utilityxitfiles</spirit:name>
+ <spirit:displayName>Utility XIT/TTCL</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>d2aad2c5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -323,11 +553,40 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>config_address</spirit:name>
+ <spirit:name>awready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>awvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>awaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -337,12 +596,35 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>config_ce</spirit:name>
+ <spirit:name>awprot</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>wready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -353,7 +635,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>config_we</spirit:name>
+ <spirit:name>wvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -363,10 +645,13 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>config_d0</spirit:name>
+ <spirit:name>wdata</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -380,10 +665,194 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>wstrb</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>bready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>bvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>bresp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>arready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>arvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>araddr</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">15</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>arprot</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rresp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>config_q0</spirit:name>
+ <spirit:name>rdata</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -410,7 +879,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_0_afull" xilinx:dependency="$NSTREAMS>2">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:name>m_axis_0_tready</spirit:name>
@@ -446,7 +925,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM0_WIDTH')) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM0_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -469,7 +948,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_1_afull" xilinx:dependency="$NSTREAMS>2">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:name>m_axis_1_tready</spirit:name>
@@ -505,7 +994,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM1_WIDTH')) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM1_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -528,7 +1017,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_2_afull" xilinx:dependency="$NSTREAMS>=3">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:name>m_axis_2_tready</spirit:name>
@@ -564,7 +1063,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM2_WIDTH')) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM2_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -587,7 +1086,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_3_afull" xilinx:dependency="$NSTREAMS>=4">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:name>m_axis_3_tready</spirit:name>
@@ -623,7 +1132,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM3_WIDTH')) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM3_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -646,7 +1155,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_4_afull" xilinx:dependency="$NSTREAMS>=5">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:name>m_axis_4_tready</spirit:name>
@@ -682,7 +1201,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM4_WIDTH')) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM4_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -705,7 +1224,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_5_afull" xilinx:dependency="$NSTREAMS = 6">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
<spirit:name>m_axis_5_tready</spirit:name>
@@ -741,7 +1270,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STRM5_WIDTH')) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM5_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -758,7 +1287,7 @@
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>CONFIG_EN</spirit:name>
<spirit:displayName>Config En</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONFIG_EN">1</spirit:value>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONFIG_EN">true</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>NSTREAMS</spirit:name>
@@ -875,90 +1404,103 @@
<spirit:displayName>Strm5 Offset</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM5_OFFSET">11520</spirit:value>
</spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>AXILITE_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>Axilite Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_ADDR_WIDTH" spirit:dependency="(2 + spirit:ceil(spirit:log(2,(spirit:decode(id('MODELPARAM_VALUE.MEM_DEPTH')) * (1 << spirit:ceil(spirit:log(2,((spirit:decode(id('MODELPARAM_VALUE.MEM_WIDTH')) + 31) / 32))))))))">16</spirit:value>
+ </spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
- <spirit:choice>
- <spirit:name>choice_list_44c459b8</spirit:name>
- <spirit:enumeration>auto</spirit:enumeration>
- <spirit:enumeration>block</spirit:enumeration>
- <spirit:enumeration>distributed</spirit:enumeration>
- </spirit:choice>
<spirit:choice>
<spirit:name>choice_list_9d8b0d81</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_e2bd1cd0</spirit:name>
+ <spirit:enumeration>auto</spirit:enumeration>
+ <spirit:enumeration>distributed</spirit:enumeration>
+ <spirit:enumeration>block</spirit:enumeration>
+ <spirit:enumeration>ultra</spirit:enumeration>
+ </spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/axilite_if.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
<spirit:file>
<spirit:name>hdl/memstream.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/mux.v</spirit:name>
+ <spirit:name>hdl/memstream_multiblock.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/memstream_singleblock.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/memstream_multiblock.v</spirit:name>
+ <spirit:name>hdl/mux.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/ramb18_wf_dualport.v</spirit:name>
+ <spirit:name>hdl/ramb18_sdp.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_9425c051</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/ramb18_sdp.v</spirit:name>
+ <spirit:name>hdl/ramb18_wf_dualport.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_9f7c64bf</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ <spirit:userFileType>CHECKSUM_9425c051</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
- <spirit:file>
- <spirit:name>sim/tb_memstream.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
<spirit:file>
<spirit:name>hdl/memstream.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/mux.v</spirit:name>
+ <spirit:name>hdl/axilite_if.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/memstream_singleblock.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/memstream_multiblock.v</spirit:name>
+ <spirit:name>hdl/mux.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ramb18_wf_dualport.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/memstream_multiblock.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ramb18_sdp.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -966,22 +1508,29 @@
<spirit:file>
<spirit:name>xgui/memstream_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_d714c73b</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_f960907f</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>gui/memstream_v1_0.gtcl</spirit:name>
+ <spirit:userFileType>GTCL</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
</spirit:fileSets>
<spirit:description>memstream_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>CONFIG_EN</spirit:name>
<spirit:displayName>Config En</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONFIG_EN">1</spirit:value>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CONFIG_EN">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NSTREAMS</spirit:name>
<spirit:displayName>Nstreams</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NSTREAMS">6</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NSTREAMS" spirit:minimum="1" spirit:maximum="6" spirit:rangeType="long">6</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MEM_DEPTH</spirit:name>
@@ -998,6 +1547,11 @@
<spirit:displayName>Mem Init</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_INIT">./</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RAM_STYLE</spirit:name>
+ <spirit:displayName>Ram Style</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RAM_STYLE" spirit:choiceRef="choice_list_e2bd1cd0">auto</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>STRM0_WIDTH</spirit:name>
<spirit:displayName>Strm0 Width</spirit:displayName>
@@ -1089,39 +1643,46 @@
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_OFFSET">11520</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_v1_0</spirit:value>
+ <spirit:name>AXILITE_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>Axilite Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXILITE_ADDR_WIDTH">16</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.AXILITE_ADDR_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>RAM_STYLE</spirit:name>
- <spirit:displayName>Ram Style</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RAM_STYLE" spirit:choiceRef="choice_list_44c459b8">auto</spirit:value>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">virtexuplusHBM</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>memstream_v1_0</xilinx:displayName>
- <xilinx:autoFamilySupportLevel>level_0</xilinx:autoFamilySupportLevel>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
- <xilinx:coreRevision>10</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2020-09-17T18:04:10Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>5</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2020-10-09T15:31:57Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d8b2551"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="629ffc9d"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="cabd7433"/>
- <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="29c70cc4"/>
- <xilinx:checksum xilinx:scope="parameters" xilinx:value="858b58f8"/>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8f86a494"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5a080bee"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d633e93f"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="2e562330"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="134f154d"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="83e5a517"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/finn-rtllib/memstream/hdl/axilite_if.v b/finn-rtllib/memstream/hdl/axilite_if.v
new file mode 100644
index 000000000..b461bad5a
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/axilite_if.v
@@ -0,0 +1,201 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module axi4lite_if
+#(
+ parameter ADDR_WIDTH = 32,
+ parameter DATA_WIDTH = 32,//AXI4 spec requires this to be strictly 32 or 64
+ parameter IP_DATA_WIDTH = 64//can be any power-of-2 multiple of DATA_WIDTH
+)
+(
+//system signals
+input aclk,
+input aresetn,//active low, asynchronous assertion and synchronous deassertion
+
+//Write channels
+//write address
+output reg awready,
+input awvalid,
+input [ADDR_WIDTH-1:0] awaddr,
+input [2:0] awprot,
+//write data
+output reg wready,
+input wvalid,
+input [DATA_WIDTH-1:0] wdata,
+input [(DATA_WIDTH/8)-1:0] wstrb,
+//burst response
+input bready,
+output reg bvalid,
+output reg [1:0] bresp,//NOTE: 00 = OKAY, 10 = SLVERR (write error)
+
+//Read channels
+//read address
+output reg arready,
+input arvalid,
+input [ADDR_WIDTH-1:0] araddr,
+input [2:0] arprot,
+//read data
+input rready,
+output reg rvalid,
+output reg [1:0] rresp,//NOTE: 00 = OKAY, 10 = SLVERR (read error)
+output reg [DATA_WIDTH-1:0] rdata,
+
+//IP-side interface
+output reg ip_en,
+output reg ip_wen,
+output reg [ADDR_WIDTH-1:0] ip_addr,
+output [IP_DATA_WIDTH-1:0] ip_wdata,
+input ip_rack,
+input [IP_DATA_WIDTH-1:0] ip_rdata
+);
+
+localparam RESP_OKAY = 2'b00;
+localparam RESP_SLVERR = 2'b10;
+//get ceil(log2(ceil(IP_DATA_WIDTH/DATA_WIDTH)))
+localparam NFOLDS_LOG = $clog2((IP_DATA_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH);
+
+reg internal_ren;
+reg internal_wen;
+reg internal_wack;
+reg [ADDR_WIDTH-1:0] internal_raddr;
+reg [ADDR_WIDTH-1:0] internal_waddr;
+reg [DATA_WIDTH-1:0] internal_wdata;
+reg [IP_DATA_WIDTH-1:0] internal_rdata;
+reg internal_error = 0;
+reg [NFOLDS_LOG-1:0] internal_rfold;
+
+//check DATA_WIDTH
+initial begin
+ if(DATA_WIDTH != 32 & DATA_WIDTH != 64) begin
+ $display("AXI4Lite DATA_WIDTH must be 32 or 64");
+ $finish;
+ end
+end
+
+//transaction state machine
+localparam STATE_IDLE = 0,
+ STATE_READ = 1,
+ STATE_WRITE = 2;
+
+reg [1:0] state;
+
+always @(posedge aclk or negedge aresetn)
+ if(~aresetn)
+ state <= STATE_IDLE;
+ else case(state)
+ STATE_IDLE:
+ if(awvalid & wvalid)
+ state <= STATE_WRITE;
+ else if(arvalid)
+ state <= STATE_READ;
+ STATE_READ:
+ if(rvalid & rready)
+ state <= STATE_IDLE;
+ STATE_WRITE:
+ if(bvalid & bready)
+ state <= STATE_IDLE;
+ default: state <= STATE_IDLE;
+ endcase
+
+//write-related internal signals
+always @(*) begin
+ internal_waddr = awaddr >> $clog2(DATA_WIDTH/8);
+ internal_wdata = wdata;
+ internal_wen = (state == STATE_IDLE) & awvalid & wvalid;
+end
+
+always @(posedge aclk) begin
+ awready <= internal_wen;
+ wready <= internal_wen;
+end
+
+//read-related internal signals
+always @(*) begin
+ internal_raddr = araddr >> $clog2(DATA_WIDTH/8);
+ internal_ren = (state == STATE_IDLE) & ~internal_wen & arvalid;
+end
+
+always @(posedge aclk)
+ arready <= internal_ren;
+
+wire write_to_last_fold;
+assign write_to_last_fold = internal_wen & (internal_waddr[NFOLDS_LOG-1:0] == {(NFOLDS_LOG){1'b1}});
+
+always @(posedge aclk) begin
+ ip_wen <= write_to_last_fold;
+ ip_en <= internal_ren | write_to_last_fold;
+ if(internal_ren | write_to_last_fold)
+ ip_addr <= internal_ren ? (internal_raddr >> NFOLDS_LOG) : (internal_waddr >> NFOLDS_LOG);
+ if(internal_ren)
+ internal_rfold <= internal_raddr[NFOLDS_LOG-1:0];
+ internal_wack <= internal_wen;
+end
+
+genvar i;
+reg [(1<<NFOLDS_LOG)*DATA_WIDTH-1:0] ip_wdata_wide;
+generate for(i=0; i<(1<<NFOLDS_LOG); i = i+1) begin: gen_wdata
+ always @(posedge aclk)
+ if(internal_waddr[NFOLDS_LOG-1:0] == i)
+ ip_wdata_wide[(i+1)*DATA_WIDTH-1:i*DATA_WIDTH] <= internal_wdata;
+end
+endgenerate
+assign ip_wdata = ip_wdata_wide[IP_DATA_WIDTH-1:0];
+
+//write response on AXI4L bus
+always @(posedge aclk or negedge aresetn)
+ if(~aresetn) begin
+ bvalid <= 0;//AXI4 spec requires BVALID pulled LOW during reset
+ bresp <= RESP_OKAY;
+ end else if(internal_wack) begin
+ bvalid <= 1;
+ bresp <= internal_error ? RESP_SLVERR : RESP_OKAY;
+ end else if(bready) begin
+ bvalid <= 0;
+ bresp <= RESP_OKAY;
+ end
+
+//read response on AXI4L bus
+always @(posedge aclk or negedge aresetn)
+ if(~aresetn) begin
+ rvalid <= 0;//AXI4 spec requires RVALID pulled LOW during reset
+ rdata <= 0;
+ rresp <= RESP_OKAY;
+ end else if(ip_rack) begin
+ rvalid <= 1;
+ rdata <= ip_rdata >> (internal_rfold*DATA_WIDTH);
+ rresp <= internal_error ? RESP_SLVERR : RESP_OKAY;
+ end else if(rready) begin
+ rvalid <= 0;
+ rdata <= 0;
+ rresp <= RESP_OKAY;
+ end
+
+endmodule
+
diff --git a/finn-rtllib/memstream/hdl/memstream.v b/finn-rtllib/memstream/hdl/memstream.v
index 961103e4c..2cd955f8d 100644
--- a/finn-rtllib/memstream/hdl/memstream.v
+++ b/finn-rtllib/memstream/hdl/memstream.v
@@ -61,19 +61,40 @@ module memstream
parameter STRM2_OFFSET = 4608,
parameter STRM3_OFFSET = 6912,
parameter STRM4_OFFSET = 9216,
- parameter STRM5_OFFSET = 11520
+ parameter STRM5_OFFSET = 11520,
+
+ parameter AXILITE_ADDR_WIDTH = 2+$clog2(MEM_DEPTH*(1<<$clog2((MEM_WIDTH+31)/32)))
)
(
input aclk,
input aresetn,
- //optional configuration interface compatible with ap_memory
- input [31:0] config_address,
- input config_ce,
- input config_we,
- input [31:0] config_d0,
- output [31:0] config_q0,
+ output awready,
+ input awvalid,
+ input [AXILITE_ADDR_WIDTH-1:0] awaddr,
+ input [2:0] awprot,
+ //write data
+ output wready,
+ input wvalid,
+ input [31:0] wdata,
+ input [3:0] wstrb,
+ //burst response
+ input bready,
+ output bvalid,
+ output [1:0] bresp,
+
+ //Read channels
+ //read address
+ output arready,
+ input arvalid,
+ input [AXILITE_ADDR_WIDTH-1:0] araddr,
+ input [2:0] arprot,
+ //read data
+ input rready,
+ output rvalid,
+ output [1:0] rresp,
+ output [31:0] rdata,
//multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
input m_axis_0_afull,
@@ -109,6 +130,13 @@ module memstream
);
+wire [31:0] config_address;
+wire config_ce;
+wire config_we;
+wire config_rack;
+wire [MEM_WIDTH-1:0] config_d0;
+wire [MEM_WIDTH-1:0] config_q0;
+
generate
if(NSTREAMS <= 2) begin: singleblock
@@ -144,6 +172,7 @@ mem
.config_we(config_we),
.config_d0(config_d0),
.config_q0(config_q0),
+ .config_rack(config_rack),
.m_axis_0_tready(m_axis_0_tready),
.m_axis_0_tvalid(m_axis_0_tvalid),
@@ -246,4 +275,53 @@ mem
end
endgenerate
+axi4lite_if
+#(
+ .ADDR_WIDTH(AXILITE_ADDR_WIDTH),
+ .DATA_WIDTH(32),
+ .IP_DATA_WIDTH(MEM_WIDTH)
+)
+config_if
+(
+ //system signals
+ .aclk(aclk),
+ .aresetn(aresetn),
+
+ //Write channels
+ //write address
+ .awready(awready),
+ .awvalid(awvalid),
+ .awaddr(awaddr),
+ .awprot(awprot),
+ //write data
+ .wready(wready),
+ .wvalid(wvalid),
+ .wdata(wdata),
+ .wstrb(wstrb),
+ //burst response
+ .bready(bready),
+ .bvalid(bvalid),
+ .bresp(bresp),
+
+ //Read channels
+ //read address
+ .arready(arready),
+ .arvalid(arvalid),
+ .araddr(araddr),
+ .arprot(arprot),
+ //read data
+ .rready(rready),
+ .rvalid(rvalid),
+ .rresp(rresp),
+ .rdata(rdata),
+
+ //IP-side interface
+ .ip_en(config_ce),
+ .ip_wen(config_we),
+ .ip_addr(config_address),
+ .ip_wdata(config_d0),
+ .ip_rack(config_rack),
+ .ip_rdata(config_q0)
+);
+
endmodule
diff --git a/finn-rtllib/memstream/hdl/memstream_multiblock.v b/finn-rtllib/memstream/hdl/memstream_multiblock.v
index 017088b8c..4e6167132 100644
--- a/finn-rtllib/memstream/hdl/memstream_multiblock.v
+++ b/finn-rtllib/memstream/hdl/memstream_multiblock.v
@@ -74,6 +74,7 @@ module memstream_multiblock
input config_we,
input [31:0] config_d0,
output [31:0] config_q0,
+ output config_rack,
//multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
input m_axis_0_afull,
@@ -466,6 +467,8 @@ always @(posedge aclk) begin
end
end
+//dummy read, for now
assign config_q0 = 0;
+assign config_rack = config_ce & ~config_we;
endmodule
diff --git a/finn-rtllib/memstream/hdl/memstream_singleblock.v b/finn-rtllib/memstream/hdl/memstream_singleblock.v
index b96730104..54ee56764 100644
--- a/finn-rtllib/memstream/hdl/memstream_singleblock.v
+++ b/finn-rtllib/memstream/hdl/memstream_singleblock.v
@@ -65,6 +65,7 @@ module memstream_singleblock
input config_we,
input [MEM_WIDTH-1:0] config_d0,
output [MEM_WIDTH-1:0] config_q0,
+ output config_rack,
//multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
input m_axis_0_tready,
@@ -97,6 +98,8 @@ wire strm1_incr_en;
assign strm0_incr_en = m_axis_0_tready | ~m_axis_0_tvalid;
assign strm1_incr_en = m_axis_1_tready | ~m_axis_1_tvalid;
+reg rack_shift[1:0];
+
generate
if(MEM_DEPTH > 1) begin: use_ram
@@ -135,9 +138,9 @@ ram
.addra(config_address[BLOCKADRWIDTH-1:0]),
.wdataa(config_d0),
- .enb(strm0_incr_en),
- .enqb(strm0_incr_en),
- .addrb(strm0_addr),
+ .enb(strm0_incr_en | config_ce),
+ .enqb(strm0_incr_en | rack_shift[0]),
+ .addrb(config_ce ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
.rdqb(m_axis_0_tdata)
);
@@ -170,7 +173,7 @@ ram
.wea(config_we),
.ena(strm0_incr_en | config_ce),
- .enqa(strm0_incr_en | config_ce),
+ .enqa(strm0_incr_en | config_ce_r),
.addra(config_we ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
.wdataa(config_d0),
.rdqa(m_axis_0_tdata),
@@ -228,6 +231,12 @@ always @(posedge aclk) begin
end
end
+always @(posedge aclk) begin
+ rack_shift[0] <= config_ce & ~config_we;
+ rack_shift[1] <= rack_shift[0];
+end
+
+assign config_rack = rack_shift[1];
assign config_q0 = m_axis_0_tdata;
endmodule
diff --git a/finn-rtllib/memstream/sim/tb_memstream_writes.v b/finn-rtllib/memstream/sim/tb_memstream_writes.v
new file mode 100644
index 000000000..867acfe81
--- /dev/null
+++ b/finn-rtllib/memstream/sim/tb_memstream_writes.v
@@ -0,0 +1,497 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+`timescale 1ns/10ps
+
+module tb_memstream_writes;
+
+//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
+parameter CONFIG_EN = 1;
+parameter NSTREAMS = 2;//1 up to 6
+
+parameter MEM_DEPTH = 40;
+parameter MEM_WIDTH = 70;
+
+//widths per stream
+parameter STRM0_WIDTH = 70;
+parameter STRM1_WIDTH = 32;
+parameter STRM2_WIDTH = 32;
+parameter STRM3_WIDTH = 32;
+parameter STRM4_WIDTH = 1;
+parameter STRM5_WIDTH = 1;
+
+//depths per stream
+parameter STRM0_DEPTH = 20;
+parameter STRM1_DEPTH = 20;
+parameter STRM2_DEPTH = 2304;
+parameter STRM3_DEPTH = 2304;
+parameter STRM4_DEPTH = 1;
+parameter STRM5_DEPTH = 1;
+
+//offsets for each stream
+parameter STRM0_OFFSET = 0;
+parameter STRM1_OFFSET = 20;
+parameter STRM2_OFFSET = 4608;
+parameter STRM3_OFFSET = 6912;
+parameter STRM4_OFFSET = 0;
+parameter STRM5_OFFSET = 0;
+
+
+reg clk;
+reg rst;
+
+wire awready;
+reg awvalid;
+reg [31:0] awaddr;
+reg [2:0] awprot;
+//write data
+wire wready;
+reg wvalid;
+reg [31:0] wdata;
+reg [3:0] wstrb;
+//burst response
+reg bready;
+wire bvalid;
+wire [1:0] bresp;
+
+//Read channels
+//read address
+wire arready;
+reg arvalid;
+reg [31:0] araddr;
+reg [2:0] arprot;
+//read data
+reg rready;
+wire rvalid;
+wire [1:0] rresp;
+wire [31:0] rdata;
+
+//multiple wire AXI Streams
+reg m_axis_0_afull;
+reg m_axis_0_tready;
+wire m_axis_0_tvalid;
+wire [STRM0_WIDTH-1:0] m_axis_0_tdata;
+
+reg m_axis_1_afull;
+reg m_axis_1_tready;
+wire m_axis_1_tvalid;
+wire [STRM1_WIDTH-1:0] m_axis_1_tdata;
+
+reg m_axis_2_afull;
+reg m_axis_2_tready;
+wire m_axis_2_tvalid;
+wire [STRM2_WIDTH-1:0] m_axis_2_tdata;
+
+reg m_axis_3_afull;
+reg m_axis_3_tready;
+wire m_axis_3_tvalid;
+wire [STRM3_WIDTH-1:0] m_axis_3_tdata;
+
+reg m_axis_4_afull;
+reg m_axis_4_tready;
+wire m_axis_4_tvalid;
+wire [STRM4_WIDTH-1:0] m_axis_4_tdata;
+
+reg m_axis_5_afull;
+reg m_axis_5_tready;
+wire m_axis_5_tvalid;
+wire [STRM5_WIDTH-1:0] m_axis_5_tdata;
+
+reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0];
+reg [MEM_WIDTH-1:0] gword;
+integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5;
+integer done = 0;
+integer i, j;
+reg [5:0] rng;
+
+parameter NFOLDS_PER_WORD = (MEM_WIDTH+31)/32;
+
+task axi_write;
+ input [MEM_WIDTH-1:0] data;
+ input [31:0] adr;
+ begin
+ for(j=0; j<(1<<$clog2(NFOLDS_PER_WORD)); j=j+1) begin
+ @(negedge clk);
+ awvalid = 1;
+ wvalid = 1;
+ wdata = data>>(j*32);
+ awaddr = (adr*(1<<$clog2(NFOLDS_PER_WORD))+j)*4;
+ fork
+ begin
+ @(posedge awready);
+ @(posedge clk) awvalid = 0;
+ end
+ begin
+ @(posedge wready);
+ @(posedge clk) wvalid = 0;
+ end
+ join
+ @(posedge clk);
+ end
+ end
+endtask
+
+task axi_read;
+ input [31:0] adr;
+ output [MEM_WIDTH-1:0] data;
+ begin
+ data = 0;
+ for(j=0; j<NFOLDS_PER_WORD; j=j+1) begin
+ @(negedge clk);
+ arvalid = 1;
+ araddr = (adr*(1<<$clog2(NFOLDS_PER_WORD))+j)*4;
+ rready = 1;
+ fork
+ begin
+ @(posedge arready);
+ @(posedge clk) arvalid = 0;
+ end
+ begin
+ @(posedge rvalid);
+ @(posedge clk) rready = 0;
+ data = data | (rdata<<(32*j));
+ end
+ join
+
+ @(posedge clk);
+ end
+ end
+endtask
+
+//clock
+initial begin
+ clk = 0;
+ forever #5 clk = ~clk;
+end
+
+initial begin
+ rst = 1;
+ awvalid = 0;
+ arvalid = 0;
+ wvalid = 0;
+ rready = 1;
+ bready = 1;
+ m_axis_0_afull = 1;
+ m_axis_1_afull = 1;
+ m_axis_2_afull = 1;
+ m_axis_3_afull = 1;
+ m_axis_4_afull = 1;
+ m_axis_5_afull = 1;
+ m_axis_0_tready = 0;
+ m_axis_1_tready = 0;
+ m_axis_2_tready = 0;
+ m_axis_3_tready = 0;
+ m_axis_4_tready = 0;
+ m_axis_5_tready = 0;
+ repeat(100) @(negedge clk);
+ rst = 0;
+ #100
+ //random initialization of golden data
+ for(i=0; i<MEM_DEPTH; i=i+1) begin
+ gword = 0;
+ repeat(NFOLDS_PER_WORD)
+ gword = (gword << 32) | $random;
+ golden[i] = gword;
+ axi_write(golden[i],i);
+ axi_read(i,gword);
+ end
+ //re-reset
+ repeat(100) @(negedge clk);
+ rst = 1;
+ #100
+ repeat(100) @(negedge clk);
+ rst = 0;
+ #100
+ @(negedge clk);
+ //start reads
+ m_axis_0_afull = 0;
+ m_axis_1_afull = 0;
+ m_axis_2_afull = 0;
+ m_axis_3_afull = 0;
+ m_axis_4_afull = 0;
+ m_axis_5_afull = 0;
+ m_axis_0_tready = 1;
+ m_axis_1_tready = 1;
+ m_axis_2_tready = 1;
+ m_axis_3_tready = 1;
+ m_axis_4_tready = 1;
+ m_axis_5_tready = 1;
+ fork
+ begin
+ $display("Starting to generate random AFULL");
+ while(~done) begin
+ rng = $random;
+ m_axis_0_afull = rng[0];
+ m_axis_1_afull = rng[1];
+ m_axis_2_afull = rng[2];
+ m_axis_3_afull = rng[3];
+ m_axis_4_afull = rng[4];
+ m_axis_5_afull = rng[5];
+ @(negedge clk);
+ end
+ end
+ join
+end
+
+
+//DUT
+memstream
+#(
+ CONFIG_EN,
+ NSTREAMS,
+ MEM_DEPTH,
+ MEM_WIDTH,
+ ".",
+ "auto",
+
+ //widths per stream
+ STRM0_WIDTH,
+ STRM1_WIDTH,
+ STRM2_WIDTH,
+ STRM3_WIDTH,
+ STRM4_WIDTH,
+ STRM5_WIDTH,
+
+ //depths per stream
+ STRM0_DEPTH,
+ STRM1_DEPTH,
+ STRM2_DEPTH,
+ STRM3_DEPTH,
+ STRM4_DEPTH,
+ STRM5_DEPTH,
+
+ //offsets for each stream
+ STRM0_OFFSET,
+ STRM1_OFFSET,
+ STRM2_OFFSET,
+ STRM3_OFFSET,
+ STRM4_OFFSET,
+ STRM5_OFFSET
+)
+dut
+(
+ clk,
+ ~rst,
+
+ //optional AXI-Lite interface
+ awready,
+ awvalid,
+ awaddr,
+ awprot,
+ //write data
+ wready,
+ wvalid,
+ wdata,
+ wstrb,
+ //burst response
+ bready,
+ bvalid,
+ bresp,
+
+ //Read channels
+ //read address
+ arready,
+ arvalid,
+ araddr,
+ arprot,
+ //read data
+ rready,
+ rvalid,
+ rresp,
+ rdata,
+
+ //multiple output AXI Streams
+ m_axis_0_afull,
+ m_axis_0_tready,
+ m_axis_0_tvalid,
+ m_axis_0_tdata,
+
+ m_axis_1_afull,
+ m_axis_1_tready,
+ m_axis_1_tvalid,
+ m_axis_1_tdata,
+
+ m_axis_2_afull,
+ m_axis_2_tready,
+ m_axis_2_tvalid,
+ m_axis_2_tdata,
+
+ m_axis_3_afull,
+ m_axis_3_tready,
+ m_axis_3_tvalid,
+ m_axis_3_tdata,
+
+ m_axis_4_afull,
+ m_axis_4_tready,
+ m_axis_4_tvalid,
+ m_axis_4_tdata,
+
+ m_axis_5_afull,
+ m_axis_5_tready,
+ m_axis_5_tvalid,
+ m_axis_5_tdata
+
+
+);
+
+//stream checkers
+initial begin
+ ptr0 = STRM0_OFFSET;
+ ptr1 = STRM1_OFFSET;
+ ptr2 = STRM2_OFFSET;
+ ptr3 = STRM3_OFFSET;
+ ptr4 = STRM4_OFFSET;
+ ptr5 = STRM5_OFFSET;
+ fork
+ //check stream 0
+ begin
+ $display("Starting stream 0 checker");
+ while(~done & (NSTREAMS > 0)) begin
+ @(negedge clk);
+ if(m_axis_0_tvalid & m_axis_0_tready) begin
+ if(m_axis_0_tdata != golden[ptr0]) begin
+ $display("Mismatch on stream 0");
+ $stop();
+ end
+ //increment pointer
+ ptr0 = ptr0 + 1;
+ //rewind pointer if it's reached end
+ if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH))
+ ptr0 = STRM0_OFFSET;
+ end
+ end
+ end
+ //check stream 1
+ begin
+ $display("Starting stream 1 checker");
+ while(~done & (NSTREAMS > 1)) begin
+ @(negedge clk);
+ if(m_axis_1_tvalid & m_axis_1_tready) begin
+ if(m_axis_1_tdata != golden[ptr1]) begin
+ $display("Mismatch on stream 1");
+ $stop();
+ end
+ //increment pointer
+ ptr1 = ptr1 + 1;
+ //rewind pointer if it's reached end
+ if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH))
+ ptr1 = STRM1_OFFSET;
+ end
+ end
+ end
+
+ //check stream 2
+ begin
+ $display("Starting stream 2 checker");
+ while(~done & (NSTREAMS > 2)) begin
+ @(negedge clk);
+ if(m_axis_2_tvalid & m_axis_2_tready) begin
+ if(m_axis_2_tdata != golden[ptr2]) begin
+ $display("Mismatch on stream 2");
+ $stop();
+ end
+ //increment pointer
+ ptr2 = ptr2 + 1;
+ //rewind pointer if it's reached end
+ if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH))
+ ptr2 = STRM2_OFFSET;
+ end
+ end
+ end
+ //check stream 3
+ begin
+ $display("Starting stream 3 checker");
+ while(~done & (NSTREAMS > 3)) begin
+ @(negedge clk);
+ if(m_axis_3_tvalid & m_axis_3_tready) begin
+ if(m_axis_3_tdata != golden[ptr3]) begin
+ $display("Mismatch on stream 3");
+ $stop();
+ end
+ //increment pointer
+ ptr3 = ptr3 + 1;
+ //rewind pointer if it's reached end
+ if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH))
+ ptr3 = STRM3_OFFSET;
+ end
+ end
+ end
+ //check stream 4
+ begin
+ $display("Starting stream 4 checker");
+ while(~done & (NSTREAMS > 4)) begin
+ @(negedge clk);
+ if(m_axis_4_tvalid & m_axis_4_tready) begin
+ if(m_axis_4_tdata != golden[ptr4]) begin
+ $display("Mismatch on stream 4");
+ $stop();
+ end
+ //increment pointer
+ ptr4 = ptr4 + 1;
+ //rewind pointer if it's reached end
+ if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH))
+ ptr4 = STRM4_OFFSET;
+ end
+ end
+ end
+ //check stream 5
+ begin
+ $display("Starting stream 5 checker");
+ while(~done & (NSTREAMS > 5)) begin
+ @(negedge clk);
+ if(m_axis_5_tvalid & m_axis_5_tready) begin
+ if(m_axis_5_tdata != golden[ptr5]) begin
+ $display("Mismatch on stream 5");
+ $stop();
+ end
+ //increment pointer
+ ptr5 = ptr5 + 1;
+ //rewind pointer if it's reached end
+ if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH))
+ ptr5 = STRM5_OFFSET;
+ end
+ end
+ end
+ join
+end
+
+initial begin
+ done = 0;
+ @(negedge rst);
+ $dumpfile("wave.vcd");
+ $dumpvars(0,tb_memstream_writes);
+ #50000
+ $display("Test done!");
+ done = 1;
+ #1000
+ $finish();
+end
+
+endmodule
diff --git a/finn-rtllib/memstream/sim/test.sh b/finn-rtllib/memstream/sim/test.sh
old mode 100644
new mode 100755
index 24767edf4..3348e64b7
--- a/finn-rtllib/memstream/sim/test.sh
+++ b/finn-rtllib/memstream/sim/test.sh
@@ -28,7 +28,6 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-./gen_memblocks.sh golden.dat
-iverilog ../hdl/*.v *v -o sim
+iverilog ../hdl/*.v tb_memstream_writes.v -o sim
./sim
diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
index 7ce84b44a..b8be5e0a2 100644
--- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
+++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
@@ -1,14 +1,19 @@
+
+# Loading additional proc with user specified bodies to compute parameter values.
+source [file join [file dirname [file dirname [info script]]] gui/memstream_v1_0.gtcl]
+
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "AXILITE_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "CONFIG_EN" -parent ${Page_0}
ipgui::add_param $IPINST -name "MEM_DEPTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "MEM_INIT" -parent ${Page_0}
ipgui::add_param $IPINST -name "MEM_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "NSTREAMS" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "STRM0_DEPTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "STRM0_OFFSET" -parent ${Page_0}
ipgui::add_param $IPINST -name "STRM0_WIDTH" -parent ${Page_0}
@@ -31,6 +36,22 @@ proc init_gui { IPINST } {
}
+proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_WIDTH } {
+ # Procedure called to update AXILITE_ADDR_WIDTH when any of the dependent parameters in the arguments change
+
+ set AXILITE_ADDR_WIDTH ${PARAM_VALUE.AXILITE_ADDR_WIDTH}
+ set MEM_DEPTH ${PARAM_VALUE.MEM_DEPTH}
+ set MEM_WIDTH ${PARAM_VALUE.MEM_WIDTH}
+ set values(MEM_DEPTH) [get_property value $MEM_DEPTH]
+ set values(MEM_WIDTH) [get_property value $MEM_WIDTH]
+ set_property value [gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE $values(MEM_DEPTH) $values(MEM_WIDTH)] $AXILITE_ADDR_WIDTH
+}
+
+proc validate_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH } {
+ # Procedure called to validate AXILITE_ADDR_WIDTH
+ return true
+}
+
proc update_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
# Procedure called to update CONFIG_EN when any of the dependent parameters in the arguments change
}
@@ -368,3 +389,8 @@ proc update_MODELPARAM_VALUE.STRM5_OFFSET { MODELPARAM_VALUE.STRM5_OFFSET PARAM_
set_property value [get_property value ${PARAM_VALUE.STRM5_OFFSET}] ${MODELPARAM_VALUE.STRM5_OFFSET}
}
+proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.AXILITE_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.AXILITE_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH}
+}
+
--
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