From e839d3acbd854280a34909aac9634dd127ccb3e5 Mon Sep 17 00:00:00 2001
From: mmrahorovic <mmrahorovic@hotmail.com>
Date: Mon, 13 Jun 2022 16:48:15 +0100
Subject: [PATCH] [notebooks]: Cleared output cells
---
.../advanced/0_custom_analysis_pass.ipynb | 66 +-
.../1_custom_transformation_pass.ipynb | 240 +-
notebooks/advanced/2_custom_op.ipynb | 344 +-
.../basics/0_how_to_work_with_onnx.ipynb | 213 +-
.../bnn-pynq/cnv_end2end_example.ipynb | 432 +-
.../bnn-pynq/tfc_end2end_example.ipynb | 885 +--
.../bnn-pynq/tfc_end2end_verification.ipynb | 5043 +----------------
.../1-train-mlp-with-brevitas.ipynb | 242 +-
.../2-import-into-finn-and-verify.ipynb | 196 +-
.../3-build-accelerator-with-finn.ipynb | 493 +-
10 files changed, 428 insertions(+), 7726 deletions(-)
diff --git a/notebooks/advanced/0_custom_analysis_pass.ipynb b/notebooks/advanced/0_custom_analysis_pass.ipynb
index 617bfa089..684b3fea7 100644
--- a/notebooks/advanced/0_custom_analysis_pass.ipynb
+++ b/notebooks/advanced/0_custom_analysis_pass.ipynb
@@ -13,7 +13,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -48,38 +48,9 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving '../LFCW1A1.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f14142de3c8>"
- ]
- },
- "execution_count": 2,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"showInNetron(\"../LFCW1A1.onnx\")"
]
@@ -93,7 +64,7 @@
},
{
"cell_type": "code",
- "execution_count": 3,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -110,7 +81,7 @@
},
{
"cell_type": "code",
- "execution_count": 4,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -140,20 +111,9 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- " def analysis(self, analysis_fxn):\n",
- " \"\"\"Runs given anaylsis_fxn on this model and return resulting dict.\"\"\"\n",
- " return analysis_fxn(self)\n",
- "\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"showSrc(ModelWrapper.analysis)"
]
@@ -167,17 +127,9 @@
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "{'Shape': 1, 'Gather': 1, 'Unsqueeze': 5, 'Concat': 1, 'Reshape': 1, 'Mul': 5, 'Sub': 1, 'Sign': 4, 'MatMul': 4, 'BatchNormalization': 3, 'Squeeze': 3}\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"print(model.analysis(count_equal_nodes))"
]
diff --git a/notebooks/advanced/1_custom_transformation_pass.ipynb b/notebooks/advanced/1_custom_transformation_pass.ipynb
index 9d9bc7463..f0c5f80d8 100644
--- a/notebooks/advanced/1_custom_transformation_pass.ipynb
+++ b/notebooks/advanced/1_custom_transformation_pass.ipynb
@@ -13,7 +13,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -42,32 +42,9 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- " def transform(self, transformation, make_deepcopy=True):\n",
- " \"\"\"Applies given Transformation repeatedly until no more changes can be made\n",
- " and returns a transformed ModelWrapper instance.\n",
- "\n",
- " If make_deepcopy is specified, operates on a new (deep)copy of model.\n",
- " \"\"\"\n",
- " transformed_model = self\n",
- " if make_deepcopy:\n",
- " transformed_model = copy.deepcopy(self)\n",
- " model_was_changed = True\n",
- " while model_was_changed:\n",
- " (transformed_model, model_was_changed) = transformation.apply(\n",
- " transformed_model\n",
- " )\n",
- " return transformed_model\n",
- "\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.core.modelwrapper import ModelWrapper\n",
"showSrc(ModelWrapper.transform)"
@@ -98,27 +75,9 @@
},
{
"cell_type": "code",
- "execution_count": 3,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "class Transformation(ABC):\n",
- " \"\"\"Transformation class all transformations are based on. Contains only\n",
- " abstract method apply() every transformation has to fill.\"\"\"\n",
- "\n",
- " def __init__(self):\n",
- " super().__init__()\n",
- "\n",
- " @abstractmethod\n",
- " def apply(self, model):\n",
- " pass\n",
- "\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.transformation.base import Transformation\n",
"\n",
@@ -145,7 +104,7 @@
},
{
"cell_type": "code",
- "execution_count": 4,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -157,45 +116,16 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving '../LFCW1A1.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fc625ac0a20>"
- ]
- },
- "execution_count": 5,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"showInNetron('../LFCW1A1.onnx')"
]
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -232,7 +162,7 @@
},
{
"cell_type": "code",
- "execution_count": 7,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -242,40 +172,9 @@
},
{
"cell_type": "code",
- "execution_count": 8,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "\n",
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/tmp/LFCW1A1_changed.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fc625ac09b0>"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"showInNetron('/tmp/LFCW1A1_changed.onnx')"
]
@@ -291,66 +190,9 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "class NodeLocalTransformation(Transformation):\n",
- " \"\"\"\n",
- " Parent class for transformations, which can be executed locally to one node\n",
- " by accessing and modifying the attributes of only that node.\n",
- " This class can then automatically parallelize the transformation.\n",
- " Transformations sublcassing NodeLocalTransformation must implement the\n",
- " abstract method applyNodeLocal().\n",
- "\n",
- " To control the degree of parallelization, specify the num_workers argument\n",
- " in the constructor, using one of the following values:\n",
- " * None: use NUM_DEFAULT_WORKERS environment variable\n",
- " * 0: use all available CPU cores\n",
- " * (any other int>0): set number of parallel workers\n",
- " \"\"\"\n",
- "\n",
- " def __init__(self, num_workers=None):\n",
- " super().__init__()\n",
- " if num_workers is None:\n",
- " self._num_workers = get_num_default_workers()\n",
- " else:\n",
- " self._num_workers = num_workers\n",
- " assert self._num_workers >= 0, \"Number of workers must be nonnegative.\"\n",
- " if self._num_workers == 0:\n",
- " self._num_workers = mp.cpu_count()\n",
- "\n",
- " @abstractmethod\n",
- " def applyNodeLocal(self, node):\n",
- " pass\n",
- "\n",
- " def apply(self, model):\n",
- " # Remove old nodes from the current model\n",
- " old_nodes = []\n",
- " for i in range(len(model.graph.node)):\n",
- " old_nodes.append(model.graph.node.pop())\n",
- "\n",
- " # Execute transformation in parallel\n",
- " with mp.Pool(self._num_workers) as p:\n",
- " new_nodes_and_bool = p.map(self.applyNodeLocal, old_nodes, chunksize=1)\n",
- "\n",
- " # extract nodes and check if the transformation needs to run again\n",
- " # Note: .pop() had initially reversed the node order\n",
- " run_again = False\n",
- " for node, run in reversed(new_nodes_and_bool):\n",
- " # Reattach new nodes to old model\n",
- " model.graph.node.append(node)\n",
- " if run is True:\n",
- " run_again = True\n",
- "\n",
- " return (model, run_again)\n",
- "\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.transformation.base import NodeLocalTransformation\n",
"\n",
@@ -370,59 +212,9 @@
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "class CompileCppSim(NodeLocalTransformation):\n",
- " \"\"\"For every node: compile C++ code in node attribute \"code_gen_dir_cppsim\"\n",
- " and save path to executables in node attribute \"executable_path\".\n",
- " All nodes in the graph must have the fpgadataflow backend attribute.\n",
- "\n",
- " To use these executables, exec_mode must be set to \"cppsim\" (using transformation\n",
- " SetExecMode) and the model has to be executed using execute_onnx() from\n",
- " finn.core.onnx_exec\n",
- "\n",
- " * num_workers (int or None) number of parallel workers, see documentation in\n",
- " NodeLocalTransformation for more details.\n",
- " \"\"\"\n",
- "\n",
- " def __init__(self, num_workers=None):\n",
- " super().__init__(num_workers=num_workers)\n",
- "\n",
- " def applyNodeLocal(self, node):\n",
- " op_type = node.op_type\n",
- " if is_fpgadataflow_node(node) is True:\n",
- " try:\n",
- " # lookup op_type in registry of CustomOps\n",
- " inst = registry.getCustomOp(node)\n",
- " # ensure that code is generated\n",
- " assert (\n",
- " inst.get_nodeattr(\"code_gen_dir_cppsim\") != \"\"\n",
- " ), \"\"\"Node\n",
- " attribute \"code_gen_dir_cppsim\" is not set. Please run\n",
- " Transformation PrepareCppSim first.\"\"\"\n",
- " # call the compilation function for this node\n",
- " inst.compile_singlenode_code()\n",
- " # ensure that executable path is now set\n",
- " assert (\n",
- " inst.get_nodeattr(\"executable_path\") != \"\"\n",
- " ), \"\"\"Transformation\n",
- " compile was not successful, there is no path to executables set\n",
- " in node attribute \"executable_path\".\"\"\"\n",
- " except KeyError:\n",
- " # exception if op_type is not supported\n",
- " raise Exception(\n",
- " \"Custom op_type %s is currently not supported.\" % op_type\n",
- " )\n",
- " return (node, False)\n",
- "\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim\n",
"\n",
diff --git a/notebooks/advanced/2_custom_op.ipynb b/notebooks/advanced/2_custom_op.ipynb
index 57f2601c7..5f2bdc4bf 100644
--- a/notebooks/advanced/2_custom_op.ipynb
+++ b/notebooks/advanced/2_custom_op.ipynb
@@ -28,57 +28,9 @@
},
{
"cell_type": "code",
- "execution_count": 1,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "['__abstractmethods__',\n",
- " '__class__',\n",
- " '__delattr__',\n",
- " '__dict__',\n",
- " '__dir__',\n",
- " '__doc__',\n",
- " '__eq__',\n",
- " '__format__',\n",
- " '__ge__',\n",
- " '__getattribute__',\n",
- " '__gt__',\n",
- " '__hash__',\n",
- " '__init__',\n",
- " '__init_subclass__',\n",
- " '__le__',\n",
- " '__lt__',\n",
- " '__module__',\n",
- " '__ne__',\n",
- " '__new__',\n",
- " '__reduce__',\n",
- " '__reduce_ex__',\n",
- " '__repr__',\n",
- " '__setattr__',\n",
- " '__sizeof__',\n",
- " '__slots__',\n",
- " '__str__',\n",
- " '__subclasshook__',\n",
- " '__weakref__',\n",
- " '_abc_impl',\n",
- " 'execute_node',\n",
- " 'get_nodeattr',\n",
- " 'get_nodeattr_allowed_values',\n",
- " 'get_nodeattr_def',\n",
- " 'get_nodeattr_types',\n",
- " 'infer_node_datatype',\n",
- " 'make_shape_compatible_op',\n",
- " 'set_nodeattr',\n",
- " 'verify_node']"
- ]
- },
- "execution_count": 1,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.custom_op.base import CustomOp\n",
"dir(CustomOp)"
@@ -95,7 +47,7 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -183,7 +135,7 @@
},
{
"cell_type": "code",
- "execution_count": 3,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -200,27 +152,9 @@
},
{
"cell_type": "code",
- "execution_count": 4,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "{'DebugMarker': finn.custom_op.general.debugmarker.DebugMarker,\n",
- " 'QuantAvgPool2d': finn.custom_op.general.quantavgpool2d.QuantAvgPool2d,\n",
- " 'MaxPoolNHWC': finn.custom_op.general.maxpoolnhwc.MaxPoolNHWC,\n",
- " 'GenericPartition': finn.custom_op.general.genericpartition.GenericPartition,\n",
- " 'MultiThreshold': finn.custom_op.general.multithreshold.MultiThreshold,\n",
- " 'XnorPopcountMatMul': finn.custom_op.general.xnorpopcount.XnorPopcountMatMul,\n",
- " 'Im2Col': finn.custom_op.general.im2col.Im2Col,\n",
- " 'MyPythonPowerOp': __main__.MyPythonPowerOp}"
- ]
- },
- "execution_count": 4,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"general.custom_op"
]
@@ -238,7 +172,7 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -283,34 +217,9 @@
},
{
"cell_type": "code",
- "execution_count": 6,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "[input: \"inp\"\n",
- "output: \"outp\"\n",
- "op_type: \"MyPythonPowerOp\"\n",
- "attribute {\n",
- " name: \"exec_mode\"\n",
- " s: \"python\"\n",
- " type: STRING\n",
- "}\n",
- "attribute {\n",
- " name: \"exponent\"\n",
- " i: 2\n",
- " type: INT\n",
- "}\n",
- "domain: \"finn.custom_op.general\"\n",
- "]"
- ]
- },
- "execution_count": 6,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"# generate a small graph with our custom op\n",
"input_shape = (1, 2, 4)\n",
@@ -327,21 +236,9 @@
},
{
"cell_type": "code",
- "execution_count": 7,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "array([[[ 0., -3., 1., -8.],\n",
- " [ 2., -2., -4., -8.]]], dtype=float32)"
- ]
- },
- "execution_count": 7,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.core.datatype import DataType\n",
"from finn.util.basic import gen_finn_dt_tensor\n",
@@ -360,21 +257,9 @@
},
{
"cell_type": "code",
- "execution_count": 8,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "{'outp': array([[[ 0., 9., 1., 64.],\n",
- " [ 4., 4., 16., 64.]]], dtype=float32)}"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.core.onnx_exec import execute_onnx\n",
"\n",
@@ -406,7 +291,7 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -521,34 +406,9 @@
},
{
"cell_type": "code",
- "execution_count": 10,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "[input: \"inp\"\n",
- "output: \"outp\"\n",
- "op_type: \"MyMixedPowerOp\"\n",
- "attribute {\n",
- " name: \"exec_mode\"\n",
- " s: \"python\"\n",
- " type: STRING\n",
- "}\n",
- "attribute {\n",
- " name: \"exponent\"\n",
- " i: 2\n",
- " type: INT\n",
- "}\n",
- "domain: \"finn.custom_op.general\"\n",
- "]"
- ]
- },
- "execution_count": 10,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"# register our new op\n",
"general.custom_op[\"MyMixedPowerOp\"] = MyMixedPowerOp\n",
@@ -567,19 +427,9 @@
},
{
"cell_type": "code",
- "execution_count": 11,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Available functions: ['__abstractmethods__', '__class__', '__delattr__', '__dict__', '__dir__', '__doc__', '__eq__', '__format__', '__ge__', '__getattribute__', '__gt__', '__hash__', '__init__', '__init_subclass__', '__le__', '__lt__', '__module__', '__ne__', '__new__', '__reduce__', '__reduce_ex__', '__repr__', '__setattr__', '__sizeof__', '__slots__', '__str__', '__subclasshook__', '__weakref__', '_abc_impl', 'execute_node', 'get_nodeattr', 'get_nodeattr_allowed_values', 'get_nodeattr_def', 'get_nodeattr_types', 'infer_node_datatype', 'make_shape_compatible_op', 'my_custom_cpp_gen', 'onnx_node', 'set_nodeattr', 'verify_node']\n",
- "codegen_dir: \n",
- "exec_mode: python\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.custom_op.registry import getCustomOp\n",
"\n",
@@ -602,7 +452,7 @@
},
{
"cell_type": "code",
- "execution_count": 12,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -641,7 +491,7 @@
},
{
"cell_type": "code",
- "execution_count": 13,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -657,17 +507,9 @@
},
{
"cell_type": "code",
- "execution_count": 14,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "/tmp/finn_dev_maltanar/my_custom_oppswiou3i\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"new_op_inst = getCustomOp(mixedop_graph_new.graph.node[0])\n",
"codegen_dir = new_op_inst.get_nodeattr(\"codegen_dir\")\n",
@@ -683,17 +525,9 @@
},
{
"cell_type": "code",
- "execution_count": 15,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "compile.sh node_model\ttop.cpp\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ls {codegen_dir}"
]
@@ -707,39 +541,9 @@
},
{
"cell_type": "code",
- "execution_count": 16,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "\r\n",
- "#include <iostream>\r\n",
- "#include <fstream>\r\n",
- "using namespace std;\r\n",
- "#define EXPONENT 2\r\n",
- "\r\n",
- "int main(int argc, char **argv) {\r\n",
- " ifstream infile(\"input.txt\");\r\n",
- " ofstream outfile(\"output.txt\");\r\n",
- " \r\n",
- " float elem;\r\n",
- " while (infile >> elem)\r\n",
- " {\r\n",
- " float res = 1.0;\r\n",
- " for(int i=0; i < EXPONENT; i++) {\r\n",
- " res *= elem;\r\n",
- " }\r\n",
- " outfile << res << \"\\n\";\r\n",
- " }\r\n",
- "\r\n",
- " return 0;\r\n",
- "}\r\n",
- " "
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! cat {codegen_dir}/top.cpp"
]
@@ -757,7 +561,7 @@
},
{
"cell_type": "code",
- "execution_count": 17,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -766,7 +570,7 @@
},
{
"cell_type": "code",
- "execution_count": 18,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -775,26 +579,16 @@
},
{
"cell_type": "code",
- "execution_count": 19,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "49\r\n",
- "64\r\n",
- "81\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! cat {codegen_dir}/output.txt"
]
},
{
"cell_type": "code",
- "execution_count": 20,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -812,21 +606,9 @@
},
{
"cell_type": "code",
- "execution_count": 21,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "array([[[-6., 3., 2., -5.],\n",
- " [ 5., 2., 0., -2.]]], dtype=float32)"
- ]
- },
- "execution_count": 21,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"# generate a random input of e.g signed 4-bit values\n",
"random_input = gen_finn_dt_tensor(DataType[\"INT4\"], input_shape)\n",
@@ -842,21 +624,9 @@
},
{
"cell_type": "code",
- "execution_count": 22,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "{'outp': array([[[36., 9., 4., 25.],\n",
- " [25., 4., 0., 4.]]], dtype=float32)}"
- ]
- },
- "execution_count": 22,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"# run with FINN's execute_onnx, custom node will use Python execution\n",
"new_op_inst.set_nodeattr(\"exec_mode\", \"python\")\n",
@@ -874,21 +644,9 @@
},
{
"cell_type": "code",
- "execution_count": 23,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "{'outp': array([[[36., 9., 4., 25.],\n",
- " [25., 4., 0., 4.]]])}"
- ]
- },
- "execution_count": 23,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"# run with FINN's execute_onnx, custom node will use c++ execution\n",
"new_op_inst.set_nodeattr(\"exec_mode\", \"c++\")\n",
diff --git a/notebooks/basics/0_how_to_work_with_onnx.ipynb b/notebooks/basics/0_how_to_work_with_onnx.ipynb
index 58f53c329..aae98ec77 100644
--- a/notebooks/basics/0_how_to_work_with_onnx.ipynb
+++ b/notebooks/basics/0_how_to_work_with_onnx.ipynb
@@ -31,7 +31,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -56,7 +56,7 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -98,7 +98,7 @@
},
{
"cell_type": "code",
- "execution_count": 3,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -119,7 +119,7 @@
},
{
"cell_type": "code",
- "execution_count": 4,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -154,7 +154,7 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -171,7 +171,7 @@
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -180,40 +180,9 @@
},
{
"cell_type": "code",
- "execution_count": 7,
- "metadata": {
- "scrolled": true
- },
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving '/tmp/simple_model.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fcdfc956b70>"
- ]
- },
- "execution_count": 7,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron('/tmp/simple_model.onnx')"
]
@@ -229,7 +198,7 @@
},
{
"cell_type": "code",
- "execution_count": 8,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -252,7 +221,7 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -270,7 +239,7 @@
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -289,7 +258,7 @@
},
{
"cell_type": "code",
- "execution_count": 11,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -308,29 +277,9 @@
},
{
"cell_type": "code",
- "execution_count": 12,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "The output of the ONNX model is: \n",
- "[[22. 13. 21. 8.]\n",
- " [ 0. 8. 11. 1.]\n",
- " [ 3. 12. 8. 2.]\n",
- " [ 0. 6. 1. 4.]]\n",
- "\n",
- "The output of the reference function is: \n",
- "[[22. 13. 21. 8.]\n",
- " [ 0. 8. 11. 1.]\n",
- " [ 3. 12. 8. 2.]\n",
- " [ 0. 6. 1. 4.]]\n",
- "\n",
- "The results are the same!\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"ref_output= expected_output(in1_values, in2_values, in3_values)\n",
"print(\"The output of the ONNX model is: \\n{}\".format(output[0]))\n",
@@ -369,7 +318,7 @@
},
{
"cell_type": "code",
- "execution_count": 13,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -386,7 +335,7 @@
},
{
"cell_type": "code",
- "execution_count": 14,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -410,7 +359,7 @@
},
{
"cell_type": "code",
- "execution_count": 15,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -433,19 +382,9 @@
},
{
"cell_type": "code",
- "execution_count": 16,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Found adder node: Add1\n",
- "Found adder node: Add2\n",
- "Found adder node: Add3\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"add_nodes = identify_adder_nodes(finn_model)\n",
"for node in add_nodes:\n",
@@ -461,7 +400,7 @@
},
{
"cell_type": "code",
- "execution_count": 17,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -490,7 +429,7 @@
},
{
"cell_type": "code",
- "execution_count": 18,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -520,19 +459,9 @@
},
{
"cell_type": "code",
- "execution_count": 19,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Found following pair that could be replaced by a sum node:\n",
- "Add1\n",
- "Add2\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"for node in add_nodes:\n",
" add_pairs = adder_pair(finn_model, node)\n",
@@ -556,18 +485,9 @@
},
{
"cell_type": "code",
- "execution_count": 20,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "The new node gets the following inputs: \n",
- "['in1', 'in2', 'in3']\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"input_list = []\n",
"for i in range(len(substitute_pair)):\n",
@@ -591,7 +511,7 @@
},
{
"cell_type": "code",
- "execution_count": 21,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -607,7 +527,7 @@
},
{
"cell_type": "code",
- "execution_count": 22,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -628,7 +548,7 @@
},
{
"cell_type": "code",
- "execution_count": 23,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -656,7 +576,7 @@
},
{
"cell_type": "code",
- "execution_count": 25,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -666,40 +586,9 @@
},
{
"cell_type": "code",
- "execution_count": 26,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "\n",
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/tmp/simple_model1.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fcdfc130cc0>"
- ]
- },
- "execution_count": 26,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron('/tmp/simple_model1.onnx')"
]
@@ -713,7 +602,7 @@
},
{
"cell_type": "code",
- "execution_count": 27,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -723,29 +612,9 @@
},
{
"cell_type": "code",
- "execution_count": 28,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "The output of the manipulated ONNX model is: \n",
- "[[22. 13. 21. 8.]\n",
- " [ 0. 8. 11. 1.]\n",
- " [ 3. 12. 8. 2.]\n",
- " [ 0. 6. 1. 4.]]\n",
- "\n",
- "The output of the reference function is: \n",
- "[[22. 13. 21. 8.]\n",
- " [ 0. 8. 11. 1.]\n",
- " [ 3. 12. 8. 2.]\n",
- " [ 0. 6. 1. 4.]]\n",
- "\n",
- "The results are the same!\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"print(\"The output of the manipulated ONNX model is: \\n{}\".format(output[0]))\n",
"print(\"\\nThe output of the reference function is: \\n{}\".format(ref_output))\n",
diff --git a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb
index 69645a350..e2762024a 100644
--- a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb
+++ b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb
@@ -55,7 +55,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -77,7 +77,7 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -109,38 +109,9 @@
},
{
"cell_type": "code",
- "execution_count": 3,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving '/workspace/finn/end2end_cnv_w1a1_tidy.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f912af76550>"
- ]
- },
- "execution_count": 3,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir+\"/end2end_cnv_w1a1_tidy.onnx\")"
]
@@ -163,18 +134,9 @@
},
{
"cell_type": "code",
- "execution_count": 4,
- "metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "/scratch/users/mirzam/finn/deps/finn-base/src/finn/transformation/infer_data_layouts.py:119: UserWarning: Assuming 4D input is NCHW\n",
- " warnings.warn(\"Assuming 4D input is NCHW\")\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.util.pytorch import ToTensor\n",
"from finn.transformation.merge_onnx_models import MergeONNXModels\n",
@@ -198,7 +160,7 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -220,39 +182,9 @@
},
{
"cell_type": "code",
- "execution_count": 6,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/workspace/finn/end2end_cnv_w1a1_pre_post.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f8ffd85a760>"
- ]
- },
- "execution_count": 6,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir+\"/end2end_cnv_w1a1_pre_post.onnx\")"
]
@@ -275,7 +207,7 @@
},
{
"cell_type": "code",
- "execution_count": 7,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -318,39 +250,9 @@
},
{
"cell_type": "code",
- "execution_count": 8,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/workspace/finn/end2end_cnv_w1a1_streamlined.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f91ac6e6f70>"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir+\"/end2end_cnv_w1a1_streamlined.onnx\")"
]
@@ -366,22 +268,9 @@
},
{
"cell_type": "code",
- "execution_count": 9,
- "metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "/scratch/users/mirzam/finn/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py:598: UserWarning: Clipping some thresholds in XnorPopcountMatMul_0\n",
- " warnings.warn(\"Clipping some thresholds in %s\" % self.onnx_node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py:598: UserWarning: Clipping some thresholds in XnorPopcountMatMul_4\n",
- " warnings.warn(\"Clipping some thresholds in %s\" % self.onnx_node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py:598: UserWarning: Clipping some thresholds in MatrixVectorActivation_MatMul_0\n",
- " warnings.warn(\"Clipping some thresholds in %s\" % self.onnx_node.name)\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls\n",
"from finn.transformation.fpgadataflow.create_dataflow_partition import (\n",
@@ -428,41 +317,9 @@
},
{
"cell_type": "code",
- "execution_count": 10,
- "metadata": {
- "scrolled": false
- },
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/workspace/finn/end2end_cnv_w1a1_dataflow_parent.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f8ffd85ae20>"
- ]
- },
- "execution_count": 10,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir + \"/end2end_cnv_w1a1_dataflow_parent.onnx\")"
]
@@ -476,39 +333,9 @@
},
{
"cell_type": "code",
- "execution_count": 11,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/workspace/finn/end2end_cnv_w1a1_dataflow_model.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f8ffd832280>"
- ]
- },
- "execution_count": 11,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir + \"/end2end_cnv_w1a1_dataflow_model.onnx\")"
]
@@ -522,7 +349,7 @@
},
{
"cell_type": "code",
- "execution_count": 12,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -566,39 +393,9 @@
},
{
"cell_type": "code",
- "execution_count": 13,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/workspace/finn/end2end_cnv_w1a1_folded.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f8ff1243af0>"
- ]
- },
- "execution_count": 13,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir + \"/end2end_cnv_w1a1_folded.onnx\")"
]
@@ -621,22 +418,9 @@
},
{
"cell_type": "code",
- "execution_count": 14,
- "metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "/workspace/finn/src/finn/transformation/fpgadataflow/floorplan.py:107: UserWarning: 32 nodes have no entry in the provided floorplan, SLR was set to -1\n",
- " warnings.warn(\n",
- "/workspace/finn/src/finn/transformation/fpgadataflow/insert_fifo.py:154: UserWarning: Overriding input FIFO depth to 32\n",
- " warnings.warn(\"Overriding input FIFO depth to 32\")\n",
- "/workspace/finn/src/finn/transformation/fpgadataflow/insert_fifo.py:200: UserWarning: Overriding output FIFO depth to 32\n",
- " warnings.warn(\"Overriding output FIFO depth to 32\")\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"test_pynq_board = \"Pynq-Z2\"\n",
"target_clk_ns = 10\n",
@@ -660,22 +444,9 @@
},
{
"cell_type": "code",
- "execution_count": 15,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Welcome to PYNQ Linux, based on Ubuntu 18.04 (GNU/Linux 4.19.0-xilinx-v2019.1 armv7l)\r\n",
- "\r\n",
- " * Super-optimized for small spaces - read how we shrank the memory\r\n",
- " footprint of MicroK8s to make it the smallest full K8s around.\r\n",
- "\r\n",
- " https://ubuntu.com/blog/microk8s-memory-optimisation\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import os\n",
"\n",
@@ -695,7 +466,7 @@
},
{
"cell_type": "code",
- "execution_count": 16,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -708,20 +479,9 @@
},
{
"cell_type": "code",
- "execution_count": 17,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "'/home/xilinx/finn_dev_jduarte/pynq_deployment_yrxnwrak'"
- ]
- },
- "execution_count": 17,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"target_dir_pynq = target_dir + \"/\" + model.get_metadata_prop(\"pynq_deployment_dir\").split(\"/\")[-1]\n",
"target_dir_pynq"
@@ -729,24 +489,9 @@
},
{
"cell_type": "code",
- "execution_count": 18,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "total 4240\r\n",
- "-rw-rw-r-- 1 xilinx xilinx 18616 Jun 28 20:42 driver_base.py\r\n",
- "-rw-r--r-- 1 xilinx xilinx 4868 Jun 28 20:42 driver.py\r\n",
- "drwxr-xr-x 4 xilinx xilinx 4096 Jun 28 20:42 finn\r\n",
- "-rw-r--r-- 1 xilinx xilinx 4045671 Jun 28 20:42 resizer.bit\r\n",
- "-rw-r--r-- 1 xilinx xilinx 247083 Jun 28 20:42 resizer.hwh\r\n",
- "drwxr-xr-x 2 xilinx xilinx 4096 Jun 28 20:42 runtime_weights\r\n",
- "-rw-rw-r-- 1 xilinx xilinx 4107 Jun 28 20:42 validate.py\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ssh {options} {username}@{ip} -p {port} 'ls -l {target_dir_pynq}'"
]
@@ -760,32 +505,9 @@
},
{
"cell_type": "code",
- "execution_count": 19,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "<matplotlib.image.AxesImage at 0x7f917faeb6d0>"
- ]
- },
- "execution_count": 19,
- "metadata": {},
- "output_type": "execute_result"
- },
- {
- "data": {
- "image/png": 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zPWhVlTsK4C9WcrJcLkezfwaGuPRWb4TdLOV5JtF1u3ZQ2/5nuOQ1U7iW2po2Gxwf3crltVcO/gu1/c7v/Rm1/eLnfN78fKRNUvVscHzi1Nt0Tuw9f67GbXlwaWgoF86y29rNfZ8+wyW0esa3hUY3cVujEc6kW4y0eKos8rp785EaevUml/NqlRPUtqkQzujb0sez6Jbq4Tmxu/eywe7unw4Mf3O5eUKIKwt9g06IRFCwC5EICnYhEkHBLkQiKNiFSISOFpzM5XLo7QtnLw2NjNB5dQu7WckV6ZyuvgFqK5d5QcG33j5Fbbd+8P1hP+Z4O6me/nDWFQCMnzhObYdef53a6g3enihH6g3Oz0zTOf0bxqhteprLUIN9vBjl+667MTj+9Auv0jnPvnqU2m69/Q+prVDkEtXhQ4eC49Oz/HnFimJWFrm8tnOUS7rdvbyg6vBweJ7neQHOejVc+NJJVimgO7sQyaBgFyIRFOxCJIKCXYhEULALkQgKdiESoaPSm3sTzXpY8hgc5oX85hfDhQgXGrzvVpbx97Ed27dR2+sv88yr6YWwxNbXyzPstl9DTTj2Oi++eOLkOLV9+MMfpLaFhbA01L9lK50zvIUX53xrkktli0tcciz2hvuvDWzcTufc1M9flzNnwv3QAODosReobX4xLFNOTXMJbePGjdQ26Px12dnHJdFNA7wHW8HCmYDVGu9v10skthx4TOjOLkQiKNiFSAQFuxCJoGAXIhEU7EIkQkd345v1GmbPhXczuyO1vZYq4V1Oa3L3zfiu5Mgwb5/0eu4wtU1Mhlv4nMv4rvRgH6+td/2NPCHn8DFeM67GuyRhaiasduzevZvO2b2LSwbHxnkCzcsvv0ht586Gk1OKJa66DPXxRJLjL3NV4NQ5XtfOSLJUFmm9FWsdtpPnmWBHP08M6srxpJalSvj6aTZ5bcNanRyPX/a6swuRCgp2IRJBwS5EIijYhUgEBbsQiaBgFyIRVtL+aTuAvwMwitbG/j53/5qZDQP4HoCr0GoB9Ul3D/f8abO0tITDh8LS1o7dv0HndeXC0luzyhMF8l0RGSRi6+/n0lDfQLiu3fXXv4/O+cmPHqO2hWle765neBO1HTo+QW3bt4WTcna972Y6p1Tkl8HVO3iSz9Qkf7lfORhOKGo61w1PTPFEkhmSDAUAlQaXbWemwlLkps086eatc7w+3fB2LpeeK3E/0OTPbaoefm6e59fpEjleFTzhZiV39jqAv3H3GwB8CMBfmdkNAO4D8Li77wbwePtnIcQVyrLB7u7j7v5s+/EsgIMAtgK4C8AD7V97AMDH18hHIcRl4KL+ZjezqwDcBOBJAKPuv0zuPYXWx3whxBXKioPdzPoA/ADA59z9Xd9PdHcH+aKemd1jZvvNbP/sLC8YIIRYW1YU7GZWQCvQv+PuP2wPnzazsbZ9DEBw18jd97n7XnffG9v8EkKsLcsGu5kZWv3YD7r7Vy4wPQrg7vbjuwE8cvndE0JcLlaS9fa7AD4D4EUze7499nkAXwLwkJl9FsAxAJ9c7kALS3U8fygsG+248RY6r4lwtpmxzB8AaPL0n5nZWWqbmjpLbRuG9wTH77zjI3TOng9cT20P/fBhajPjEsrg4BC1bd0SlpT6Bsp0TlYPry8ADG/ml8jYrhq1TXeHZaPnXuD14sbneEqZF3g7r8HNPItx5JqwVJZFZK2Gcz9e83D7MgA4dIrLg8WMH3OxUgmOL0Qu73ozfH3MNnh24LLB7u4/A8A8/f3l5gshrgz0DTohEkHBLkQiKNiFSAQFuxCJoGAXIhE6WnCy0jC8Pt0dtJ1t8AKAXghLE7kqL4boRJoAgFyO27aM8Wyzf/074cyxrgKXXHbt5G2X/uhPP0Vt33/4H6jt7Cn+vMenw8ULK5VDdE4RXOOZXOS2Q8d41h6qYVnOR3iG4NCmcJFKAGhGKim2vvNF5nWFj9m0cCFKAKhF2opNN/i5ugr8mF15Lr3NWzjLrlbg5/JmeH0bEclWd3YhEkHBLkQiKNiFSAQFuxCJoGAXIhEU7EIkQkelt6WG4fWp8PvLIz/jfcP27BwJjm8u8gyknkIkW2sz7782NsKzq665mhQpdF5McPzMOWq7/0Eurz37/CvUxnrfAQBNBHT+vu4NfrxGia9HI8eloTzCEms9Ig3Vc+E5ANAVu1IjWWqVavh5e47PyUcy4rIm7+vnFS5T1sHnFZphHzPjr1m1FvY/0uJQd3YhUkHBLkQiKNiFSAQFuxCJoGAXIhE6uhvfgGEuF04WePzZ1+m8N94Mt4y647dvoHOu2cLb9Bw5HG5NBAC3ffBGausiiQmzVb7D/NA/Pk1tz71yktoW6pFWQpHd4lwh/P7djNTkyxnfRY7tWjeaPAFoieww1xp8jhmvabeESFKI8+eWz5Od7ozf53p6eEJLEdz/Bt9wR8N4qDXIxHqNvy7F/nJw3HL8PLqzC5EICnYhEkHBLkQiKNiFSAQFuxCJoGAXIhGWld7MbDuAv0OrJbMD2OfuXzOzLwL4cwBn2r/6eXd/LHqyfB4bRjYGbZPnuXwyfn4qOP7zF3irm0ZtZ8QTLq1s3EySXQBYFpbDntr/Ep3zDz/9BbUtNXnNNeS59JbLXfx7dGOJJ7t4RJZrRuS1mOTFWigV8vySs4xLmMj4a5aPzMuy8PliTUazyPrmnMuDjUiyUTMiHTLNbvNmLh/3D4Rtb5Yi68Q9+CV1AH/j7s+aWT+AZ8zsx23bV939v67gGEKIdWYlvd7GAYy3H8+a2UEAvGSqEOKK5KI+D5rZVQBuAvBke+heMztgZvebGW8tKoRYd1Yc7GbWB+AHAD7n7jMAvg7gGgB70Lrzf5nMu8fM9pvZ/voib5UshFhbVhTs1qrC/wMA33H3HwKAu59294a7NwF8A0Cwwbq773P3ve6+N9/NG0EIIdaWZYPdzAzANwEcdPevXDA+dsGvfQIA35IWQqw7K9mN/10AnwHwopk93x77PIBPm9ketOS4owD+YrkDmRmVSQoFLjXVK2E54ejpGTpnaf4gtd1283XU1l0eo7bpSlgi+ecn99M5FeeZS7U6l3FKJZ7Z1ozUQVtYCLcSipFFMrKMJ70h0pEJJSJ5xbKyELFZicuU3d28dl2eSH21SEbZ7Pw8tTUiMuVSnb8ug0PhOooAMDoWtvVFCu8tzob/JPbItbGS3fifAQi95FFNXQhxZaFv0AmRCAp2IRJBwS5EIijYhUgEBbsQidDRgpNwR7NOsqhiGUNZWIaqgmc7TcwtUduzr/FCj3cucGll1sNyx4nz/JuBpT6eXVVf4P5Xlrj/PT0RqYm0vYodz3Lcj1ykXVMsg82JjOaR+0shIjfO1Xj2XbXOpTImy8Uy9mIS2nyk9VZfmctr5Y285Vi1Hj7ma6/yrM4CyUasVbl/urMLkQgKdiESQcEuRCIo2IVIBAW7EImgYBciETosvQFgWUPO5Y4sCxfrazqXhRo5XuDv6ASXyu5/iOf3fPT2vcHxIyfPBMcBYKERK0IYkaG6eOHArMhtPaSHWbGby1qLs1y6imWHeUSiKpCMrSzPX7PYubJIUclYH7vFhbmLnhM7V3lomNo2jPKMybPnJqlt6uyp8PhbvCfhtbt2hQ0RSVF3diESQcEuRCIo2IVIBAW7EImgYBciERTsQiRCR6W3LJ9huFwO2ioVLofNL4YzeYoZz/6qR2ShXKS45RNPHaC2IyfD2XLT87xw5OTcIrWRZCcAQG9vJFsuUlSwVAo/t3xEruvq5hllWSQjLl/gx2yQ+0g9InlZxObOfWzU+PpXa+FF7u7iUuTIhg3UNjTC5bVqJHNzqRgpHkn6szXzXD6er4Svq2ZEwtadXYhEULALkQgKdiESQcEuRCIo2IVIhGV3482sC8ATAErt3/++u3/BzHYBeBDABgDPAPiMu0f2lwFvOpbILmIp8raz1AjvthYyvhtc55vI8Bw/Wa6b74IfIwkvuUhyR73Gd5hjikGlUqG2+Uh7ohx5bmyXHgB6i3zXtzuSQJPLcf+LXeHzdffw9a1WeSLM2UmeSNIEn5cvhNdjaKCXzhkdLlPb5s08EWZqntf5m506T21z01PB8fIwP9fZM2eD4/VIMtFK7uxLAD7q7h9Aqz3zHWb2IQB/C+Cr7n4tgPMAPruCYwkh1ollg91bvJMnWGj/cwAfBfD99vgDAD6+Fg4KIS4PK+3PnrU7uE4A+DGANwFMuf+yRelxAFvXxEMhxGVhRcHu7g133wNgG4BbAFy/0hOY2T1mtt/M9tcWeItlIcTaclG78e4+BeCfAHwYQNnsl429twE4Qebsc/e97r630DOwGl+FEKtg2WA3s41mVm4/7gbwMQAH0Qr6P23/2t0AHlkjH4UQl4GVJMKMAXjAzDK03hwecve/N7NXADxoZv8ZwHMAvrncgZrNJpYWw5JSKTM6r4d42azxJJNI1yI0wSWjWCJBk7SbqlcjCRwN/rxiLYhitmYkEYZJb+fPc+lnMrKOA31cohqM1GMbILXwusClvEaTS1d5iyTrlPiLvVQJH7OU569L7Fz1hemIjfs/N3WO2pokWaerxCXRCquTZ5HnRS1t3P0AgJsC44fR+vtdCPErgL5BJ0QiKNiFSAQFuxCJoGAXIhEU7EIkgsUknst+MrMzAI61fxwBEE7d6Szy493Ij3fzq+bHTnffGDJ0NNjfdWKz/e4ebp4mP+SH/LjsfuhjvBCJoGAXIhHWM9j3reO5L0R+vBv58W5+bfxYt7/ZhRCdRR/jhUiEdQl2M7vDzF4zs0Nmdt96+ND246iZvWhmz5vZ/g6e934zmzCzly4YGzazH5vZG+3/h9bJjy+a2Yn2mjxvZnd2wI/tZvZPZvaKmb1sZn/dHu/omkT86OiamFmXmT1lZi+0/fhP7fFdZvZkO26+Z2a84moId+/oPwAZWmWtrgZQBPACgBs67Ufbl6MARtbhvLcBuBnASxeM/RcA97Uf3wfgb9fJjy8C+PcdXo8xADe3H/cDeB3ADZ1ek4gfHV0TAAagr/24AOBJAB8C8BCAT7XH/zuAv7yY467Hnf0WAIfc/bC3Sk8/COCudfBj3XD3JwC8tzbyXWgV7gQ6VMCT+NFx3H3c3Z9tP55FqzjKVnR4TSJ+dBRvcdmLvK5HsG8F8PYFP69nsUoH8CMze8bM7lknH95h1N3H249PARhdR1/uNbMD7Y/5a/7nxIWY2VVo1U94Euu4Ju/xA+jwmqxFkdfUN+hudfebAfwhgL8ys9vW2yGg9c6O1hvRevB1ANeg1SNgHMCXO3ViM+sD8AMAn3P3d1Un7eSaBPzo+Jr4Koq8MtYj2E8A2H7Bz7RY5Vrj7ifa/08AeBjrW3nntJmNAUD7/4n1cMLdT7cvtCaAb6BDa2JmBbQC7Dvu/sP2cMfXJOTHeq1J+9xTuMgir4z1CPanAexu7ywWAXwKwKOddsLMes2s/53HAP4AwEvxWWvKo2gV7gTWsYDnO8HV5hPowJqYmaFVw/Cgu3/lAlNH14T50ek1WbMir53aYXzPbuOdaO10vgngP6yTD1ejpQS8AODlTvoB4LtofRysofW312fR6pn3OIA3APwEwPA6+fFtAC8COIBWsI11wI9b0fqIfgDA8+1/d3Z6TSJ+dHRNAPwWWkVcD6D1xvIfL7hmnwJwCMD/BlC6mOPqG3RCJELqG3RCJIOCXYhEULALkQgKdiESQcEuRCIo2IVIBAW7EImgYBciEf4vt7E0CllzrOkAAAAASUVORK5CYII=\n",
- "text/plain": [
- "<Figure size 432x288 with 1 Axes>"
- ]
- },
- "metadata": {
- "needs_background": "light"
- },
- "output_type": "display_data"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import pkg_resources as pk\n",
"import matplotlib.pyplot as plt\n",
@@ -806,7 +528,7 @@
},
{
"cell_type": "code",
- "execution_count": 20,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -823,20 +545,9 @@
},
{
"cell_type": "code",
- "execution_count": 21,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "array([[3.]], dtype=float32)"
- ]
- },
- "execution_count": 21,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"ret[oname]"
]
@@ -868,20 +579,9 @@
},
{
"cell_type": "code",
- "execution_count": 22,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "[sudo] password for xilinx: Requirement already satisfied: dataset_loading from git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading in /usr/local/lib/python3.6/dist-packages\n",
- "Requirement already satisfied: Pillow in /usr/lib/python3/dist-packages (from dataset_loading)\n",
- "Requirement already satisfied: scipy in /usr/lib/python3/dist-packages (from dataset_loading)\n",
- "Connection to 99.121.248.96 closed.\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ssh {options} -t {username}@{ip} -p {port} 'echo {password} | sudo -S pip3 install git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading'"
]
@@ -899,31 +599,9 @@
},
{
"cell_type": "code",
- "execution_count": 23,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "[sudo] password for xilinx: Tar File found in dest_dir. Not Downloading again\n",
- "Extracting Python CIFAR10 data.\n",
- "Files extracted\n",
- "batch 1 / 10 : total OK 851 NOK 149\n",
- "batch 2 / 10 : total OK 1683 NOK 317\n",
- "batch 3 / 10 : total OK 2522 NOK 478\n",
- "batch 4 / 10 : total OK 3370 NOK 630\n",
- "batch 5 / 10 : total OK 4207 NOK 793\n",
- "batch 6 / 10 : total OK 5044 NOK 956\n",
- "batch 7 / 10 : total OK 5887 NOK 1113\n",
- "batch 8 / 10 : total OK 6728 NOK 1272\n",
- "batch 9 / 10 : total OK 7570 NOK 1430\n",
- "batch 10 / 10 : total OK 8419 NOK 1581\n",
- "Final accuracy: 84.190000\n",
- "Connection to 99.121.248.96 closed.\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ssh {options} -t {username}@{ip} -p {port} 'cd {target_dir_pynq}; echo {password} | sudo -S python3.6 validate.py --dataset cifar10 --batchsize 1000'"
]
diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb
index d34a77b13..2e19cda3d 100644
--- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb
+++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb
@@ -42,7 +42,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -77,7 +77,7 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -99,38 +99,9 @@
},
{
"cell_type": "code",
- "execution_count": 3,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving '/workspace/finn/tfc_w1_a1.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fe30c65e828>"
- ]
- },
- "execution_count": 3,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir+\"/tfc_w1_a1.onnx\")"
]
@@ -144,7 +115,7 @@
},
{
"cell_type": "code",
- "execution_count": 4,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -232,7 +203,7 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -260,40 +231,9 @@
},
{
"cell_type": "code",
- "execution_count": 8,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "\n",
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/workspace/finn/tfc_w1_a1_tidy.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fe2d26a7da0>"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir+\"/tfc_w1_a1_tidy.onnx\")"
]
@@ -313,18 +253,9 @@
},
{
"cell_type": "code",
- "execution_count": 7,
- "metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "/scratch/users/mirzam/finn/deps/finn-base/src/finn/transformation/infer_data_layouts.py:119: UserWarning: Assuming 4D input is NCHW\n",
- " warnings.warn(\"Assuming 4D input is NCHW\")\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.util.pytorch import ToTensor\n",
"from finn.transformation.merge_onnx_models import MergeONNXModels\n",
@@ -360,38 +291,9 @@
},
{
"cell_type": "code",
- "execution_count": 9,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving '/scratch/users/mirzam/finn/tfc_w1_a1_pre_post.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f88efb6cd60>"
- ]
- },
- "execution_count": 9,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.transformation.insert_topk import InsertTopK\n",
"\n",
@@ -429,52 +331,9 @@
},
{
"cell_type": "code",
- "execution_count": 10,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "class Streamline(Transformation):\n",
- " \"\"\"Apply the streamlining transform, see arXiv:1709.04060.\"\"\"\n",
- "\n",
- " def apply(self, model):\n",
- " streamline_transformations = [\n",
- " ConvertSubToAdd(),\n",
- " ConvertDivToMul(),\n",
- " BatchNormToAffine(),\n",
- " ConvertSignToThres(),\n",
- " MoveMulPastMaxPool(),\n",
- " MoveScalarLinearPastInvariants(),\n",
- " AbsorbSignBiasIntoMultiThreshold(),\n",
- " MoveAddPastMul(),\n",
- " MoveScalarAddPastMatMul(),\n",
- " MoveAddPastConv(),\n",
- " MoveScalarMulPastMatMul(),\n",
- " MoveScalarMulPastConv(),\n",
- " MoveAddPastMul(),\n",
- " CollapseRepeatedAdd(),\n",
- " CollapseRepeatedMul(),\n",
- " MoveMulPastMaxPool(),\n",
- " AbsorbAddIntoMultiThreshold(),\n",
- " FactorOutMulSignMagnitude(),\n",
- " AbsorbMulIntoMultiThreshold(),\n",
- " Absorb1BitMulIntoMatMul(),\n",
- " Absorb1BitMulIntoConv(),\n",
- " RoundAndClipThresholds(),\n",
- " ]\n",
- " for trn in streamline_transformations:\n",
- " model = model.transform(trn)\n",
- " model = model.transform(RemoveIdentityOps())\n",
- " model = model.transform(GiveUniqueNodeNames())\n",
- " model = model.transform(GiveReadableTensorNames())\n",
- " model = model.transform(InferDataTypes())\n",
- " return (model, False)\n",
- "\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.transformation.streamline import Streamline\n",
"showSrc(Streamline)"
@@ -491,39 +350,9 @@
},
{
"cell_type": "code",
- "execution_count": 11,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:5905\n",
- "Serving '/scratch/users/mirzam/finn/tfc_w1_a1_streamlined.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f88efafd310>"
- ]
- },
- "execution_count": 11,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.transformation.streamline.reorder import MoveScalarLinearPastInvariants\n",
"import finn.transformation.streamline.absorb as absorb\n",
@@ -550,39 +379,9 @@
},
{
"cell_type": "code",
- "execution_count": 12,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:5905\n",
- "Serving '/scratch/users/mirzam/finn/tfc_w1a1_ready_for_hls_conversion.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f88efb54ca0>"
- ]
- },
- "execution_count": 12,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount\n",
"from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds\n",
@@ -630,41 +429,9 @@
},
{
"cell_type": "code",
- "execution_count": 13,
- "metadata": {
- "scrolled": false
- },
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:5905\n",
- "Serving '/scratch/users/mirzam/finn/tfc_w1_a1_hls_layers.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f8a8012a730>"
- ]
- },
- "execution_count": 13,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls\n",
"model = ModelWrapper(build_dir+\"/tfc_w1a1_ready_for_hls_conversion.onnx\")\n",
@@ -695,39 +462,9 @@
},
{
"cell_type": "code",
- "execution_count": 14,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:5905\n",
- "Serving '/scratch/users/mirzam/finn/tfc_w1_a1_dataflow_parent.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f88efb54970>"
- ]
- },
- "execution_count": 14,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.transformation.fpgadataflow.create_dataflow_partition import CreateDataflowPartition\n",
"\n",
@@ -746,39 +483,9 @@
},
{
"cell_type": "code",
- "execution_count": 15,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:5905\n",
- "Serving '/scratch/users/mirzam/build_files/dataflow_partition_do4n5hd_/partition_0.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f88eda0af10>"
- ]
- },
- "execution_count": 15,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.custom_op.registry import getCustomOp\n",
"sdp_node = parent_model.get_nodes_by_op_type(\"StreamingDataflowPartition\")[0]\n",
@@ -796,7 +503,7 @@
},
{
"cell_type": "code",
- "execution_count": 16,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -823,60 +530,9 @@
},
{
"cell_type": "code",
- "execution_count": 17,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "CustomOp wrapper is of class Thresholding_Batch\n"
- ]
- },
- {
- "data": {
- "text/plain": [
- "{'PE': ('i', True, 0),\n",
- " 'NumChannels': ('i', True, 0),\n",
- " 'numSteps': ('i', True, 1),\n",
- " 'ram_style': ('s', False, 'distributed', {'block', 'distributed'}),\n",
- " 'inputDataType': ('s', True, ''),\n",
- " 'weightDataType': ('s', True, ''),\n",
- " 'outputDataType': ('s', True, ''),\n",
- " 'inFIFODepth': ('i', False, 2),\n",
- " 'outFIFODepth': ('i', False, 2),\n",
- " 'numInputVectors': ('ints', False, [1]),\n",
- " 'ActVal': ('i', False, 0),\n",
- " 'mem_mode': ('s', False, 'const', {'const', 'decoupled'}),\n",
- " 'runtime_writeable_weights': ('i', False, 0, {0, 1}),\n",
- " 'backend': ('s', True, 'fpgadataflow'),\n",
- " 'code_gen_dir_cppsim': ('s', False, ''),\n",
- " 'code_gen_dir_ipgen': ('s', False, ''),\n",
- " 'executable_path': ('s', False, ''),\n",
- " 'ipgen_path': ('s', False, ''),\n",
- " 'ip_path': ('s', False, ''),\n",
- " 'ip_vlnv': ('s', False, ''),\n",
- " 'exec_mode': ('s', False, '', {'', 'cppsim', 'rtlsim'}),\n",
- " 'cycles_rtlsim': ('i', False, 0),\n",
- " 'cycles_estimate': ('i', False, 0),\n",
- " 'rtlsim_trace': ('s', False, ''),\n",
- " 'res_estimate': ('s', False, ''),\n",
- " 'res_hls': ('s', False, ''),\n",
- " 'res_synth': ('s', False, ''),\n",
- " 'rtlsim_so': ('s', False, ''),\n",
- " 'slr': ('i', False, -1),\n",
- " 'mem_port': ('s', False, ''),\n",
- " 'partition_id': ('i', False, 0),\n",
- " 'device_id': ('i', False, 0),\n",
- " 'output_hook': ('s', False, ''),\n",
- " 'hls_version': ('s', False, 'vitis_hls', {'vitis_hls', 'vivado_hls'})}"
- ]
- },
- "execution_count": 17,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"fc0 = model.graph.node[0]\n",
"fc0w = getCustomOp(fc0)\n",
@@ -896,7 +552,7 @@
},
{
"cell_type": "code",
- "execution_count": 18,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -941,41 +597,9 @@
},
{
"cell_type": "code",
- "execution_count": 19,
- "metadata": {
- "scrolled": true
- },
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Stopping http://0.0.0.0:5905\n",
- "Serving '/scratch/users/mirzam/finn/tfc_w1_a1_set_folding_factors.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f88efb26400>"
- ]
- },
- "execution_count": 19,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"model.save(build_dir+\"/tfc_w1_a1_set_folding_factors.onnx\")\n",
"showInNetron(build_dir+\"/tfc_w1_a1_set_folding_factors.onnx\")"
@@ -1001,17 +625,9 @@
},
{
"cell_type": "code",
- "execution_count": 43,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "dict_keys(['Ultra96', 'Pynq-Z1', 'Pynq-Z2', 'ZCU102', 'ZCU104'])\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"# print the names of the supported PYNQ boards\n",
"from finn.util.basic import pynq_part_map\n",
@@ -1020,7 +636,7 @@
},
{
"cell_type": "code",
- "execution_count": 44,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -1039,7 +655,7 @@
},
{
"cell_type": "code",
- "execution_count": 45,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -1050,7 +666,7 @@
},
{
"cell_type": "code",
- "execution_count": 46,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -1068,40 +684,9 @@
},
{
"cell_type": "code",
- "execution_count": 99,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "\n",
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/workspace/finn/tfc_w1_a1_post_synthesis.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fe2ef58eb00>"
- ]
- },
- "execution_count": 99,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"showInNetron(build_dir + \"/tfc_w1_a1_post_synthesis.onnx\")"
]
@@ -1115,40 +700,9 @@
},
{
"cell_type": "code",
- "execution_count": 102,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "\n",
- "Stopping http://0.0.0.0:8081\n",
- "Serving '/tmp/finn_dev_maltanar/dataflow_partition2_b6c72_s0/df_model.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://0.0.0.0:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7fe2ef5a0e48>"
- ]
- },
- "execution_count": 102,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"model = ModelWrapper(build_dir + \"/tfc_w1_a1_post_synthesis.onnx\")\n",
"sdp_node_middle = getCustomOp(model.graph.node[1])\n",
@@ -1166,34 +720,9 @@
},
{
"cell_type": "code",
- "execution_count": 103,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "[key: \"pynq_driver_dir\"\n",
- "value: \"/tmp/finn_dev_maltanar/pynq_driver_kl300vbh\"\n",
- ", key: \"vivado_stitch_proj\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_stitch_proj_yy5ixo91\"\n",
- ", key: \"clk_ns\"\n",
- "value: \"10\"\n",
- ", key: \"wrapper_filename\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_stitch_proj_yy5ixo91/finn_vivado_stitch_proj.srcs/sources_1/bd/StreamingDataflowPartition_1/hdl/StreamingDataflowPartition_1_wrapper.v\"\n",
- ", key: \"vivado_stitch_vlnv\"\n",
- "value: \"xilinx_finn:finn:StreamingDataflowPartition_1:1.0\"\n",
- ", key: \"vivado_stitch_ifnames\"\n",
- "value: \"{\\'clk\\': [\\'ap_clk\\'], \\'rst\\': [\\'ap_rst_n\\'], \\'s_axis\\': [\\'s_axis_0\\'], \\'m_axis\\': [\\'m_axis_0\\'], \\'aximm\\': [], \\'axilite\\': []}\"\n",
- ", key: \"platform\"\n",
- "value: \"zynq-iodma\"\n",
- "]"
- ]
- },
- "execution_count": 103,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"model = ModelWrapper(postsynth_layers)\n",
"model.model.metadata_props"
@@ -1215,32 +744,9 @@
},
{
"cell_type": "code",
- "execution_count": 97,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "[key: \"pynq_driver_dir\"\n",
- "value: \"/tmp/finn_dev_maltanar/pynq_driver_kl300vbh\"\n",
- ", key: \"vivado_pynq_proj\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f\"\n",
- ", key: \"bitfile\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f/resizer.bit\"\n",
- ", key: \"hw_handoff\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f/resizer.hwh\"\n",
- ", key: \"vivado_synth_rpt\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f/synth_report.xml\"\n",
- ", key: \"platform\"\n",
- "value: \"zynq-iodma\"\n",
- "]"
- ]
- },
- "execution_count": 97,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"model = ModelWrapper(build_dir + \"/tfc_w1_a1_post_synthesis.onnx\")\n",
"model.model.metadata_props"
@@ -1255,20 +761,9 @@
},
{
"cell_type": "code",
- "execution_count": 98,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "NA\t\t\t finn_zynq_link.runs resizer.bit\t vivado.jou\r\n",
- "finn_zynq_link.cache\t finn_zynq_link.srcs resizer.hwh\t vivado.log\r\n",
- "finn_zynq_link.hw\t finn_zynq_link.xpr synth_project.sh\r\n",
- "finn_zynq_link.ip_user_files ip_config.tcl\t synth_report.xml\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ls {model.get_metadata_prop(\"vivado_pynq_proj\")}"
]
@@ -1307,21 +802,9 @@
},
{
"cell_type": "code",
- "execution_count": 1,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Welcome to PYNQ Linux, based on Ubuntu 18.04 (GNU/Linux 5.4.0-xilinx-v2020.1 armv7l)\r\n",
- "\r\n",
- " * Pure upstream Kubernetes 1.21, smallest, simplest cluster ops!\r\n",
- "\r\n",
- " https://microk8s.io/\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import os\n",
"\n",
@@ -1341,7 +824,7 @@
},
{
"cell_type": "code",
- "execution_count": 47,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -1360,68 +843,18 @@
},
{
"cell_type": "code",
- "execution_count": 48,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "[key: \"pynq_driver_dir\"\n",
- "value: \"/tmp/finn_dev_maltanar/pynq_driver_kl300vbh\"\n",
- ", key: \"vivado_pynq_proj\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f\"\n",
- ", key: \"bitfile\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f/resizer.bit\"\n",
- ", key: \"hw_handoff\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f/resizer.hwh\"\n",
- ", key: \"vivado_synth_rpt\"\n",
- "value: \"/tmp/finn_dev_maltanar/vivado_zynq_proj_kdf60v6f/synth_report.xml\"\n",
- ", key: \"platform\"\n",
- "value: \"zynq-iodma\"\n",
- ", key: \"pynq_ip\"\n",
- "value: \"192.168.2.99\"\n",
- ", key: \"pynq_port\"\n",
- "value: \"22\"\n",
- ", key: \"pynq_username\"\n",
- "value: \"xilinx\"\n",
- ", key: \"pynq_password\"\n",
- "value: \"xilinx\"\n",
- ", key: \"pynq_target_dir\"\n",
- "value: \"/home/xilinx/finn_tfc_end2end_example\"\n",
- ", key: \"pynq_deployment_dir\"\n",
- "value: \"/tmp/finn_dev_maltanar/pynq_deployment_3wrnn2sp\"\n",
- ", key: \"pynq_deploy_dir\"\n",
- "value: \"/tmp/finn_dev_maltanar/pynq_deployment_3wrnn2sp\"\n",
- ", key: \"exec_mode\"\n",
- "value: \"remote_pynq\"\n",
- "]"
- ]
- },
- "execution_count": 48,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"model.model.metadata_props"
]
},
{
"cell_type": "code",
- "execution_count": 106,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "'/home/xilinx/finn_tfc_end2end_example/pynq_deployment_3wrnn2sp'"
- ]
- },
- "execution_count": 106,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"target_dir_pynq = target_dir + \"/\" + model.get_metadata_prop(\"pynq_deployment_dir\").split(\"/\")[-1]\n",
"target_dir_pynq"
@@ -1429,27 +862,9 @@
},
{
"cell_type": "code",
- "execution_count": 107,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "total 4236\r\n",
- "-rw-r--r-- 1 xilinx xilinx 8490 Sep 21 11:06 driver.py\r\n",
- "drwxr-xr-x 4 xilinx xilinx 4096 Sep 21 11:06 finn\r\n",
- "-rw-r--r-- 1 xilinx xilinx 3264 Sep 21 12:05 input.npy\r\n",
- "-rw-r--r-- 1 root root 205 Sep 21 12:34 nw_metrics.txt\r\n",
- "-rw-r--r-- 1 root root 84 Sep 21 12:06 output.npy\r\n",
- "drwxrwxr-x 2 xilinx xilinx 4096 Sep 21 11:34 __pycache__\r\n",
- "-rw-r--r-- 1 xilinx xilinx 4045671 Sep 21 11:06 resizer.bit\r\n",
- "-rw-r--r-- 1 xilinx xilinx 246211 Sep 21 11:06 resizer.hwh\r\n",
- "-rw-r--r-- 1 root root 32 Sep 21 12:34 sds_trace_data.dat\r\n",
- "-rw-r--r-- 1 xilinx xilinx 1727 Sep 21 11:06 validate.py\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ssh {options} {username}@{ip} -p {port} 'ls -l {target_dir_pynq}'"
]
@@ -1463,32 +878,9 @@
},
{
"cell_type": "code",
- "execution_count": 2,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "<matplotlib.image.AxesImage at 0x7fcb96004cc0>"
- ]
- },
- "execution_count": 2,
- "metadata": {},
- "output_type": "execute_result"
- },
- {
- "data": {
- "image/png": "iVBORw0KGgoAAAANSUhEUgAAAPsAAAD4CAYAAAAq5pAIAAAAOXRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjMuMSwgaHR0cHM6Ly9tYXRwbG90bGliLm9yZy/d3fzzAAAACXBIWXMAAAsTAAALEwEAmpwYAAARYElEQVR4nO3dfYyVZXrH8d/FoDAw8iYRCaisG/5QqmUbgk1KyOKmxlUMbKJm/aPauAmarMmqTVqz/UOSaqJVa/pH3YStL9CsmiWoq0a7a82mWo1GNFQQW1CULGR4E5H3t+HqH/NgZ3We6549z3nOc9z7+0kmM3Ouec65OTM/zsv13Pdt7i4Af/xGNT0AAJ1B2IFMEHYgE4QdyARhBzIxupM3Zma89Z+ZUaPKH09OnTpV23VXvf6enp6wPjAw0PJ1183dbbjLK4XdzK6U9M+SeiT9q7vfV+X6cmU27O/mS6k/6ip/eKNHx38CqcCk6r29vaW1Q4cOhcem9PX1hfUDBw6U1lIt50mTJoX1zz77LKx3o5afxptZj6R/kfR9SRdLusHMLm7XwAC0V5XX7PMlfeTuW9z9uKSnJS1pz7AAtFuVsM+Q9Lsh328rLvs9ZrbMzNaa2doKtwWgotrfoHP3FZJWSLxBBzSpyiP7dknnDfl+ZnEZgC5UJezvSJptZt8yszMl/VDS8+0ZFoB2a/lpvLufNLPbJP1ag623x9z9g7aNLCPjx48P6wcPHmz5useMGRPWjx07FtZTbcFx48aF9ai9lmoppqSOj9prqT76vn37WhlSV6v0mt3dX5L0UpvGAqBGnC4LZIKwA5kg7EAmCDuQCcIOZIKwA5mwTq4um+vpsqled6qXffTo0bA+duzYlo9Nia676vWfffbZYb3qNNLofp06dWp47O7du8N6amrwyZMnw3qdyuaz88gOZIKwA5kg7EAmCDuQCcIOZIKwA5mg9fYNkGrNVfkd1nnddUtNDa6yem1q6m5qanCTS03TegMyR9iBTBB2IBOEHcgEYQcyQdiBTBB2IBP02TvgrLPOCuvRbqOSNHHixLB+4sSJ0lpqN9LUFNbPP/88rC9YsCCs33rrraW1VC/6jjvuCOtbt24N601OM20SfXYgc4QdyARhBzJB2IFMEHYgE4QdyARhBzJBn/0b4JFHHgnrUS871Wuuuox1b29vWI+ktk2+5JJLwvqmTZvC+vHjx0trZ5xxRnhsdO6ClP53HzlyJKzXqazPXmnLZjP7VNIBSQOSTrr7vCrXB6A+lcJeWOTue9pwPQBqxGt2IBNVw+6SfmNm75rZsuF+wMyWmdlaM1tb8bYAVFD1afwCd99uZudIesXM/sfdXxv6A+6+QtIKiTfogCZVemR39+3F512SnpU0vx2DAtB+LYfdzMab2Vmnv5Z0haQN7RoYgPaq8jR+mqRniz7taElPuvu/t2VUf2RSWzYvWrQorF922WVhPeqVHzx4MDw21W/u6+sL66nzNKI566m11x999NGWr1uS7rzzztLaW2+9FR5b93bSTWg57O6+RdKftnEsAGpE6w3IBGEHMkHYgUwQdiAThB3IBFNcu0Bqqubs2bPD+v79+0trEyZMCI+NpoFK6SmwVbZ8TrX9UlJLcO/du7e0tnTp0vDYdevWhfVUSzLV8qwTS0kDmSPsQCYIO5AJwg5kgrADmSDsQCYIO5CJdiw42TFRT7fOfnBK6thU/ZZbbgnrq1atCuszZ85s+bZTffZ77rknrK9evTqsn3nmmaW1K664Ijz2wQcfDOuprbCj2168eHF47LZt28L6nj3fvDVWeWQHMkHYgUwQdiAThB3IBGEHMkHYgUwQdiATHZ/Pnup3Rzo51naqOvd54cKFYf2iiy4qrY0bNy48dvTo+FSLNWvWhPUtW7aE9SpSyz3PmTMnrKfu90jq75T57AC6FmEHMkHYgUwQdiAThB3IBGEHMkHYgUx0vM8+alT5/y9V54XXqcpc+lOnTlW67eg+S9VPnjwZHjt+/PiwfujQobCe2o46+p2l5tJfffXVYf3pp58O61X67Kk17VP3a5Na7rOb2WNmtsvMNgy5bIqZvWJmm4vPk9s5WADtN5Kn8U9IuvIrl90l6VV3ny3p1eJ7AF0sGXZ3f03SV/fRWSJpZfH1SklL2zssAO3W6hp009y9v/h6h6RpZT9oZsskLWvxdgC0SeUFJ93dow0b3X2FpBUSGzsCTWq19bbTzKZLUvF5V/uGBKAOrYb9eUk3FV/fJOlX7RkOgLok++xm9pSk70qaKmmnpLslPSfpl5LOl7RV0vXuXr4Z9v9fV21P46uuG1+1Hkn1ZFN7qEf7r1fV29sb1o8cORLWU+cAVDnH4MILLwzrH3/8ccvXnRpXak36lMOHD1c6voqyPnvyNbu731BS+l6lEQHoKE6XBTJB2IFMEHYgE4QdyARhBzLBls2FVAtyYGAgrEd6enrCetVlh6M2UarFlJrCmpK6/mjb5KgmSYsWLWppTKdFv9MTJ06Ex6amuFb5e2gKj+xAJgg7kAnCDmSCsAOZIOxAJgg7kAnCDmSiq/rsdW7nXHU55yrqvu0DBw6U1lL94lSvO3V8qk8fLRedWsb6uuuuC+tHjx4N62PHji2tpfrsqd9Zk1syt4pHdiAThB3IBGEHMkHYgUwQdiAThB3IBGEHMtHxPns0t7ube+XRksmp5ZRT6txW+dJLLw2PnTNnTlhPLSX93HPPhfVI1AeXpIULF4b1Klt4p5ahjs5dkKovwd0EHtmBTBB2IBOEHcgEYQcyQdiBTBB2IBOEHchEx/vs0Zz1OvvoqbnyqXndUU949Oj4bly6dGlYTx2/ZMmSsD5mzJjS2ty5c8NjJ02aFNZTvezXX3+95eNnz54dHptamz3V616/fn1p7fLLLw+Pje5TqTv76CnJR3Yze8zMdpnZhiGXLTez7Wa2rvi4qt5hAqhqJE/jn5B05TCXP+zuc4uPl9o7LADtlgy7u78maW8HxgKgRlXeoLvNzN4vnuZPLvshM1tmZmvNbG2F2wJQUath/5mkb0uaK6lf0kNlP+juK9x9nrvPa/G2ALRBS2F3953uPuDupyT9XNL89g4LQLu1FHYzmz7k2x9I2lD2swC6g6X6qGb2lKTvSpoqaaeku4vv50pySZ9KusXd+5M3ZhbeWKrfnJr3HZk1a1ZYv+aaa8L64sWLS2upedepedupudPR/utSvIZ5X19feGxK1Xnd0e/0iy++CI+dOHFiWE/ZvHlzaW3VqlXhsQ89VPrKVFJ399ndfdiTSpIn1bj7DcNc/GjlEQHoKE6XBTJB2IFMEHYgE4QdyARhBzKRbL219cbMPFp2uc4prnfffXdYX758eVjfs2dPaW3q1KmtDOlLqa2H9+6NpyZE9QsuuCA8NtUWTG3ZnHLs2LHSWmoaaervIdWKjaYtp7Zcfvnll8P6zTffHNab3NK5rPXGIzuQCcIOZIKwA5kg7EAmCDuQCcIOZIKwA5noeJ89qlfZmjg11TLV96yy7fKuXbvC+tatW8P6Aw88ENZXr14d1ufNK18E6OGHHw6PTW3ZPHly6YpjkqRt27aF9eh3+sQTT4THfvLJJ2H92muvDevR1OOq02tffPHFsJ6aMl0n+uxA5gg7kAnCDmSCsAOZIOxAJgg7kAnCDmSio332UaNGeTQ/+vjx4+Hx55xzTmlt9+7d4bGpPntq7nTUL05tB71p06awPmXKlLCeWrY4Wu75/PPPD49NzWdPLe+9b9++sH7jjTeW1l544YXw2JTUOgLRctGLFi0Kj02tMZC6X1LLf9eJPjuQOcIOZIKwA5kg7EAmCDuQCcIOZIKwA5noqvnsVaT6nitXrgzr119/fcvXf/jw4fDYcePGhfXUtsipef4DAwOltdS672+++WZYf/LJJ8P6unXrwvobb7xRWkudX5Dq4ad+59F5G/Pnzw+Pffvtt8P6448/HtZT68rXqeU+u5mdZ2a/NbONZvaBmf2kuHyKmb1iZpuLz/EqBwAaNZKn8Scl/Y27XyzpzyX92MwulnSXpFfdfbakV4vvAXSpZNjdvd/d3yu+PiDpQ0kzJC2RdPq58UpJS2saI4A2iF/0fIWZzZL0HUlvS5rm7v1FaYekaSXHLJO0rMIYAbTBiN+NN7M+SWsk3e7u+4fWfPBdvmHffHP3Fe4+z93LV0UEULsRhd3MztBg0H/h7s8UF+80s+lFfbqkeIlVAI1Ktt5scP7mSkl73f32IZc/IOkzd7/PzO6SNMXd/zZxXeGNnXvuueFYduzYEdYj0fa9kjRz5sywfu+995bWZsyYER6b2nI5tXVxtF20JN1///2ltY0bN4bHpqa4prZFTklNW46k2oYnTpwI69HU49Tf/YQJE8J61SnTdSprvY3kNftfSPorSevNbF1x2U8l3Sfpl2b2I0lbJcWNagCNSobd3f9LUtl/kd9r73AA1IXTZYFMEHYgE4QdyARhBzJB2IFMdHSKa09Pj0d93dRU0aj3uX///tKaJPX19YX1VN806vlW6fdK6Z5v6hyBqJed6uEfO3YsrFcV/b5TyzWnpgan/l6q/M5Sqo6tTiwlDWSOsAOZIOxAJgg7kAnCDmSCsAOZIOxAJrpqKenUHOKol55aVrjqvOzp06eX1vr7+0trI9Hb2xvWU1s213ndqWWsDx06FNarzClPGTUqfqyqMqe86fMTqqDPDmSOsAOZIOxAJgg7kAnCDmSCsAOZIOxAJrqqzw6gOvrsQOYIO5AJwg5kgrADmSDsQCYIO5AJwg5kIhl2MzvPzH5rZhvN7AMz+0lx+XIz225m64qPq+ofLoBWJU+qMbPpkqa7+3tmdpakdyUt1eB+7Afd/cER3xgn1QC1KzupZiT7s/dL6i++PmBmH0qa0d7hAajbH/Sa3cxmSfqOpLeLi24zs/fN7DEzm1xyzDIzW2tma6sNFUAVIz433sz6JP2npHvd/RkzmyZpjySX9A8afKp/c+I6eBoP1KzsafyIwm5mZ0h6UdKv3f2fhqnPkvSiu/9J4noIO1CzlifC2ODyoI9K+nBo0Is37k77gaQNVQcJoD4jeTd+gaTXJa2XdHpt3p9KukHSXA0+jf9U0i3Fm3nRdfHIDtSs0tP4diHsQP2Yzw5kjrADmSDsQCYIO5AJwg5kgrADmSDsQCYIO5AJwg5kgrADmSDsQCYIO5AJwg5kgrADmUguONlmeyRtHfL91OKybtStY+vWcUmMrVXtHNsFZYWOzmf/2o2brXX3eY0NINCtY+vWcUmMrVWdGhtP44FMEHYgE02HfUXDtx/p1rF167gkxtaqjoyt0dfsADqn6Ud2AB1C2IFMNBJ2M7vSzP7XzD4ys7uaGEMZM/vUzNYX21A3uj9dsYfeLjPbMOSyKWb2ipltLj4Pu8deQ2Prim28g23GG73vmt7+vOOv2c2sR9ImSX8paZukdyTd4O4bOzqQEmb2qaR57t74CRhmtlDSQUmrTm+tZWb/KGmvu99X/Ec52d3/rkvGtlx/4DbeNY2tbJvxv1aD9107tz9vRROP7PMlfeTuW9z9uKSnJS1pYBxdz91fk7T3KxcvkbSy+HqlBv9YOq5kbF3B3fvd/b3i6wOSTm8z3uh9F4yrI5oI+wxJvxvy/TZ1137vLuk3ZvaumS1rejDDmDZkm60dkqY1OZhhJLfx7qSvbDPeNfddK9ufV8UbdF+3wN3/TNL3Jf24eLralXzwNVg39U5/JunbGtwDsF/SQ00OpthmfI2k2919/9Bak/fdMOPqyP3WRNi3SzpvyPczi8u6grtvLz7vkvSsBl92dJOdp3fQLT7vang8X3L3ne4+4O6nJP1cDd53xTbjayT9wt2fKS5u/L4bblydut+aCPs7kmab2bfM7ExJP5T0fAPj+BozG1+8cSIzGy/pCnXfVtTPS7qp+PomSb9qcCy/p1u28S7bZlwN33eNb3/u7h3/kHSVBt+R/1jS3zcxhpJxXSjpv4uPD5oem6SnNPi07oQG39v4kaSzJb0qabOk/5A0pYvG9m8a3Nr7fQ0Ga3pDY1ugwafo70taV3xc1fR9F4yrI/cbp8sCmeANOiAThB3IBGEHMkHYgUwQdiAThB3IBGEHMvF/rSIwqVQD1iIAAAAASUVORK5CYII=",
- "text/plain": [
- "<Figure size 432x288 with 1 Axes>"
- ]
- },
- "metadata": {
- "needs_background": "light"
- },
- "output_type": "display_data"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from pkgutil import get_data\n",
"import onnx.numpy_helper as nph\n",
@@ -1501,17 +893,9 @@
},
{
"cell_type": "code",
- "execution_count": 92,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Expected network input shape is [1, 784]\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"model = ModelWrapper(build_dir + \"/tfc_w1_a1_pynq_deploy.onnx\")\n",
"iname = model.graph.input[0].name\n",
@@ -1529,7 +913,7 @@
},
{
"cell_type": "code",
- "execution_count": 95,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -1542,20 +926,9 @@
},
{
"cell_type": "code",
- "execution_count": 96,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "array([[2.]], dtype=float32)"
- ]
- },
- "execution_count": 96,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"ret[oname]"
]
@@ -1587,22 +960,9 @@
},
{
"cell_type": "code",
- "execution_count": 75,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "[sudo] password for xilinx: Collecting git+https://github.com/fbcotter/dataset_loading.git@0.0.4\n",
- " Cloning https://github.com/fbcotter/dataset_loading.git (to 0.0.4) to /tmp/pip-hhwx4j3n-build\n",
- " Requirement already satisfied (use --upgrade to upgrade): dataset-loading==0.0.4 from git+https://github.com/fbcotter/dataset_loading.git@0.0.4 in /usr/local/lib/python3.6/dist-packages\n",
- "Requirement already satisfied: Pillow in /usr/lib/python3/dist-packages (from dataset-loading==0.0.4)\n",
- "Requirement already satisfied: scipy in /usr/lib/python3/dist-packages (from dataset-loading==0.0.4)\n",
- "Connection to 192.168.2.99 closed.\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ssh {options} -t {username}@{ip} -p {port} 'echo {password} | sudo -S pip3 install git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading'"
]
@@ -1620,36 +980,9 @@
},
{
"cell_type": "code",
- "execution_count": 108,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "[sudo] password for xilinx: Looking for Train Imgs\n",
- "Tar File found in data_dir. Not Downloading again\n",
- "Looking for Train Labels\n",
- "Tar File found in data_dir. Not Downloading again\n",
- "Looking for Test Imgs\n",
- "Tar File found in data_dir. Not Downloading again\n",
- "Looking for Test Labels\n",
- "Tar File found in data_dir. Not Downloading again\n",
- "batch 0 / 10 : total OK 913 NOK 87\n",
- "batch 1 / 10 : total OK 1800 NOK 200\n",
- "batch 2 / 10 : total OK 2714 NOK 286\n",
- "batch 3 / 10 : total OK 3619 NOK 381\n",
- "batch 4 / 10 : total OK 4535 NOK 465\n",
- "batch 5 / 10 : total OK 5488 NOK 512\n",
- "batch 6 / 10 : total OK 6438 NOK 562\n",
- "batch 7 / 10 : total OK 7399 NOK 601\n",
- "batch 8 / 10 : total OK 8371 NOK 629\n",
- "batch 9 / 10 : total OK 9296 NOK 704\n",
- "Final accuracy: 92.960000\n",
- "Connection to 192.168.2.99 closed.\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ssh {options} -t {username}@{ip} -p {port} 'cd {target_dir_pynq}; echo {password} | sudo -S python3.6 validate.py --dataset mnist --batchsize 1000'"
]
@@ -1672,23 +1005,9 @@
},
{
"cell_type": "code",
- "execution_count": 104,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Network metrics:\n",
- "runtime[ms]: 10.43391227722168\n",
- "throughput[images/s]: 958413.2714850444\n",
- "DRAM_in_bandwidth[Mb/s]: 751.3960048442748\n",
- "DRAM_out_bandwidth[Mb/s]: 0.9584132714850445\n",
- "fclk[mhz]: 100.0\n",
- "N: 10000\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from finn.core.throughput_test import throughput_test_remote\n",
"\n",
@@ -1708,17 +1027,9 @@
},
{
"cell_type": "code",
- "execution_count": 105,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "We reach approximately 61% of the ideal performance.\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"II = 64\n",
"# frequency in MHz\n",
diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb
index 205202887..dbb98bc30 100644
--- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb
+++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb
@@ -28,7 +28,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -48,30 +48,9 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "<ipython-input-2-ddb8addf4232>:10: UserWarning: The given NumPy array is not writeable, and PyTorch does not support non-writeable tensors. This means you can write to the underlying (supposedly non-writeable) NumPy array using the tensor. You may want to copy the array to protect its data or make it writeable before converting it to a tensor. This type of warning will be suppressed for the rest of this program. (Triggered internally at /opt/conda/conda-bld/pytorch_1607370172916/work/torch/csrc/utils/tensor_numpy.cpp:141.)\n",
- " input_brevitas = torch.from_numpy(nph.to_array(input_tensor)).float()\n"
- ]
- },
- {
- "data": {
- "text/plain": [
- "array([[-1.4090618, -1.3267527, 0.9779036, -1.2444434, -1.4090618,\n",
- " -1.6559892, -1.3267527, -1.4913709, -1.3267527, -1.6559892]],\n",
- " dtype=float32)"
- ]
- },
- "execution_count": 2,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"from pkgutil import get_data\n",
"import onnx\n",
@@ -100,42 +79,9 @@
},
{
"cell_type": "code",
- "execution_count": 3,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "def xnorpopcountmatmul(inp0, inp1):\n",
- " \"\"\"Simulates XNOR-popcount matrix multiplication as a regular bipolar\n",
- " matrix multiplication followed by some post processing.\"\"\"\n",
- " # extract the operand shapes\n",
- " # (M, K0) = inp0.shape\n",
- " # (K1, N) = inp1.shape\n",
- " K0 = inp0.shape[-1]\n",
- " K1 = inp1.shape[0]\n",
- " # make sure shapes are compatible with matmul\n",
- " assert K0 == K1, \"Matrix shapes are not compatible with matmul.\"\n",
- " K = K0\n",
- " # convert binary inputs to bipolar\n",
- " inp0_bipolar = 2.0 * inp0 - 1.0\n",
- " inp1_bipolar = 2.0 * inp1 - 1.0\n",
- " # call regular numpy matrix multiplication\n",
- " out = np.matmul(inp0_bipolar, inp1_bipolar)\n",
- " # XNOR-popcount does not produce the regular dot product result --\n",
- " # it returns the number of +1s after XNOR. let P be the number of +1s\n",
- " # and N be the number of -1s. XNOR-popcount returns P, whereas the\n",
- " # regular dot product result from numpy is P-N, so we need to apply\n",
- " # some correction.\n",
- " # out = P-N\n",
- " # K = P+N\n",
- " # out + K = 2P, so P = (out + K)/2\n",
- " return (out + K) * 0.5\n",
- "\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.custom_op.general.xnorpopcount import xnorpopcountmatmul\n",
"showSrc(xnorpopcountmatmul)"
@@ -154,7 +100,7 @@
},
{
"cell_type": "code",
- "execution_count": 4,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -167,17 +113,9 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Results are the same!\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"import finn.core.onnx_exec as oxe\n",
"output_dict = oxe.execute_onnx(model_for_sim, input_dict, return_full_exec_context=False)\n",
@@ -209,7 +147,7 @@
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -227,7 +165,7 @@
},
{
"cell_type": "code",
- "execution_count": 7,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -249,38 +187,9 @@
},
{
"cell_type": "code",
- "execution_count": 8,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving '/scratch/users/mirzam/finn/tfc_w1_a1_for_cppsim.onnx' at http://0.0.0.0:5905\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:5905/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f91261099a0>"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"model_for_cppsim.save(build_dir+\"/tfc_w1_a1_for_cppsim.onnx\")\n",
"showInNetron(build_dir+\"/tfc_w1_a1_for_cppsim.onnx\")"
@@ -299,19 +208,9 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "compile.sh\t\t\t memblock_synth_0.dat weights.npy\r\n",
- "execute_MatrixVectorActivation.cpp node_model\r\n",
- "memblock_sim_0.dat\t\t thresh.h\r\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.custom_op.registry import getCustomOp\n",
"\n",
@@ -337,7 +236,7 @@
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -358,17 +257,9 @@
},
{
"cell_type": "code",
- "execution_count": 11,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Results are the same!\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"parent_model = ModelWrapper(build_dir+\"/tfc_w1_a1_dataflow_parent.onnx\")\n",
"sdp_node = parent_model.graph.node[1]\n",
@@ -414,1919 +305,9 @@
},
{
"cell_type": "code",
- "execution_count": 12,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0.v:73: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0.v:74: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:73: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:74: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:236: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:257: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'ap_sig_allocacmp_block_1' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0.v:221: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:584: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:585: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:586: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:828: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:852: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1575: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_739_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1577: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_771_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1579: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_915_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1581: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_931_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1583: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_947_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1585: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_963_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1587: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_979_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1589: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_1011_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1591: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_1155_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1593: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_1171_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1595: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_403_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1597: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_1187_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1599: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_1203_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1601: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_1219_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1603: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_1251_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1605: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_1395_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1607: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_1411_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1609: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_1427_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1611: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_1443_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1613: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_1459_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1615: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_1491_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1617: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_427_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1619: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_1635_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1621: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_1651_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1623: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_1667_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1625: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_1683_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1627: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_1699_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1629: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_1731_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1631: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_1875_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1633: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_1891_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1635: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_1907_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1637: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_1923_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1639: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_451_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1641: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_1939_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1643: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_1971_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1645: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_2115_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1647: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_2131_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1649: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_2147_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1651: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_2163_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1653: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_2179_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1655: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_2211_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1657: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_129_fu_2355_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1659: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_131_fu_2371_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1661: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_475_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1663: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_133_fu_2387_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1665: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_135_fu_2403_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1667: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_137_fu_2419_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1669: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_141_fu_2451_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1671: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_145_fu_2595_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1673: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_147_fu_2611_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1675: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_149_fu_2627_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1677: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_151_fu_2643_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1679: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_153_fu_2659_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1681: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_157_fu_2691_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1683: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_523_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1685: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_675_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1687: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_691_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1689: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_707_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1691: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_723_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1693: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_379_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1695: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_13_fu_829_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1697: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_reg_3215' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1699: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_995_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1701: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_1027_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1703: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_fu_1037_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1705: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_fu_1053_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1707: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_fu_1069_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1709: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_reg_3225' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1711: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_1235_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1713: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_1267_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1715: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_547_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1717: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_fu_1277_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1719: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_fu_1293_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1721: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_29_fu_1309_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1723: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_reg_3235' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1725: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_1475_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1727: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_1507_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1729: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_fu_1517_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1731: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_35_fu_1533_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1733: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_37_fu_1549_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1735: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_reg_3245' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1737: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_1_fu_557_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1739: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_1715_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1741: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_1747_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1743: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_fu_1757_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1745: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_fu_1773_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1747: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_fu_1789_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1749: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_reg_3255' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1751: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_1955_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1753: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_1987_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1755: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_fu_1997_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1757: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_51_fu_2013_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1759: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_fu_573_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1761: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_53_fu_2029_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1763: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_54_reg_3265' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1765: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_2195_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1767: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_2227_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1769: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_fu_2237_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1771: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_59_fu_2253_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1773: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_fu_2269_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1775: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_62_reg_3275' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1777: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_139_fu_2435_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1779: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_143_fu_2467_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1781: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_5_fu_589_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1783: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_65_fu_2477_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1785: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_67_fu_2493_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1787: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_69_fu_2509_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1789: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_70_reg_3285' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1791: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_155_fu_2675_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1793: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_159_fu_2707_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1795: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_73_fu_2717_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1797: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_75_fu_2733_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1799: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_77_fu_2749_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1801: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_78_reg_3295' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1803: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_reg_3205' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1805: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_755_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1807: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_787_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1809: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_fu_797_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1811: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_11_fu_813_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1813: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_499_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0.v:68: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0.v:69: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:440: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:441: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:442: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:443: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1715: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1739: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1763: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1904: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'nf_1_fu_346' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1910: Operator ASSIGNW expects 56 bits on the Assign RHS, but Assign RHS's VARREF 'p_Result_s_fu_2138_p50' generates 49 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1914: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1916: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1918: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1920: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1922: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1924: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1926: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1928: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1930: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1932: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1934: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1936: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1938: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1940: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1942: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1944: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1946: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1948: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1950: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1952: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1954: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1956: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1958: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1960: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1962: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1964: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1966: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1968: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1970: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1972: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1974: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1976: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1978: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1980: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1982: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1984: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1986: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1988: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1990: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1992: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1994: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1996: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1998: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2000: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2002: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2004: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2006: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2008: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2010: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0.v:186: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:587: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:588: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:589: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:590: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1146: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1170: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1194: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1357: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1397: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'nf_1_load_reg_3263' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1405: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1407: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1409: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1411: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1413: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1415: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1417: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1419: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_954_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_1082_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_1098_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_1114_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_1130_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_1146_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_1162_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_1274_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_1290_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_1306_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_1322_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_1338_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_1354_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_1466_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_1482_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_1498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_1514_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_1530_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_1546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_1658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_1674_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_1690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_1706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_1722_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_1738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_1850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_1866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_1882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_1898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_1914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_1930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_2042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_2058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_2074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_2090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_2106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_2122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_770_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_890_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_906_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_938_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1951: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_1_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1953: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_2_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1955: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_3_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1957: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_4_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1959: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_5_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1961: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_6_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1963: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_7_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1965: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_0_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1967: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_13_reg_3164' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1969: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_fu_2409_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1971: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_2437_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_1178_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1975: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_reg_3169' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1977: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_reg_3174' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1979: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_reg_3179' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1981: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_fu_2468_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1983: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_2496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_1370_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_794_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1989: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_reg_3184' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1991: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_reg_3189' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1993: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_29_reg_3194' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1995: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_fu_2527_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1997: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_2555_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_1562_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2001: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_reg_3199' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2003: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_35_reg_3204' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2005: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_37_reg_3209' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2007: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_fu_2586_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2009: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_1_reg_3139' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2011: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_2614_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_1754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2015: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_reg_3214' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2017: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_reg_3219' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2019: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_reg_3224' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2021: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_fu_2645_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2023: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_2673_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_1946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2027: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_reg_3229' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2029: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_51_reg_3234' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2031: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_reg_3144' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2033: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_53_reg_3239' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2035: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_54_fu_2704_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2037: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_2732_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_2138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2041: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_reg_3244' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2043: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_59_reg_3249' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2045: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_reg_3254' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2047: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_62_fu_2763_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2049: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_5_reg_3149' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2051: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_fu_2350_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2053: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_2378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_986_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2057: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_reg_3154' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2059: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_11_reg_3159' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2061: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_2319_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:587: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:588: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:589: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:590: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1146: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1170: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1194: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1357: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1397: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'nf_1_load_reg_3263' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1405: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1407: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1409: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1411: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1413: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1415: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1417: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1419: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_954_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_1082_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_1098_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_1114_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_1130_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_1146_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_1162_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_1274_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_1290_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_1306_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_1322_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_1338_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_1354_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_1466_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_1482_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_1498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_1514_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_1530_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_1546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_1658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_1674_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_1690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_1706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_1722_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_1738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_1850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_1866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_1882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_1898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_1914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_1930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_2042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_2058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_2074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_2090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_2106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_2122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_770_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_890_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_906_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_938_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1951: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_1_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1953: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_2_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1955: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_3_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1957: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_4_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1959: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_5_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1961: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_6_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1963: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_7_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1965: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_0_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1967: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_13_reg_3164' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1969: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_fu_2409_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1971: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_2437_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_1178_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1975: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_reg_3169' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1977: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_reg_3174' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1979: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_reg_3179' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1981: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_fu_2468_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1983: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_2496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_1370_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_794_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1989: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_reg_3184' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1991: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_reg_3189' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1993: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_29_reg_3194' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1995: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_fu_2527_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1997: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_2555_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_1562_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2001: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_reg_3199' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2003: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_35_reg_3204' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2005: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_37_reg_3209' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2007: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_fu_2586_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2009: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_1_reg_3139' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2011: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_2614_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_1754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2015: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_reg_3214' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2017: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_reg_3219' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2019: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_reg_3224' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2021: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_fu_2645_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2023: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_2673_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_1946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2027: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_reg_3229' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2029: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_51_reg_3234' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2031: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_reg_3144' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2033: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_53_reg_3239' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2035: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_54_fu_2704_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2037: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_2732_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_2138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2041: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_reg_3244' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2043: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_59_reg_3249' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2045: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_reg_3254' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2047: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_62_fu_2763_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2049: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_5_reg_3149' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2051: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_fu_2350_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2053: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_2378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_986_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2057: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_reg_3154' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2059: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_11_reg_3159' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2061: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_2319_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5050: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5051: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5052: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5053: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5054: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6186: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6210: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6234: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6258: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:7867: Operator ASSIGNW expects 49 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12803: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_205_fu_5758_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12805: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_207_fu_5774_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12807: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_209_fu_5790_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12809: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_211_fu_5806_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12811: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_213_fu_5822_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12813: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_215_fu_5838_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12815: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_217_fu_5854_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12817: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_219_fu_5870_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12819: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_221_fu_5886_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12821: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_223_fu_5902_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12823: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_2826_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12825: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_225_fu_5918_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12827: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_227_fu_5934_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12829: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_229_fu_5950_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12831: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_231_fu_5966_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12833: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_233_fu_5982_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12835: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_235_fu_5998_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12837: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_237_fu_6014_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12839: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_239_fu_6030_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12841: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_241_fu_6046_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12843: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_243_fu_6062_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12845: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_2850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12847: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_245_fu_6078_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12849: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_247_fu_6094_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12851: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_249_fu_6110_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12853: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_251_fu_6126_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_253_fu_6142_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_255_fu_6158_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_257_fu_6174_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_259_fu_6190_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_261_fu_6206_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_263_fu_6222_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_2874_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_265_fu_6238_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_267_fu_6254_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_269_fu_6270_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_271_fu_6286_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_273_fu_6302_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_275_fu_6318_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_277_fu_6334_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_279_fu_6350_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_281_fu_6366_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_283_fu_6382_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_2898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_285_fu_6398_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_287_fu_6414_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_289_fu_6430_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_291_fu_6446_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_295_fu_7056_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_297_fu_7072_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_299_fu_7088_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_301_fu_7104_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_303_fu_7120_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_305_fu_7136_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_2922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_307_fu_7152_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_309_fu_7168_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_311_fu_7184_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_313_fu_7200_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_315_fu_7216_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_317_fu_7232_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_319_fu_7248_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_321_fu_7264_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_323_fu_7280_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_325_fu_7296_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_2946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_327_fu_7312_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_329_fu_7328_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_331_fu_7344_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_333_fu_7360_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_335_fu_7376_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_337_fu_7392_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_339_fu_7408_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_341_fu_7424_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12951: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_343_fu_7440_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12953: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_345_fu_7456_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12955: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_2970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12957: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_347_fu_7472_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12959: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_349_fu_7488_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12961: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_351_fu_7504_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12963: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_353_fu_7520_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12965: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_355_fu_7536_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12967: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_357_fu_7552_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12969: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_359_fu_7568_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12971: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_361_fu_7584_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_363_fu_7600_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12975: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_365_fu_7616_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12977: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_2994_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12979: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_367_fu_7632_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12981: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_369_fu_7648_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12983: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_371_fu_7664_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_373_fu_7680_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_375_fu_7696_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12989: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_377_fu_7712_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12991: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_379_fu_7728_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12993: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_381_fu_7744_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12995: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_383_fu_7760_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12997: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_385_fu_7776_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_3018_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13001: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_387_fu_7792_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13003: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_389_fu_7808_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13005: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_393_fu_8418_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13007: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_395_fu_8434_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13009: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_397_fu_8450_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13011: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_399_fu_8466_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_401_fu_8482_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13015: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_403_fu_8498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13017: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_405_fu_8514_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13019: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_407_fu_8530_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13021: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_3042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13023: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_2610_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_409_fu_8546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13027: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_411_fu_8562_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13029: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_413_fu_8578_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13031: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_415_fu_8594_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13033: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_417_fu_8610_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13035: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_419_fu_8626_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13037: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_421_fu_8642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_423_fu_8658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13041: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_425_fu_8674_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13043: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_427_fu_8690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13045: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_3066_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13047: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_429_fu_8706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13049: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_431_fu_8722_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13051: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_433_fu_8738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13053: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_435_fu_8754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_437_fu_8770_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13057: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_439_fu_8786_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13059: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_441_fu_8802_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13061: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_443_fu_8818_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13063: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_445_fu_8834_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13065: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_447_fu_8850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13067: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_3090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13069: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_449_fu_8866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13071: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_451_fu_8882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13073: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_453_fu_8898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13075: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_455_fu_8914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13077: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_457_fu_8930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13079: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_459_fu_8946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13081: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_461_fu_8962_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13083: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_463_fu_8978_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13085: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_465_fu_8994_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13087: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_467_fu_9010_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13089: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_3114_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13091: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_469_fu_9026_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13093: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_471_fu_9042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13095: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_473_fu_9058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13097: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_475_fu_9074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13099: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_477_fu_9090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13101: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_479_fu_9106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13103: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_481_fu_9122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13105: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_483_fu_9138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13107: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_485_fu_9154_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13109: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_487_fu_9170_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13111: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_3138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13113: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_491_fu_9780_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13115: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_493_fu_9796_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13117: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_495_fu_9812_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13119: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_497_fu_9828_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13121: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_499_fu_9844_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13123: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_501_fu_9860_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13125: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_503_fu_9876_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13127: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_505_fu_9892_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13129: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_507_fu_9908_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13131: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_509_fu_9924_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13133: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_3162_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13135: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_511_fu_9940_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13137: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_513_fu_9956_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13139: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_515_fu_9972_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13141: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_517_fu_9988_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13143: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_519_fu_10004_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13145: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_521_fu_10020_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13147: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_523_fu_10036_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13149: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_525_fu_10052_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13151: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_527_fu_10068_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13153: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_529_fu_10084_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13155: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_3186_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13157: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_531_fu_10100_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13159: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_533_fu_10116_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13161: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_535_fu_10132_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13163: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_537_fu_10148_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13165: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_539_fu_10164_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13167: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_541_fu_10180_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13169: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_543_fu_10196_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13171: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_545_fu_10212_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13173: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_547_fu_10228_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13175: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_549_fu_10244_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13177: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_3210_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13179: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_551_fu_10260_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13181: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_553_fu_10276_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13183: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_555_fu_10292_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13185: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_557_fu_10308_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13187: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_559_fu_10324_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13189: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_561_fu_10340_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13191: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_563_fu_10356_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13193: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_565_fu_10372_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13195: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_567_fu_10388_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13197: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_569_fu_10404_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13199: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_3234_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13201: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_571_fu_10420_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13203: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_573_fu_10436_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13205: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_575_fu_10452_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13207: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_577_fu_10468_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13209: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_579_fu_10484_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13211: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_581_fu_10500_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13213: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_583_fu_10516_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13215: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_585_fu_10532_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13217: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_589_fu_11142_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13219: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_591_fu_11158_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13221: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_3258_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13223: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_593_fu_11174_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13225: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_595_fu_11190_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13227: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_597_fu_11206_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13229: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_599_fu_11222_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13231: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_601_fu_11238_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13233: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_603_fu_11254_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13235: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_605_fu_11270_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13237: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_607_fu_11286_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13239: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_609_fu_11302_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13241: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_611_fu_11318_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13243: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_3282_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13245: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_2634_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13247: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_613_fu_11334_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13249: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_615_fu_11350_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13251: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_617_fu_11366_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13253: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_619_fu_11382_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13255: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_621_fu_11398_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13257: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_623_fu_11414_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13259: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_625_fu_11430_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13261: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_627_fu_11446_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13263: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_629_fu_11462_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13265: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_631_fu_11478_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13267: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_3306_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13269: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_633_fu_11494_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13271: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_635_fu_11510_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13273: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_637_fu_11526_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13275: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_639_fu_11542_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13277: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_641_fu_11558_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13279: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_643_fu_11574_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13281: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_645_fu_11590_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13283: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_647_fu_11606_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13285: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_649_fu_11622_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13287: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_651_fu_11638_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13289: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_3330_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13291: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_653_fu_11654_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13293: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_655_fu_11670_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13295: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_657_fu_11686_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13297: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_659_fu_11702_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13299: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_661_fu_11718_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13301: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_663_fu_11734_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13303: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_665_fu_11750_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13305: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_667_fu_11766_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13307: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_669_fu_11782_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13309: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_671_fu_11798_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13311: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_3354_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13313: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_673_fu_11814_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13315: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_675_fu_11830_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13317: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_677_fu_11846_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13319: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_679_fu_11862_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13321: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_681_fu_11878_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13323: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_683_fu_11894_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13325: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_687_fu_12504_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13327: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_689_fu_12520_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13329: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_691_fu_12536_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13331: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_693_fu_12552_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13333: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_3378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13335: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_695_fu_12568_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13337: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_697_fu_12584_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13339: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_699_fu_12600_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13341: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_701_fu_12616_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13343: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_703_fu_12632_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13345: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_705_fu_12648_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13347: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_707_fu_12664_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13349: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_709_fu_12680_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13351: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_711_fu_12696_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13353: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_713_fu_12712_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13355: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_3402_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13357: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_715_fu_12728_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13359: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_717_fu_12744_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13361: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_719_fu_12760_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13363: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_721_fu_12776_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13365: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_723_fu_12792_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13367: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_725_fu_12808_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13369: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_727_fu_12824_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13371: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_729_fu_12840_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13373: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_731_fu_12856_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13375: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_733_fu_12872_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13377: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_3426_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13379: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_735_fu_12888_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13381: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_737_fu_12904_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13383: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_739_fu_12920_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13385: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_741_fu_12936_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13387: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_743_fu_12952_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13389: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_745_fu_12968_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13391: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_747_fu_12984_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13393: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_749_fu_13000_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13395: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_751_fu_13016_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13397: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_753_fu_13032_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13399: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_3450_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13401: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_755_fu_13048_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13403: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_757_fu_13064_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13405: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_759_fu_13080_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13407: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_761_fu_13096_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13409: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_763_fu_13112_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13411: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_765_fu_13128_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13413: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_767_fu_13144_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13415: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_769_fu_13160_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13417: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_771_fu_13176_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13419: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_773_fu_13192_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13421: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_3474_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13423: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_775_fu_13208_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13425: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_777_fu_13224_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13427: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_779_fu_13240_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13429: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_781_fu_13256_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13431: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_785_fu_13866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13433: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_787_fu_13882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13435: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_789_fu_13898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13437: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_791_fu_13914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13439: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_793_fu_13930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13441: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_795_fu_13946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13443: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_3498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13445: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_797_fu_13962_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13447: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_799_fu_13978_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13449: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_801_fu_13994_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13451: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_803_fu_14010_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13453: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_805_fu_14026_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13455: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_807_fu_14042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13457: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_809_fu_14058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13459: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_811_fu_14074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13461: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_813_fu_14090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13463: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_815_fu_14106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13465: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_3522_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13467: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_2658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13469: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_817_fu_14122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13471: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_819_fu_14138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13473: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_821_fu_14154_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13475: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_823_fu_14170_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13477: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_825_fu_14186_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13479: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_827_fu_14202_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13481: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_829_fu_14218_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13483: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_831_fu_14234_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13485: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_833_fu_14250_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13487: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_835_fu_14266_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13489: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_3546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13491: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_837_fu_14282_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13493: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_839_fu_14298_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13495: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_841_fu_14314_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13497: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_843_fu_14330_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13499: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_845_fu_14346_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13501: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_847_fu_14362_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13503: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_849_fu_14378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13505: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_851_fu_14394_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13507: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_853_fu_14410_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13509: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_855_fu_14426_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13511: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_3570_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13513: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_857_fu_14442_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13515: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_859_fu_14458_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13517: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_861_fu_14474_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13519: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_863_fu_14490_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13521: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_865_fu_14506_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13523: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_867_fu_14522_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13525: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_869_fu_14538_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13527: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_871_fu_14554_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13529: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_873_fu_14570_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13531: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_875_fu_14586_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13533: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_3594_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13535: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_877_fu_14602_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13537: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_879_fu_14618_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13539: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_883_fu_15228_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13541: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_885_fu_15244_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13543: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_887_fu_15260_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13545: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_889_fu_15276_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13547: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_891_fu_15292_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13549: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_893_fu_15308_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13551: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_895_fu_15324_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13553: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_897_fu_15340_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13555: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_3618_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13557: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_899_fu_15356_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13559: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_901_fu_15372_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13561: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_903_fu_15388_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13563: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_905_fu_15404_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13565: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_907_fu_15420_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13567: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_909_fu_15436_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13569: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_911_fu_15452_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13571: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_913_fu_15468_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13573: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_915_fu_15484_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13575: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_917_fu_15500_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13577: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_3642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13579: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_919_fu_15516_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13581: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_921_fu_15532_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13583: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_923_fu_15548_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13585: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_925_fu_15564_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13587: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_927_fu_15580_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13589: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_929_fu_15596_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13591: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_931_fu_15612_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13593: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_933_fu_15628_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13595: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_935_fu_15644_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13597: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_937_fu_15660_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13599: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_3666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13601: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_939_fu_15676_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13603: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_941_fu_15692_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13605: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_943_fu_15708_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13607: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_945_fu_15724_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13609: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_947_fu_15740_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13611: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_949_fu_15756_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13613: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_951_fu_15772_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13615: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_953_fu_15788_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13617: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_955_fu_15804_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13619: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_957_fu_15820_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13621: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_3690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13623: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_959_fu_15836_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13625: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_961_fu_15852_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13627: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_963_fu_15868_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13629: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_965_fu_15884_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13631: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_967_fu_15900_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13633: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_969_fu_15916_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13635: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_971_fu_15932_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13637: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_973_fu_15948_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13639: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_975_fu_15964_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13641: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_977_fu_15980_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13643: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_3714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13645: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_981_fu_16590_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13647: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_983_fu_16606_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13649: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_985_fu_16622_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13651: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_987_fu_16638_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13653: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_989_fu_16654_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13655: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_991_fu_16670_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13657: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_993_fu_16686_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13659: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_995_fu_16702_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13661: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_997_fu_16718_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13663: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_999_fu_16734_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13665: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_4332_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13667: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1001_fu_16750_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13669: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1003_fu_16766_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13671: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1005_fu_16782_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13673: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1007_fu_16798_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13675: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1009_fu_16814_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13677: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1011_fu_16830_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13679: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1013_fu_16846_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13681: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1015_fu_16862_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13683: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1017_fu_16878_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13685: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1019_fu_16894_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13687: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_4348_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13689: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_2682_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13691: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1021_fu_16910_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13693: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1023_fu_16926_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13695: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1025_fu_16942_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13697: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1027_fu_16958_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13699: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1029_fu_16974_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13701: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1031_fu_16990_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13703: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1033_fu_17006_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13705: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1035_fu_17022_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13707: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1037_fu_17038_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13709: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1039_fu_17054_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13711: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_4364_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13713: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1041_fu_17070_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13715: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1043_fu_17086_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13717: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1045_fu_17102_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13719: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1047_fu_17118_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13721: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1049_fu_17134_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13723: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1051_fu_17150_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13725: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1053_fu_17166_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13727: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1055_fu_17182_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13729: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1057_fu_17198_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13731: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1059_fu_17214_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13733: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_4380_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13735: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1061_fu_17230_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13737: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1063_fu_17246_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13739: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1065_fu_17262_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13741: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1067_fu_17278_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13743: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1069_fu_17294_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13745: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1071_fu_17310_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13747: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1073_fu_17326_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13749: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1075_fu_17342_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13751: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1079_fu_17952_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13753: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1081_fu_17968_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13755: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_4396_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13757: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1083_fu_17984_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13759: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1085_fu_18000_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13761: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1087_fu_18016_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13763: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1089_fu_18032_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13765: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1091_fu_18048_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13767: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1093_fu_18064_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13769: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1095_fu_18080_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13771: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1097_fu_18096_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13773: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1099_fu_18112_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13775: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1101_fu_18128_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13777: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_4412_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13779: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1103_fu_18144_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13781: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1105_fu_18160_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13783: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1107_fu_18176_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13785: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1109_fu_18192_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13787: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1111_fu_18208_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13789: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1113_fu_18224_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13791: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1115_fu_18240_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13793: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1117_fu_18256_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13795: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1119_fu_18272_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13797: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1121_fu_18288_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13799: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_4428_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13801: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1123_fu_18304_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13803: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1125_fu_18320_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13805: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1127_fu_18336_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13807: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1129_fu_18352_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13809: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1131_fu_18368_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13811: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1133_fu_18384_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13813: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1135_fu_18400_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13815: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1137_fu_18416_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13817: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1139_fu_18432_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13819: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1141_fu_18448_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13821: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_4444_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13823: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1143_fu_18464_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13825: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1145_fu_18480_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13827: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1147_fu_18496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13829: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1149_fu_18512_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13831: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1151_fu_18528_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13833: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1153_fu_18544_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13835: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1155_fu_18560_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13837: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1157_fu_18576_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13839: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1159_fu_18592_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13841: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1161_fu_18608_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13843: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_4460_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13845: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1163_fu_18624_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13847: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1165_fu_18640_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13849: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1167_fu_18656_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13851: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1169_fu_18672_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13853: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1171_fu_18688_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1173_fu_18704_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1177_fu_19314_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1179_fu_19330_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1181_fu_19346_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1183_fu_19362_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_4476_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1185_fu_19378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1187_fu_19394_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1189_fu_19410_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1191_fu_19426_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1193_fu_19442_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1195_fu_19458_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1197_fu_19474_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1199_fu_19490_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1201_fu_19506_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1203_fu_19522_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_4492_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1205_fu_19538_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1207_fu_19554_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1209_fu_19570_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1211_fu_19586_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1213_fu_19602_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1215_fu_19618_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1217_fu_19634_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1219_fu_19650_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1221_fu_19666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1223_fu_19682_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_4508_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_2706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1225_fu_19698_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1227_fu_19714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1229_fu_19730_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1231_fu_19746_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1233_fu_19762_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1235_fu_19778_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1237_fu_19794_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1239_fu_19810_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1241_fu_19826_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1243_fu_19842_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_4524_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1245_fu_19858_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1247_fu_19874_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1249_fu_19890_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1251_fu_19906_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1253_fu_19922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1255_fu_19938_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1257_fu_19954_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1259_fu_19970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13951: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1261_fu_19986_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13953: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1263_fu_20002_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13955: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_4540_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13957: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1265_fu_20018_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13959: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1267_fu_20034_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13961: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1269_fu_20050_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13963: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1271_fu_20066_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13965: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1275_fu_20676_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13967: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1277_fu_20692_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13969: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1279_fu_20708_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13971: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1281_fu_20724_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1283_fu_20740_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13975: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1285_fu_20756_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13977: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_4556_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13979: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1287_fu_20772_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13981: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1289_fu_20788_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13983: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1291_fu_20804_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1293_fu_20820_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1295_fu_20836_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13989: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1297_fu_20852_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13991: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1299_fu_20868_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13993: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1301_fu_20884_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13995: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1303_fu_20900_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13997: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1305_fu_20916_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_129_fu_4572_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14001: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1307_fu_20932_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14003: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1309_fu_20948_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14005: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1311_fu_20964_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14007: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1313_fu_20980_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14009: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1315_fu_20996_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14011: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1317_fu_21012_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1319_fu_21028_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14015: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1321_fu_21044_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14017: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1323_fu_21060_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14019: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1325_fu_21076_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14021: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_131_fu_4588_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14023: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1327_fu_21092_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1329_fu_21108_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14027: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1331_fu_21124_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14029: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1333_fu_21140_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14031: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1335_fu_21156_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14033: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1337_fu_21172_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14035: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1339_fu_21188_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14037: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1341_fu_21204_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1343_fu_21220_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14041: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1345_fu_21236_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14043: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_133_fu_4604_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14045: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1347_fu_21252_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14047: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1349_fu_21268_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14049: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1351_fu_21284_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14051: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1353_fu_21300_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14053: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1355_fu_21316_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1357_fu_21332_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14057: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1359_fu_21348_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14059: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1361_fu_21364_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14061: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1363_fu_21380_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14063: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1365_fu_21396_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14065: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_135_fu_4620_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14067: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1367_fu_21412_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14069: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1369_fu_21428_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14071: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1373_fu_22038_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14073: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1375_fu_22054_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14075: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1377_fu_22070_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14077: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1379_fu_22086_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14079: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1381_fu_22102_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14081: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1383_fu_22118_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14083: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1385_fu_22134_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14085: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1387_fu_22150_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14087: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_137_fu_4636_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14089: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1389_fu_22166_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14091: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1391_fu_22182_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14093: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1393_fu_22198_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14095: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1395_fu_22214_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14097: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1397_fu_22230_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14099: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1399_fu_22246_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14101: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1401_fu_22262_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14103: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1403_fu_22278_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14105: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1405_fu_22294_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14107: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1407_fu_22310_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14109: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_139_fu_4652_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14111: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1409_fu_22326_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14113: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1411_fu_22342_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14115: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1413_fu_22358_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14117: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1415_fu_22374_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14119: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1417_fu_22390_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14121: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1419_fu_22406_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14123: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1421_fu_22422_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14125: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1423_fu_22438_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14127: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1425_fu_22454_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14129: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1427_fu_22470_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14131: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_141_fu_4668_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14133: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_2730_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14135: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1429_fu_22486_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14137: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1431_fu_22502_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14139: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1433_fu_22518_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14141: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1435_fu_22534_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14143: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1437_fu_22550_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14145: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1439_fu_22566_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14147: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1441_fu_22582_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14149: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1443_fu_22598_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14151: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1445_fu_22614_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14153: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1447_fu_22630_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14155: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_143_fu_4684_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14157: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1449_fu_22646_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14159: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1451_fu_22662_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14161: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1453_fu_22678_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14163: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1455_fu_22694_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14165: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1457_fu_22710_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14167: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1459_fu_22726_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14169: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1461_fu_22742_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14171: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1463_fu_22758_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14173: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1465_fu_22774_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14175: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1467_fu_22790_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14177: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_145_fu_4700_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14179: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1471_fu_23400_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14181: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1473_fu_23416_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14183: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1475_fu_23432_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14185: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1477_fu_23448_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14187: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1479_fu_23464_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14189: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1481_fu_23480_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14191: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1483_fu_23496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14193: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1485_fu_23512_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14195: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1487_fu_23528_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14197: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1489_fu_23544_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14199: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_147_fu_4716_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14201: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1491_fu_23560_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14203: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1493_fu_23576_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14205: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1495_fu_23592_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14207: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1497_fu_23608_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14209: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1499_fu_23624_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14211: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1501_fu_23640_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14213: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1503_fu_23656_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14215: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1505_fu_23672_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14217: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1507_fu_23688_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14219: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1509_fu_23704_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14221: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_149_fu_4732_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14223: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1511_fu_23720_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14225: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1513_fu_23736_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14227: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1515_fu_23752_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14229: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1517_fu_23768_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14231: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1519_fu_23784_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14233: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1521_fu_23800_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14235: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1523_fu_23816_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14237: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1525_fu_23832_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14239: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1527_fu_23848_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14241: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1529_fu_23864_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14243: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_151_fu_4748_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14245: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1531_fu_23880_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14247: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1533_fu_23896_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14249: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1535_fu_23912_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14251: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1537_fu_23928_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14253: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1539_fu_23944_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14255: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1541_fu_23960_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14257: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1543_fu_23976_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14259: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1545_fu_23992_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14261: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1547_fu_24008_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14263: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1549_fu_24024_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14265: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_153_fu_4764_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14267: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1551_fu_24040_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14269: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1553_fu_24056_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14271: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1555_fu_24072_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14273: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1557_fu_24088_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14275: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1559_fu_24104_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14277: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1561_fu_24120_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14279: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1563_fu_24136_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14281: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1565_fu_24152_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14283: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_155_fu_4780_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14285: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_157_fu_4796_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14287: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_159_fu_4812_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14289: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_161_fu_4828_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14291: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_2754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14293: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_163_fu_4844_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14295: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_165_fu_4860_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14297: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_167_fu_4876_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14299: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_169_fu_4892_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14301: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_171_fu_4908_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14303: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_173_fu_4924_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14305: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_175_fu_4940_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14307: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_177_fu_4956_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14309: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_179_fu_4972_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14311: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_181_fu_4988_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14313: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_2778_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14315: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_183_fu_5004_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14317: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_185_fu_5020_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14319: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_187_fu_5036_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14321: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_189_fu_5052_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14323: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_191_fu_5068_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14325: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_193_fu_5084_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14327: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_197_fu_5694_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14329: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_199_fu_5710_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14331: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_201_fu_5726_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14333: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_203_fu_5742_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14335: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_2802_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14337: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_2586_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14339: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_165_reg_28885' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14341: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_166_reg_28890' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14343: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_168_fu_24940_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14345: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_169_reg_30094' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14347: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_172_reg_28895' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14349: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_174_reg_28900' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14351: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_175_fu_24962_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14353: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_177_reg_28905' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14355: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_179_reg_28910' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14357: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_180_fu_24978_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14359: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_18_reg_28615' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14361: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_181_fu_24988_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14363: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_183_reg_28915' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14365: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_185_reg_28920' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14367: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_186_fu_25004_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14369: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_188_reg_28925' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14371: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_189_reg_28930' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14373: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_190_reg_28935' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14375: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_192_fu_25029_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14377: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_193_fu_25039_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14379: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_194_reg_30099' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14381: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_reg_28620' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14383: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_489_fu_9186_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14385: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_196_reg_28940_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14387: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_199_reg_28945_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14389: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_202_reg_28950' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14391: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_204_reg_28955' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14393: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_205_reg_30104' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14395: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_208_reg_28960' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14397: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_210_reg_28965' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14399: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_211_fu_25073_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14401: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_213_reg_28970' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14403: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_fu_24466_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14405: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_214_reg_28975' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14407: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_215_reg_28980' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14409: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_217_fu_25098_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14411: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_218_reg_30109' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14413: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_221_reg_28985' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14415: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_223_reg_28990' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14417: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_224_fu_25120_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14419: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_226_reg_28995' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14421: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_228_reg_29000' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14423: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_229_fu_25136_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14425: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_reg_30049' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14427: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_230_fu_25146_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14429: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_232_reg_29005' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14431: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_234_reg_29010' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14433: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_235_fu_25162_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14435: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_237_reg_29015' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14437: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_238_reg_29020' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14439: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_239_reg_29025' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14441: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_241_fu_25187_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14443: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_242_fu_25197_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14445: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_243_reg_30114' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14447: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_reg_28625' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14449: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_587_fu_10548_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14451: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_245_reg_29030_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14453: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_248_reg_29035_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14455: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_251_reg_29040' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14457: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_253_reg_29045' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14459: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_254_reg_30119' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14461: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_257_reg_29050' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14463: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_259_reg_29055' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14465: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_260_fu_25231_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14467: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_262_reg_29060' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14469: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_reg_28630' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14471: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_263_reg_29065' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14473: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_264_reg_29070' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14475: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_266_fu_25256_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14477: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_267_reg_30124' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14479: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_270_reg_29075' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14481: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_272_reg_29080' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14483: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_273_fu_25278_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14485: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_275_reg_29085' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14487: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_277_reg_29090' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14489: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_278_fu_25294_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14491: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_28_fu_24488_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14493: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_279_fu_25304_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14495: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_281_reg_29095' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14497: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_283_reg_29100' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14499: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_284_fu_25320_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14501: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_286_reg_29105' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14503: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_287_reg_29110' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14505: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_288_reg_29115' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14507: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_290_fu_25345_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14509: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_291_fu_25355_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14511: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_292_reg_30129' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14513: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_reg_28635' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14515: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_685_fu_11910_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14517: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_294_reg_29120_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14519: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_297_reg_29125_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14521: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_300_reg_29130' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14523: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_302_reg_29135' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14525: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_303_reg_30134' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14527: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_306_reg_29140' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14529: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_308_reg_29145' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14531: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_309_fu_25389_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14533: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_311_reg_29150' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14535: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_32_reg_28640' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14537: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_312_reg_29155' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14539: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_313_reg_29160' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14541: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_315_fu_25414_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14543: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_316_reg_30139' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14545: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_319_reg_29165' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14547: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_321_reg_29170' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14549: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_322_fu_25436_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14551: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_324_reg_29175' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14553: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_326_reg_29180' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14555: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_327_fu_25452_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14557: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_fu_24504_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14559: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_reg_28580_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14561: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_328_fu_25462_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14563: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_330_reg_29185' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14565: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_332_reg_29190' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14567: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_333_fu_25478_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14569: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_335_reg_29195' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14571: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_336_reg_29200' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14573: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_337_reg_29205' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14575: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_339_fu_25503_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14577: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_340_fu_25513_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14579: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_341_reg_30144' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14581: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_34_fu_24514_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14583: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_783_fu_13272_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14585: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_343_reg_29210_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14587: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_346_reg_29215_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14589: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_349_reg_29220' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14591: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_351_reg_29225' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14593: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_352_reg_30149' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14595: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_355_reg_29230' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14597: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_357_reg_29235' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14599: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_358_fu_25547_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14601: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_360_reg_29240' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14603: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_36_reg_28645' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14605: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_361_reg_29245' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14607: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_362_reg_29250' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14609: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_364_fu_25572_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14611: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_365_reg_30154' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14613: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_368_reg_29255' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14615: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_370_reg_29260' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14617: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_371_fu_25594_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14619: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_373_reg_29265' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14621: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_375_reg_29270' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14623: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_376_fu_25610_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14625: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_reg_28650' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14627: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_377_fu_25620_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14629: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_379_reg_29275' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14631: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_381_reg_29280' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14633: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_382_fu_25636_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14635: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_384_reg_29285' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14637: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_385_reg_29290' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14639: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_386_reg_29295' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14641: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_388_fu_25661_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14643: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_389_fu_25671_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14645: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_390_reg_30159' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14647: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_39_fu_24530_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14649: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_881_fu_14634_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14651: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_392_reg_29300_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14653: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_395_reg_29305_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14655: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_398_reg_29310' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14657: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_400_reg_29315' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14659: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_401_reg_30164' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14661: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_404_reg_29320' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14663: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_406_reg_29325' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14665: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_407_fu_25705_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14667: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_409_reg_29330' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14669: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_reg_28655' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14671: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_410_reg_29335' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14673: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_411_reg_29340' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14675: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_413_fu_25730_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14677: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_414_reg_30169' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14679: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_417_reg_29345' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14681: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_419_reg_29350' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14683: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_420_fu_25752_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14685: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_422_reg_29355' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14687: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_424_reg_29360' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14689: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_425_fu_25768_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14691: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_42_reg_28660' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14693: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_426_fu_25778_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14695: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_428_reg_29365' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14697: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_430_reg_29370' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14699: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_431_fu_25794_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14701: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_433_reg_29375' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14703: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_434_reg_29380' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14705: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_435_reg_29385' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14707: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_437_fu_25819_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14709: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_438_fu_25829_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14711: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_439_reg_30174' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14713: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_reg_28665' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14715: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_979_fu_15996_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14717: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_441_reg_29390_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14719: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_444_reg_29395_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14721: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_447_reg_29400' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14723: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_449_reg_29405' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14725: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_450_reg_30179' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14727: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_453_reg_29410' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14729: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_455_reg_29415' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14731: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_456_fu_25863_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14733: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_458_reg_29420' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14735: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_fu_24555_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14737: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_459_reg_29425' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14739: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_460_reg_29430' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14741: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_462_fu_25888_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14743: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_463_reg_30184' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14745: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_466_reg_29435' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14747: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_468_reg_29440' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14749: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_469_fu_25910_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14751: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_471_reg_29445' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14753: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_473_reg_29450' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14755: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_474_fu_25926_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14757: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_fu_24565_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14759: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_475_fu_25936_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14761: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_477_reg_29455' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14763: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_479_reg_29460' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14765: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_480_fu_25952_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14767: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_482_reg_29465' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14769: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_483_reg_29470' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14771: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_484_reg_29475' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14773: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_486_fu_25977_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14775: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_487_fu_25987_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14777: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_488_reg_30189' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14779: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_47_reg_30054' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14781: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_reg_28585_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14783: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1077_fu_17358_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14785: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_490_reg_29480_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14787: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_493_reg_29485_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14789: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_496_reg_29490' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14791: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_498_reg_29495' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14793: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_499_reg_30194' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14795: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_502_reg_29500' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14797: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_504_reg_29505' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14799: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_505_fu_26021_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14801: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_507_reg_29510' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14803: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_195_fu_5100_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14805: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_508_reg_29515' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14807: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_509_reg_29520' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14809: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_511_fu_26046_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14811: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_512_reg_30199' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14813: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_515_reg_29525' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14815: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_517_reg_29530' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14817: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_518_fu_26068_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14819: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_520_reg_29535' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14821: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_522_reg_29540' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14823: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_523_fu_26084_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14825: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_reg_28670_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14827: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_524_fu_26094_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14829: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_526_reg_29545' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14831: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_528_reg_29550' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14833: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_529_fu_26110_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14835: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_531_reg_29555' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14837: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_532_reg_29560' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14839: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_533_reg_29565' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14841: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_535_fu_26135_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14843: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_536_fu_26145_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14845: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_537_reg_30204' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14847: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_52_reg_28675_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14849: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1175_fu_18720_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14851: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_539_reg_29570_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14853: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_542_reg_29575_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14855: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_545_reg_29580' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14857: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_547_reg_29585' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14859: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_548_reg_30209' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14861: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_551_reg_29590' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14863: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_553_reg_29595' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14865: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_554_fu_26179_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14867: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_556_reg_29600' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14869: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_55_reg_28680' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14871: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_557_reg_29605' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14873: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_558_reg_29610' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14875: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_560_fu_26204_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14877: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_561_reg_30214' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14879: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_564_reg_29615' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14881: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_566_reg_29620' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14883: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_567_fu_26226_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14885: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_569_reg_29625' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14887: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_571_reg_29630' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14889: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_572_fu_26242_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14891: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_reg_28685' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14893: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_573_fu_26252_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14895: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_575_reg_29635' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14897: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_577_reg_29640' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14899: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_578_fu_26268_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14901: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_580_reg_29645' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14903: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_581_reg_29650' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14905: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_582_reg_29655' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14907: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_584_fu_26293_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14909: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_585_fu_26303_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14911: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_586_reg_30219' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14913: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_58_reg_30059' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1273_fu_20082_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14917: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_588_reg_29660_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14919: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_591_reg_29665_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14921: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_594_reg_29670' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14923: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_596_reg_29675' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14925: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_597_reg_30224' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14927: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_600_reg_29680' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14929: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_602_reg_29685' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14931: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_603_fu_26337_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14933: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_605_reg_29690' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14935: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_reg_28690' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14937: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_606_reg_29695' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14939: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_607_reg_29700' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14941: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_609_fu_26362_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14943: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_610_reg_30229' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14945: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_613_reg_29705' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14947: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_615_reg_29710' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14949: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_616_fu_26384_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14951: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_618_reg_29715' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14953: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_620_reg_29720' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14955: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_621_fu_26400_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14957: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_63_reg_28695' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14959: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_622_fu_26410_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14961: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_624_reg_29725' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14963: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_626_reg_29730' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14965: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_627_fu_26426_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14967: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_629_reg_29735' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14969: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_630_reg_29740' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14971: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_631_reg_29745' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14973: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_633_fu_26451_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14975: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_634_fu_26461_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14977: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_635_reg_30234' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14979: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_64_fu_24599_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14981: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1371_fu_21444_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14983: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_637_reg_29750_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14985: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_640_reg_29755_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14987: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_643_reg_29760' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14989: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_645_reg_29765' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14991: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_646_reg_30239' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14993: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_649_reg_29770' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14995: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_651_reg_29775' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14997: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_652_fu_26495_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14999: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_654_reg_29780' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15001: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_66_reg_28700' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15003: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_reg_28590' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15005: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_655_reg_29785' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15007: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_656_reg_29790' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15009: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_658_fu_26520_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15011: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_659_reg_30244' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15013: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_662_reg_29795' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15015: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_664_reg_29800' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15017: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_665_fu_26542_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15019: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_667_reg_29805' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15021: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_669_reg_29810' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15023: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_670_fu_26558_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15025: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_67_reg_28705' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15027: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_671_fu_26568_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15029: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_673_reg_29815' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15031: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_675_reg_29820' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15033: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_676_fu_26584_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15035: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_678_reg_29825' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15037: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_679_reg_29830' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15039: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_680_reg_29835' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15041: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_682_fu_26609_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15043: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_683_fu_26619_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15045: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_684_reg_30249' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15047: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_68_reg_28710' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15049: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1469_fu_22806_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15051: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_686_reg_29840_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15053: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_689_reg_29845_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15055: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_692_reg_29850' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15057: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_694_reg_29855' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15059: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_695_reg_30254' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15061: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_698_reg_29860' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15063: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_700_reg_29865' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15065: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_701_fu_26653_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15067: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_703_reg_29870' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15069: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_70_fu_24624_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15071: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_704_reg_29875' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15073: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_705_reg_29880' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15075: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_707_fu_26678_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15077: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_708_reg_30259' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15079: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_711_reg_29885' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15081: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_713_reg_29890' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15083: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_714_fu_26700_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15085: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_716_reg_29895' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15087: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_718_reg_29900' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15089: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_719_fu_26716_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15091: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_71_reg_30064' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15093: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_720_fu_26726_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15095: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_722_reg_29905' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15097: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_724_reg_29910' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15099: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_725_fu_26742_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15101: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_727_reg_29915' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15103: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_728_reg_29920' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15105: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_729_reg_29925' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15107: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_731_fu_26767_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15109: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_732_fu_26777_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15111: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_733_reg_30264' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15113: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_74_reg_28715' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15115: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1567_fu_24168_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15117: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_735_reg_29930_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15119: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_738_reg_29935_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15121: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_741_reg_29940' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15123: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_743_reg_29945' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15125: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_744_reg_30269' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15127: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_747_reg_29950' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15129: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_749_reg_29955' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15131: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_750_fu_26811_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15133: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_752_reg_29960' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15135: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_76_reg_28720' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15137: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_753_reg_29965' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15139: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_754_reg_29970' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15141: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_756_fu_26836_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15143: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_757_reg_30274' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15145: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_760_reg_29975' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15147: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_762_reg_29980' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15149: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_763_fu_26858_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15151: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_765_reg_29985' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15153: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_767_reg_29990' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15155: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_768_fu_26874_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15157: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_77_fu_24646_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15159: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_769_fu_26884_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15161: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_771_reg_29995' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15163: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_773_reg_30000' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15165: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_774_fu_26900_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15167: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_776_reg_30005' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15169: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_777_reg_30010' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15171: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_778_reg_30015' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15173: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_780_fu_26925_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15175: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_781_fu_26935_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15177: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_782_reg_30279' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15179: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_79_reg_28725' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15181: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_81_reg_28730' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15183: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_82_fu_24662_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15185: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_8_reg_28595' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15187: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_83_fu_24672_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15189: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_85_reg_28735' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15191: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_87_reg_28740' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15193: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_88_fu_24688_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15195: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_90_reg_28745' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15197: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_91_reg_28750' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15199: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_92_reg_28755' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15201: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_94_fu_24713_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15203: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_95_fu_24723_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15205: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_96_reg_30069' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15207: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_reg_30044' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15209: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_293_fu_6462_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15211: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_98_reg_28760_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15213: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_101_reg_28765_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15215: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_104_reg_28770' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15217: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_106_reg_28775' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15219: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_107_reg_30074' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15221: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_110_reg_28780' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15223: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_112_reg_28785' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15225: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_113_fu_24757_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15227: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_115_reg_28790' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15229: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_12_reg_28600' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15231: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_116_reg_28795' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15233: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_117_reg_28800' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15235: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_119_fu_24782_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15237: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_120_reg_30079' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15239: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_123_reg_28805' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15241: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_125_reg_28810' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15243: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_126_fu_24804_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15245: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_128_reg_28815' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15247: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_130_reg_28820' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15249: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_131_fu_24820_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15251: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_reg_28605' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15253: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_132_fu_24830_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15255: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_134_reg_28825' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15257: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_136_reg_28830' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15259: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_137_fu_24846_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15261: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_139_reg_28835' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15263: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_140_reg_28840' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15265: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_141_reg_28845' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15267: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_143_fu_24871_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15269: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_144_fu_24881_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15271: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_145_reg_30084' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15273: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_15_fu_24441_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15275: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_391_fu_7824_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15277: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_147_reg_28850_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15279: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_150_reg_28855_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15281: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_153_reg_28860' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15283: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_155_reg_28865' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15285: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_156_reg_30089' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15287: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_159_reg_28870' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15289: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_161_reg_28875' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15291: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_162_fu_24915_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15293: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_164_reg_28880' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15295: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_reg_28610' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15297: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_3738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_LabelSelect_Batch_0_4zs87lj8'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_LabelSelect_Batch_0_4zs87lj8/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VLabelSelect_Batch_0.cpp > VLabelSelect_Batch_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VLabelSelect_Batch_0__ALLcls.o VLabelSelect_Batch_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VLabelSelect_Batch_0__Trace.cpp VLabelSelect_Batch_0__Syms.cpp VLabelSelect_Batch_0__Trace__Slow.cpp > VLabelSelect_Batch_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VLabelSelect_Batch_0__ALLsup.o VLabelSelect_Batch_0__ALLsup.cpp\n",
- " Archiving VLabelSelect_Batch_0__ALL.a ...\n",
- "ar r VLabelSelect_Batch_0__ALL.a VLabelSelect_Batch_0__ALLcls.o VLabelSelect_Batch_0__ALLsup.o\n",
- "ranlib VLabelSelect_Batch_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VLabelSelect_Batch_0__ALL.a -o VLabelSelect_Batch_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_LabelSelect_Batch_0_4zs87lj8'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VLabelSelect_Batch_0__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_3_67sx4sp7'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_3_67sx4sp7/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_3.cpp > VMatrixVectorActivation_3__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_3__ALLcls.o VMatrixVectorActivation_3__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_3__Trace.cpp VMatrixVectorActivation_3__Syms.cpp VMatrixVectorActivation_3__Trace__Slow.cpp > VMatrixVectorActivation_3__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_3__ALLsup.o VMatrixVectorActivation_3__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_3__ALL.a ...\n",
- "ar r VMatrixVectorActivation_3__ALL.a VMatrixVectorActivation_3__ALLcls.o VMatrixVectorActivation_3__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_3__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_3__ALL.a -o VMatrixVectorActivation_3 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_3_67sx4sp7'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VMatrixVectorActivation_3__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_2_dp2q3fl1'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_2_dp2q3fl1/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_2.cpp > VMatrixVectorActivation_2__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_2__ALLcls.o VMatrixVectorActivation_2__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_2__Trace.cpp VMatrixVectorActivation_2__Syms.cpp VMatrixVectorActivation_2__Trace__Slow.cpp > VMatrixVectorActivation_2__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_2__ALLsup.o VMatrixVectorActivation_2__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_2__ALL.a ...\n",
- "ar r VMatrixVectorActivation_2__ALL.a VMatrixVectorActivation_2__ALLcls.o VMatrixVectorActivation_2__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_2__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_2__ALL.a -o VMatrixVectorActivation_2 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_2_dp2q3fl1'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VMatrixVectorActivation_2__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_1_o5wwg70v'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_1_o5wwg70v/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_1.cpp > VMatrixVectorActivation_1__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_1__ALLcls.o VMatrixVectorActivation_1__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_1__Trace.cpp VMatrixVectorActivation_1__Syms.cpp VMatrixVectorActivation_1__Trace__Slow.cpp > VMatrixVectorActivation_1__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_1__ALLsup.o VMatrixVectorActivation_1__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_1__ALL.a ...\n",
- "ar r VMatrixVectorActivation_1__ALL.a VMatrixVectorActivation_1__ALLcls.o VMatrixVectorActivation_1__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_1__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_1__ALL.a -o VMatrixVectorActivation_1 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_1_o5wwg70v'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VMatrixVectorActivation_1__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_Thresholding_Batch_0_l97czx4u'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_Thresholding_Batch_0_l97czx4u/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VThresholding_Batch_0.cpp > VThresholding_Batch_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VThresholding_Batch_0__ALLcls.o VThresholding_Batch_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VThresholding_Batch_0__Trace.cpp VThresholding_Batch_0__Syms.cpp VThresholding_Batch_0__Trace__Slow.cpp > VThresholding_Batch_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VThresholding_Batch_0__ALLsup.o VThresholding_Batch_0__ALLsup.cpp\n",
- " Archiving VThresholding_Batch_0__ALL.a ...\n",
- "ar r VThresholding_Batch_0__ALL.a VThresholding_Batch_0__ALLcls.o VThresholding_Batch_0__ALLsup.o\n",
- "ranlib VThresholding_Batch_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VThresholding_Batch_0__ALL.a -o VThresholding_Batch_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_Thresholding_Batch_0_l97czx4u'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VThresholding_Batch_0__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_0_mpv09ezq'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_0_mpv09ezq/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_0.cpp > VMatrixVectorActivation_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_0__ALLcls.o VMatrixVectorActivation_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_0__Trace.cpp VMatrixVectorActivation_0__Syms.cpp VMatrixVectorActivation_0__Trace__Slow.cpp > VMatrixVectorActivation_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_0__ALLsup.o VMatrixVectorActivation_0__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_0__ALL.a ...\n",
- "ar r VMatrixVectorActivation_0__ALL.a VMatrixVectorActivation_0__ALLcls.o VMatrixVectorActivation_0__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_0__ALL.a -o VMatrixVectorActivation_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_0_mpv09ezq'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VMatrixVectorActivation_0__ALL.a\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim\n",
"from finn.transformation.fpgadataflow.prepare_ip import PrepareIP\n",
@@ -2353,7 +334,7 @@
},
{
"cell_type": "code",
- "execution_count": 13,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -2375,17 +356,9 @@
},
{
"cell_type": "code",
- "execution_count": 14,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Results are the same!\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"output_dict = oxe.execute_onnx(model_for_rtlsim, input_dict)\n",
"output_rtlsim = output_dict[list(output_dict.keys())[0]]\n",
@@ -2407,2943 +380,9 @@
},
{
"cell_type": "code",
- "execution_count": 15,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/insert_fifo.py:161: UserWarning: Overriding input FIFO depth to 32\n",
- " warnings.warn(\"Overriding input FIFO depth to 32\")\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/insert_fifo.py:208: UserWarning: Overriding output FIFO depth to 32\n",
- " warnings.warn(\"Overriding output FIFO depth to 32\")\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/prepare_ip.py:57: UserWarning: Using pre-existing code for Thresholding_Batch_0\n",
- " warnings.warn(\"Using pre-existing code for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/prepare_ip.py:57: UserWarning: Using pre-existing code for MatrixVectorActivation_0\n",
- " warnings.warn(\"Using pre-existing code for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/prepare_ip.py:57: UserWarning: Using pre-existing code for MatrixVectorActivation_1\n",
- " warnings.warn(\"Using pre-existing code for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/prepare_ip.py:57: UserWarning: Using pre-existing code for MatrixVectorActivation_2\n",
- " warnings.warn(\"Using pre-existing code for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/prepare_ip.py:57: UserWarning: Using pre-existing code for MatrixVectorActivation_3\n",
- " warnings.warn(\"Using pre-existing code for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/prepare_ip.py:57: UserWarning: Using pre-existing code for LabelSelect_Batch_0\n",
- " warnings.warn(\"Using pre-existing code for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/hlssynth_ip.py:71: UserWarning: Using pre-existing IP for LabelSelect_Batch_0\n",
- " warnings.warn(\"Using pre-existing IP for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/hlssynth_ip.py:71: UserWarning: Using pre-existing IP for MatrixVectorActivation_2\n",
- " warnings.warn(\"Using pre-existing IP for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/hlssynth_ip.py:71: UserWarning: Using pre-existing IP for MatrixVectorActivation_1\n",
- " warnings.warn(\"Using pre-existing IP for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/hlssynth_ip.py:71: UserWarning: Using pre-existing IP for MatrixVectorActivation_3\n",
- " warnings.warn(\"Using pre-existing IP for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/hlssynth_ip.py:71: UserWarning: Using pre-existing IP for MatrixVectorActivation_0\n",
- " warnings.warn(\"Using pre-existing IP for %s\" % node.name)\n",
- "/scratch/users/mirzam/finn/src/finn/transformation/fpgadataflow/hlssynth_ip.py:71: UserWarning: Using pre-existing IP for Thresholding_Batch_0\n",
- " warnings.warn(\"Using pre-existing IP for %s\" % node.name)\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//StreamingFIFO_6.v:32: Output port connection 'count' expects 5 bits on the pin connection, but pin connection's VARREF 'count' generates 4 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_6_0s1i_f39/project_StreamingFIFO_6/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:119: Operator EQ expects 32 or 6 bits on the LHS, but LHS's VARREF 'addr_' generates 5 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:171: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//StreamingFIFO_7.v:32: Output port connection 'count' expects 6 bits on the pin connection, but pin connection's VARREF 'count' generates 5 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_7_qj8yiehx/project_StreamingFIFO_7/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:119: Operator EQ expects 32 or 7 bits on the LHS, but LHS's VARREF 'addr_' generates 6 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:171: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 7 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//StreamingFIFO_5.v:32: Output port connection 'count' expects 7 bits on the pin connection, but pin connection's VARREF 'count' generates 6 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_5_feja1kw0/project_StreamingFIFO_5/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0.v:73: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0.v:74: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:73: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:74: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:236: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0_LabelSelect_Batch_0_Pipeline_VITIS_LOOP_495_3.v:257: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'ap_sig_allocacmp_block_1' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_LabelSelect_Batch_0_8ox9e2e8/project_LabelSelect_Batch_0/sol1/impl/verilog//LabelSelect_Batch_0.v:221: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1_flow_control_loop_pipe_no_ap_cont.v:50: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1_flow_control_loop_pipe_no_ap_cont.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:101: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:102: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:103: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:339: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:363: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:376: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'ap_ST_iter0_fsm_state1' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:389: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:424: Operator ASSIGNW expects 80 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_1_s5umz0lp/project_StreamingDataWidthConverter_Batch_1/sol1/impl/verilog//StreamingDataWidthConverter_Batch_1.v:454: Operator ASSIGNW expects 80 bits on the Assign RHS, but Assign RHS's VARREF 'ei_V_fu_58' generates 72 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:119: Operator EQ expects 32 or 7 bits on the LHS, but LHS's VARREF 'addr_' generates 6 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:171: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 7 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//StreamingFIFO_4.v:32: Output port connection 'count' expects 7 bits on the pin connection, but pin connection's VARREF 'count' generates 6 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_4_gep8u3ro/project_StreamingFIFO_4/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:584: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:585: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:586: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:828: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:852: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1575: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_739_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1577: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_771_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1579: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_915_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1581: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_931_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1583: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_947_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1585: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_963_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1587: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_979_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1589: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_1011_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1591: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_1155_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1593: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_1171_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1595: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_403_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1597: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_1187_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1599: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_1203_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1601: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_1219_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1603: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_1251_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1605: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_1395_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1607: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_1411_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1609: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_1427_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1611: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_1443_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1613: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_1459_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1615: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_1491_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1617: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_427_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1619: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_1635_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1621: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_1651_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1623: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_1667_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1625: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_1683_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1627: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_1699_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1629: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_1731_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1631: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_1875_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1633: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_1891_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1635: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_1907_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1637: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_1923_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1639: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_451_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1641: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_1939_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1643: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_1971_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1645: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_2115_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1647: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_2131_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1649: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_2147_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1651: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_2163_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1653: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_2179_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1655: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_2211_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1657: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_129_fu_2355_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1659: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_131_fu_2371_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1661: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_475_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1663: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_133_fu_2387_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1665: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_135_fu_2403_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1667: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_137_fu_2419_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1669: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_141_fu_2451_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1671: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_145_fu_2595_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1673: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_147_fu_2611_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1675: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_149_fu_2627_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1677: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_151_fu_2643_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1679: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_153_fu_2659_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1681: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_157_fu_2691_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1683: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_523_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1685: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_675_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1687: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_691_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1689: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_707_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1691: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_723_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1693: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_379_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1695: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_13_fu_829_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1697: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_reg_3215' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1699: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_995_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1701: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_1027_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1703: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_fu_1037_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1705: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_fu_1053_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1707: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_fu_1069_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1709: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_reg_3225' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1711: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_1235_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1713: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_1267_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1715: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_547_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1717: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_fu_1277_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1719: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_fu_1293_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1721: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_29_fu_1309_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1723: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_reg_3235' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1725: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_1475_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1727: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_1507_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1729: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_fu_1517_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1731: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_35_fu_1533_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1733: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_37_fu_1549_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1735: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_reg_3245' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1737: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_1_fu_557_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1739: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_1715_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1741: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_1747_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1743: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_fu_1757_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1745: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_fu_1773_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1747: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_fu_1789_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1749: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_reg_3255' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1751: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_1955_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1753: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_1987_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1755: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_fu_1997_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1757: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_51_fu_2013_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1759: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_fu_573_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1761: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_53_fu_2029_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1763: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_54_reg_3265' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1765: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_2195_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1767: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_2227_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1769: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_fu_2237_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1771: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_59_fu_2253_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1773: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_fu_2269_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1775: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_62_reg_3275' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1777: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_139_fu_2435_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1779: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_143_fu_2467_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1781: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_5_fu_589_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1783: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_65_fu_2477_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1785: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_67_fu_2493_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1787: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_69_fu_2509_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1789: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_70_reg_3285' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1791: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_155_fu_2675_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1793: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_159_fu_2707_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1795: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_73_fu_2717_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1797: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_75_fu_2733_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1799: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_77_fu_2749_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1801: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_78_reg_3295' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1803: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_reg_3205' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1805: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_755_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1807: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_787_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1809: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_fu_797_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1811: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_11_fu_813_p2' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3_Matrix_Vector_Activate_Stream_Batch.v:1813: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_499_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_3_v1o6vgm7/project_MatrixVectorActivation_3/sol1/impl/verilog//MatrixVectorActivation_3.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:587: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:588: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:589: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:590: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1146: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1170: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1194: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1357: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1397: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'nf_1_load_reg_3263' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1405: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1407: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1409: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1411: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1413: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1415: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1417: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1419: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_954_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_1082_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_1098_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_1114_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_1130_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_1146_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_1162_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_1274_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_1290_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_1306_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_1322_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_1338_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_1354_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_1466_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_1482_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_1498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_1514_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_1530_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_1546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_1658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_1674_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_1690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_1706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_1722_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_1738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_1850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_1866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_1882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_1898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_1914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_1930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_2042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_2058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_2074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_2090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_2106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_2122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_770_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_890_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_906_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_938_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1951: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_1_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1953: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_2_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1955: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_3_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1957: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_4_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1959: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_5_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1961: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_6_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1963: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_7_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1965: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_0_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1967: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_13_reg_3164' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1969: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_fu_2409_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1971: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_2437_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_1178_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1975: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_reg_3169' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1977: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_reg_3174' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1979: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_reg_3179' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1981: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_fu_2468_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1983: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_2496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_1370_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_794_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1989: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_reg_3184' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1991: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_reg_3189' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1993: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_29_reg_3194' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1995: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_fu_2527_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1997: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_2555_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:1999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_1562_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2001: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_reg_3199' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2003: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_35_reg_3204' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2005: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_37_reg_3209' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2007: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_fu_2586_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2009: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_1_reg_3139' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2011: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_2614_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_1754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2015: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_reg_3214' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2017: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_reg_3219' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2019: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_reg_3224' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2021: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_fu_2645_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2023: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_2673_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_1946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2027: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_reg_3229' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2029: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_51_reg_3234' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2031: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_reg_3144' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2033: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_53_reg_3239' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2035: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_54_fu_2704_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2037: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_2732_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_2138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2041: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_reg_3244' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2043: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_59_reg_3249' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2045: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_reg_3254' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2047: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_62_fu_2763_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2049: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_5_reg_3149' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2051: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_fu_2350_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2053: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_2378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_986_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2057: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_reg_3154' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2059: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_11_reg_3159' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2_Matrix_Vector_Activate_Stream_Batch.v:2061: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_2319_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_2_xmc4k10x/project_MatrixVectorActivation_2/sol1/impl/verilog//MatrixVectorActivation_2.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_6_2xp4mohe'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_6_2xp4mohe/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_6.cpp > VStreamingFIFO_6__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_6__ALLcls.o VStreamingFIFO_6__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_6__Trace.cpp VStreamingFIFO_6__Syms.cpp VStreamingFIFO_6__Trace__Slow.cpp > VStreamingFIFO_6__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_6__ALLsup.o VStreamingFIFO_6__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_6__ALL.a ...\n",
- "ar r VStreamingFIFO_6__ALL.a VStreamingFIFO_6__ALLcls.o VStreamingFIFO_6__ALLsup.o\n",
- "ranlib VStreamingFIFO_6__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_6__ALL.a -o VStreamingFIFO_6 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_6_2xp4mohe'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_6__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_5_eizqfluk'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_5_eizqfluk/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_5.cpp > VStreamingFIFO_5__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_5__ALLcls.o VStreamingFIFO_5__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_5__Trace.cpp VStreamingFIFO_5__Syms.cpp VStreamingFIFO_5__Trace__Slow.cpp > VStreamingFIFO_5__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_5__ALLsup.o VStreamingFIFO_5__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_5__ALL.a ...\n",
- "ar r VStreamingFIFO_5__ALL.a VStreamingFIFO_5__ALLcls.o VStreamingFIFO_5__ALLsup.o\n",
- "ranlib VStreamingFIFO_5__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_5__ALL.a -o VStreamingFIFO_5 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_5_eizqfluk'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_5__ALL.a\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:119: Operator EQ expects 32 or 7 bits on the LHS, but LHS's VARREF 'addr_' generates 6 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:171: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 7 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//StreamingFIFO_3.v:32: Output port connection 'count' expects 7 bits on the pin connection, but pin connection's VARREF 'count' generates 6 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_3_8abvbrq4/project_StreamingFIFO_3/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:587: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:588: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:589: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:590: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1146: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1170: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1194: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1357: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1397: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'nf_1_load_reg_3263' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1405: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1407: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1409: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1411: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1413: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1415: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1417: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1419: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_2779_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_954_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_1082_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_1098_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_1114_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_1130_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_1146_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_1162_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_1274_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_1290_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_1306_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_1322_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_1338_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_1354_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_1466_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_1482_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_1498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_1514_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_1530_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_1546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_1658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_1674_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_1690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_1706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_1722_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_1738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_1850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_1866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_1882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_1898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_1914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_1930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_2042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_2058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_2074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_2090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_2106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_2122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_770_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_890_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_906_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_938_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1951: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_1_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1953: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_2_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1955: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_3_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1957: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_4_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1959: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_5_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1961: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_6_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1963: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_7_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1965: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'p_ZL7threshs_0_q0' generates 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1967: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_13_reg_3164' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1969: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_fu_2409_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1971: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_2437_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_1178_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1975: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_reg_3169' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1977: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_reg_3174' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1979: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_reg_3179' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1981: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_fu_2468_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1983: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_2496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_1370_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_794_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1989: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_reg_3184' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1991: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_reg_3189' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1993: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_29_reg_3194' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1995: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_fu_2527_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1997: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_2555_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:1999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_1562_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2001: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_reg_3199' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2003: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_35_reg_3204' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2005: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_37_reg_3209' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2007: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_fu_2586_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2009: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_1_reg_3139' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2011: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_2614_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_1754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2015: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_reg_3214' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2017: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_reg_3219' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2019: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_reg_3224' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2021: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_fu_2645_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2023: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_2673_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_1946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2027: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_reg_3229' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2029: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_51_reg_3234' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2031: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_reg_3144' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2033: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_53_reg_3239' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2035: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_54_fu_2704_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2037: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_2732_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_2138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2041: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_reg_3244' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2043: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_59_reg_3249' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2045: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_reg_3254' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2047: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_62_fu_2763_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2049: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_5_reg_3149' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2051: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_fu_2350_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2053: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_2378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_986_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2057: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_reg_3154' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2059: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_11_reg_3159' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1_Matrix_Vector_Activate_Stream_Batch.v:2061: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_2319_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_1_n3pnmp3r/project_MatrixVectorActivation_1/sol1/impl/verilog//MatrixVectorActivation_1.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_4_bi3gt0zs'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_4_bi3gt0zs/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_4.cpp > VStreamingFIFO_4__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_4__ALLcls.o VStreamingFIFO_4__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_4__Trace.cpp VStreamingFIFO_4__Syms.cpp VStreamingFIFO_4__Trace__Slow.cpp > VStreamingFIFO_4__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_4__ALLsup.o VStreamingFIFO_4__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_4__ALL.a ...\n",
- "ar r VStreamingFIFO_4__ALL.a VStreamingFIFO_4__ALLcls.o VStreamingFIFO_4__ALLsup.o\n",
- "ranlib VStreamingFIFO_4__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_4__ALL.a -o VStreamingFIFO_4 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_4_bi3gt0zs'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_4__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_3_miiy8tff'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_3_miiy8tff/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_3.cpp > VMatrixVectorActivation_3__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_3__ALLcls.o VMatrixVectorActivation_3__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_3__Trace.cpp VMatrixVectorActivation_3__Syms.cpp VMatrixVectorActivation_3__Trace__Slow.cpp > VMatrixVectorActivation_3__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_3__ALLsup.o VMatrixVectorActivation_3__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_3__ALL.a ...\n",
- "ar r VMatrixVectorActivation_3__ALL.a VMatrixVectorActivation_3__ALLcls.o VMatrixVectorActivation_3__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_3__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_3__ALL.a -o VMatrixVectorActivation_3 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_3_miiy8tff'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VMatrixVectorActivation_3__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_7_ck6n3uuc'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_7_ck6n3uuc/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_7.cpp > VStreamingFIFO_7__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_7__ALLcls.o VStreamingFIFO_7__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_7__Trace.cpp VStreamingFIFO_7__Syms.cpp VStreamingFIFO_7__Trace__Slow.cpp > VStreamingFIFO_7__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_7__ALLsup.o VStreamingFIFO_7__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_7__ALL.a ...\n",
- "ar r VStreamingFIFO_7__ALL.a VStreamingFIFO_7__ALLcls.o VStreamingFIFO_7__ALLsup.o\n",
- "ranlib VStreamingFIFO_7__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_7__ALL.a -o VStreamingFIFO_7 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_7_ck6n3uuc'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_7__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_LabelSelect_Batch_0_vih00206'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_LabelSelect_Batch_0_vih00206/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VLabelSelect_Batch_0.cpp > VLabelSelect_Batch_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VLabelSelect_Batch_0__ALLcls.o VLabelSelect_Batch_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VLabelSelect_Batch_0__Trace.cpp VLabelSelect_Batch_0__Syms.cpp VLabelSelect_Batch_0__Trace__Slow.cpp > VLabelSelect_Batch_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VLabelSelect_Batch_0__ALLsup.o VLabelSelect_Batch_0__ALLsup.cpp\n",
- " Archiving VLabelSelect_Batch_0__ALL.a ...\n",
- "ar r VLabelSelect_Batch_0__ALL.a VLabelSelect_Batch_0__ALLcls.o VLabelSelect_Batch_0__ALLsup.o\n",
- "ranlib VLabelSelect_Batch_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VLabelSelect_Batch_0__ALL.a -o VLabelSelect_Batch_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_LabelSelect_Batch_0_vih00206'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VLabelSelect_Batch_0__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingDataWidthConverter_Batch_1_xit3s2ym'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingDataWidthConverter_Batch_1_xit3s2ym/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingDataWidthConverter_Batch_1.cpp > VStreamingDataWidthConverter_Batch_1__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingDataWidthConverter_Batch_1__ALLcls.o VStreamingDataWidthConverter_Batch_1__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingDataWidthConverter_Batch_1__Trace.cpp VStreamingDataWidthConverter_Batch_1__Syms.cpp VStreamingDataWidthConverter_Batch_1__Trace__Slow.cpp > VStreamingDataWidthConverter_Batch_1__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingDataWidthConverter_Batch_1__ALLsup.o VStreamingDataWidthConverter_Batch_1__ALLsup.cpp\n",
- " Archiving VStreamingDataWidthConverter_Batch_1__ALL.a ...\n",
- "ar r VStreamingDataWidthConverter_Batch_1__ALL.a VStreamingDataWidthConverter_Batch_1__ALLcls.o VStreamingDataWidthConverter_Batch_1__ALLsup.o\n",
- "ranlib VStreamingDataWidthConverter_Batch_1__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingDataWidthConverter_Batch_1__ALL.a -o VStreamingDataWidthConverter_Batch_1 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingDataWidthConverter_Batch_1_xit3s2ym'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingDataWidthConverter_Batch_1__ALL.a\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:101: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:102: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:103: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0_flow_control_loop_pipe_no_ap_cont.v:50: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0_flow_control_loop_pipe_no_ap_cont.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:339: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:363: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:376: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'ap_ST_iter0_fsm_state1' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:389: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:424: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingDataWidthConverter_Batch_0_e1l8jedz/project_StreamingDataWidthConverter_Batch_0/sol1/impl/verilog//StreamingDataWidthConverter_Batch_0.v:454: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'ei_V_fu_56' generates 8 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:119: Operator EQ expects 32 or 7 bits on the LHS, but LHS's VARREF 'addr_' generates 6 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:171: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 7 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//StreamingFIFO_2.v:32: Output port connection 'count' expects 7 bits on the pin connection, but pin connection's VARREF 'count' generates 6 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_2_ue1m3_ol/project_StreamingFIFO_2/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:119: Operator EQ expects 32 or 5 bits on the LHS, but LHS's VARREF 'addr_' generates 4 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:171: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//StreamingFIFO_1.v:32: Output port connection 'count' expects 5 bits on the pin connection, but pin connection's VARREF 'count' generates 4 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_1_yjdc0047/project_StreamingFIFO_1/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_2_4qhmjv_v'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_2_4qhmjv_v/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_2.cpp > VMatrixVectorActivation_2__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_2__ALLcls.o VMatrixVectorActivation_2__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_2__Trace.cpp VMatrixVectorActivation_2__Syms.cpp VMatrixVectorActivation_2__Trace__Slow.cpp > VMatrixVectorActivation_2__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_2__ALLsup.o VMatrixVectorActivation_2__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_2__ALL.a ...\n",
- "ar r VMatrixVectorActivation_2__ALL.a VMatrixVectorActivation_2__ALLcls.o VMatrixVectorActivation_2__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_2__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_2__ALL.a -o VMatrixVectorActivation_2 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_2_4qhmjv_v'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VMatrixVectorActivation_2__ALL.a\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0.v:68: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0.v:69: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:440: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:441: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:442: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:443: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1715: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1739: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1763: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1904: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'nf_1_fu_346' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1910: Operator ASSIGNW expects 56 bits on the Assign RHS, but Assign RHS's VARREF 'p_Result_s_fu_2138_p50' generates 49 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1914: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1916: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1918: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1920: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1922: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1924: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1926: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1928: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1930: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1932: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1934: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1936: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1938: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1940: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1942: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1944: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1946: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1948: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1950: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1952: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1954: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1956: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1958: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1960: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1962: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1964: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1966: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1968: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1970: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1972: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1974: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1976: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1978: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1980: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1982: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1984: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1986: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1988: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1990: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1992: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1994: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1996: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:1998: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2000: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2002: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2004: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2006: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2008: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0_Thresholding_Batch.v:2010: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'idxprom2_i_fu_1521_p1' generates 64 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_Thresholding_Batch_0_h_ip63q3/project_Thresholding_Batch_0/sol1/impl/verilog//Thresholding_Batch_0.v:186: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:119: Operator EQ expects 32 or 6 bits on the LHS, but LHS's VARREF 'addr_' generates 5 bits.\n",
- "%Warning-WIDTH: Use \"/* verilator lint_off WIDTH */\" and lint_on around source to disable this message.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:171: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 6 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:179: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:182: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:195: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:205: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:219: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:226: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:239: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:257: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:271: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:288: Operator ASSIGNDLY expects 392 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:291: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//StreamingFIFO_0.v:32: Output port connection 'count' expects 6 bits on the pin connection, but pin connection's VARREF 'count' generates 5 bits.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:179: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: *** See the manual before disabling this,\n",
- "%Warning-COMBDLY: else you may end up with different sim results.\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:180: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:181: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:182: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:183: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:188: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:189: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:190: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:191: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:192: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:195: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:196: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:197: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:198: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:199: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:205: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:206: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:207: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:208: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:209: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:212: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:213: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:214: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:215: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:216: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:219: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:220: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:221: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:222: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:223: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:226: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:227: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:228: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:229: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:230: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:239: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:240: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:241: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:242: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:243: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:246: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:247: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:248: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:251: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:252: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:257: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:258: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:259: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:260: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:261: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:264: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:265: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:266: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:267: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:268: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:271: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:272: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:273: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:274: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:275: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:278: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:279: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:280: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:281: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:282: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:288: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:289: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:290: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:291: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n",
- "%Warning-COMBDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_StreamingFIFO_0_7ac6_8n3/project_StreamingFIFO_0/sol1/impl/verilog//Q_srl.v:292: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0.v:80: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: Use \"/* verilator lint_off STMTDLY */\" and lint_on around source to disable this message.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0.v:81: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5050: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5051: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5052: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5053: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:5054: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_flow_control_loop_pipe_sequential_init.v:51: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-STMTDLY: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_flow_control_loop_pipe_sequential_init.v:52: Unsupported: Ignoring delay on this delayed statement.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6186: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6210: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6234: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:6258: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:7867: Operator ASSIGNW expects 49 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12803: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_205_fu_5758_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12805: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_207_fu_5774_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12807: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_209_fu_5790_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12809: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_211_fu_5806_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12811: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_213_fu_5822_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12813: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_215_fu_5838_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12815: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_217_fu_5854_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12817: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_219_fu_5870_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12819: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_221_fu_5886_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12821: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_223_fu_5902_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12823: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_21_fu_2826_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12825: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_225_fu_5918_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12827: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_227_fu_5934_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12829: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_229_fu_5950_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12831: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_231_fu_5966_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12833: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_233_fu_5982_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12835: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_235_fu_5998_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12837: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_237_fu_6014_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12839: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_239_fu_6030_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12841: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_241_fu_6046_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12843: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_243_fu_6062_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12845: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_23_fu_2850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12847: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_245_fu_6078_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12849: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_247_fu_6094_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12851: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_249_fu_6110_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12853: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_251_fu_6126_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_253_fu_6142_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_255_fu_6158_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_257_fu_6174_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_259_fu_6190_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_261_fu_6206_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_263_fu_6222_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_25_fu_2874_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_265_fu_6238_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_267_fu_6254_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_269_fu_6270_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_271_fu_6286_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_273_fu_6302_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_275_fu_6318_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_277_fu_6334_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_279_fu_6350_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_281_fu_6366_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_283_fu_6382_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_27_fu_2898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_285_fu_6398_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_287_fu_6414_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_289_fu_6430_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_291_fu_6446_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_295_fu_7056_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_297_fu_7072_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_299_fu_7088_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_301_fu_7104_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_303_fu_7120_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_305_fu_7136_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_29_fu_2922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_307_fu_7152_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_309_fu_7168_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_311_fu_7184_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_313_fu_7200_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_315_fu_7216_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_317_fu_7232_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_319_fu_7248_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_321_fu_7264_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_323_fu_7280_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_325_fu_7296_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_31_fu_2946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_327_fu_7312_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_329_fu_7328_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_331_fu_7344_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_333_fu_7360_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_335_fu_7376_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_337_fu_7392_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_339_fu_7408_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_341_fu_7424_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12951: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_343_fu_7440_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12953: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_345_fu_7456_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12955: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_33_fu_2970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12957: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_347_fu_7472_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12959: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_349_fu_7488_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12961: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_351_fu_7504_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12963: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_353_fu_7520_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12965: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_355_fu_7536_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12967: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_357_fu_7552_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12969: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_359_fu_7568_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12971: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_361_fu_7584_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_363_fu_7600_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12975: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_365_fu_7616_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12977: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_35_fu_2994_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12979: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_367_fu_7632_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12981: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_369_fu_7648_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12983: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_371_fu_7664_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_373_fu_7680_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_375_fu_7696_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12989: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_377_fu_7712_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12991: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_379_fu_7728_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12993: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_381_fu_7744_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12995: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_383_fu_7760_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12997: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_385_fu_7776_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:12999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_37_fu_3018_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13001: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_387_fu_7792_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13003: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_389_fu_7808_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13005: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_393_fu_8418_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13007: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_395_fu_8434_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13009: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_397_fu_8450_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13011: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_399_fu_8466_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_401_fu_8482_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13015: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_403_fu_8498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13017: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_405_fu_8514_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13019: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_407_fu_8530_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13021: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_39_fu_3042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13023: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_3_fu_2610_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_409_fu_8546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13027: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_411_fu_8562_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13029: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_413_fu_8578_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13031: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_415_fu_8594_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13033: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_417_fu_8610_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13035: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_419_fu_8626_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13037: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_421_fu_8642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_423_fu_8658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13041: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_425_fu_8674_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13043: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_427_fu_8690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13045: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_41_fu_3066_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13047: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_429_fu_8706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13049: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_431_fu_8722_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13051: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_433_fu_8738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13053: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_435_fu_8754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_437_fu_8770_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13057: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_439_fu_8786_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13059: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_441_fu_8802_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13061: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_443_fu_8818_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13063: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_445_fu_8834_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13065: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_447_fu_8850_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13067: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_43_fu_3090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13069: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_449_fu_8866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13071: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_451_fu_8882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13073: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_453_fu_8898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13075: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_455_fu_8914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13077: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_457_fu_8930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13079: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_459_fu_8946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13081: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_461_fu_8962_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13083: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_463_fu_8978_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13085: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_465_fu_8994_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13087: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_467_fu_9010_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13089: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_45_fu_3114_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13091: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_469_fu_9026_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13093: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_471_fu_9042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13095: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_473_fu_9058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13097: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_475_fu_9074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13099: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_477_fu_9090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13101: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_479_fu_9106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13103: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_481_fu_9122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13105: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_483_fu_9138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13107: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_485_fu_9154_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13109: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_487_fu_9170_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13111: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_47_fu_3138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13113: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_491_fu_9780_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13115: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_493_fu_9796_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13117: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_495_fu_9812_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13119: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_497_fu_9828_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13121: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_499_fu_9844_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13123: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_501_fu_9860_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13125: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_503_fu_9876_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13127: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_505_fu_9892_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13129: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_507_fu_9908_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13131: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_509_fu_9924_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13133: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_49_fu_3162_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13135: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_511_fu_9940_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13137: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_513_fu_9956_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13139: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_515_fu_9972_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13141: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_517_fu_9988_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13143: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_519_fu_10004_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13145: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_521_fu_10020_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13147: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_523_fu_10036_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13149: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_525_fu_10052_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13151: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_527_fu_10068_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13153: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_529_fu_10084_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13155: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_51_fu_3186_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13157: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_531_fu_10100_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13159: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_533_fu_10116_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13161: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_535_fu_10132_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13163: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_537_fu_10148_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13165: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_539_fu_10164_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13167: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_541_fu_10180_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13169: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_543_fu_10196_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13171: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_545_fu_10212_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13173: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_547_fu_10228_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13175: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_549_fu_10244_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13177: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_53_fu_3210_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13179: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_551_fu_10260_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13181: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_553_fu_10276_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13183: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_555_fu_10292_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13185: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_557_fu_10308_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13187: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_559_fu_10324_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13189: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_561_fu_10340_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13191: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_563_fu_10356_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13193: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_565_fu_10372_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13195: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_567_fu_10388_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13197: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_569_fu_10404_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13199: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_55_fu_3234_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13201: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_571_fu_10420_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13203: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_573_fu_10436_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13205: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_575_fu_10452_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13207: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_577_fu_10468_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13209: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_579_fu_10484_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13211: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_581_fu_10500_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13213: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_583_fu_10516_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13215: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_585_fu_10532_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13217: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_589_fu_11142_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13219: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_591_fu_11158_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13221: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_57_fu_3258_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13223: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_593_fu_11174_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13225: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_595_fu_11190_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13227: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_597_fu_11206_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13229: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_599_fu_11222_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13231: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_601_fu_11238_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13233: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_603_fu_11254_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13235: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_605_fu_11270_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13237: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_607_fu_11286_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13239: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_609_fu_11302_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13241: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_611_fu_11318_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13243: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_59_fu_3282_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13245: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_5_fu_2634_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13247: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_613_fu_11334_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13249: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_615_fu_11350_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13251: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_617_fu_11366_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13253: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_619_fu_11382_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13255: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_621_fu_11398_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13257: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_623_fu_11414_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13259: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_625_fu_11430_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13261: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_627_fu_11446_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13263: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_629_fu_11462_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13265: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_631_fu_11478_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13267: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_61_fu_3306_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13269: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_633_fu_11494_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13271: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_635_fu_11510_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13273: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_637_fu_11526_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13275: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_639_fu_11542_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13277: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_641_fu_11558_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13279: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_643_fu_11574_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13281: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_645_fu_11590_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13283: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_647_fu_11606_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13285: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_649_fu_11622_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13287: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_651_fu_11638_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13289: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_63_fu_3330_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13291: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_653_fu_11654_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13293: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_655_fu_11670_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13295: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_657_fu_11686_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13297: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_659_fu_11702_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13299: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_661_fu_11718_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13301: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_663_fu_11734_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13303: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_665_fu_11750_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13305: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_667_fu_11766_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13307: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_669_fu_11782_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13309: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_671_fu_11798_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13311: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_65_fu_3354_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13313: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_673_fu_11814_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13315: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_675_fu_11830_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13317: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_677_fu_11846_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13319: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_679_fu_11862_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13321: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_681_fu_11878_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13323: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_683_fu_11894_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13325: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_687_fu_12504_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13327: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_689_fu_12520_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13329: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_691_fu_12536_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13331: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_693_fu_12552_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13333: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_67_fu_3378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13335: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_695_fu_12568_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13337: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_697_fu_12584_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13339: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_699_fu_12600_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13341: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_701_fu_12616_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13343: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_703_fu_12632_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13345: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_705_fu_12648_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13347: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_707_fu_12664_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13349: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_709_fu_12680_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13351: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_711_fu_12696_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13353: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_713_fu_12712_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13355: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_69_fu_3402_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13357: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_715_fu_12728_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13359: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_717_fu_12744_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13361: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_719_fu_12760_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13363: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_721_fu_12776_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13365: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_723_fu_12792_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13367: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_725_fu_12808_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13369: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_727_fu_12824_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13371: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_729_fu_12840_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13373: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_731_fu_12856_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13375: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_733_fu_12872_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13377: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_71_fu_3426_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13379: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_735_fu_12888_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13381: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_737_fu_12904_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13383: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_739_fu_12920_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13385: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_741_fu_12936_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13387: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_743_fu_12952_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13389: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_745_fu_12968_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13391: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_747_fu_12984_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13393: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_749_fu_13000_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13395: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_751_fu_13016_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13397: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_753_fu_13032_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13399: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_73_fu_3450_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13401: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_755_fu_13048_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13403: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_757_fu_13064_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13405: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_759_fu_13080_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13407: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_761_fu_13096_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13409: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_763_fu_13112_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13411: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_765_fu_13128_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13413: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_767_fu_13144_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13415: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_769_fu_13160_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13417: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_771_fu_13176_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13419: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_773_fu_13192_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13421: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_75_fu_3474_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13423: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_775_fu_13208_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13425: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_777_fu_13224_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13427: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_779_fu_13240_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13429: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_781_fu_13256_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13431: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_785_fu_13866_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13433: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_787_fu_13882_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13435: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_789_fu_13898_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13437: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_791_fu_13914_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13439: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_793_fu_13930_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13441: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_795_fu_13946_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13443: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_77_fu_3498_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13445: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_797_fu_13962_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13447: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_799_fu_13978_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13449: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_801_fu_13994_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13451: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_803_fu_14010_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13453: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_805_fu_14026_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13455: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_807_fu_14042_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13457: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_809_fu_14058_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13459: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_811_fu_14074_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13461: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_813_fu_14090_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13463: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_815_fu_14106_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13465: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_79_fu_3522_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13467: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_7_fu_2658_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13469: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_817_fu_14122_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13471: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_819_fu_14138_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13473: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_821_fu_14154_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13475: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_823_fu_14170_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13477: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_825_fu_14186_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13479: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_827_fu_14202_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13481: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_829_fu_14218_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13483: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_831_fu_14234_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13485: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_833_fu_14250_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13487: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_835_fu_14266_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13489: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_81_fu_3546_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13491: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_837_fu_14282_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13493: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_839_fu_14298_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13495: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_841_fu_14314_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13497: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_843_fu_14330_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13499: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_845_fu_14346_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13501: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_847_fu_14362_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13503: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_849_fu_14378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13505: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_851_fu_14394_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13507: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_853_fu_14410_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13509: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_855_fu_14426_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13511: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_83_fu_3570_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13513: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_857_fu_14442_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13515: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_859_fu_14458_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13517: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_861_fu_14474_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13519: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_863_fu_14490_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13521: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_865_fu_14506_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13523: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_867_fu_14522_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13525: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_869_fu_14538_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13527: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_871_fu_14554_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13529: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_873_fu_14570_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13531: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_875_fu_14586_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13533: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_85_fu_3594_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13535: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_877_fu_14602_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13537: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_879_fu_14618_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13539: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_883_fu_15228_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13541: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_885_fu_15244_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13543: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_887_fu_15260_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13545: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_889_fu_15276_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13547: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_891_fu_15292_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13549: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_893_fu_15308_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13551: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_895_fu_15324_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13553: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_897_fu_15340_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13555: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_87_fu_3618_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13557: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_899_fu_15356_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13559: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_901_fu_15372_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13561: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_903_fu_15388_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13563: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_905_fu_15404_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13565: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_907_fu_15420_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13567: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_909_fu_15436_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13569: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_911_fu_15452_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13571: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_913_fu_15468_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13573: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_915_fu_15484_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13575: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_917_fu_15500_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13577: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_89_fu_3642_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13579: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_919_fu_15516_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13581: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_921_fu_15532_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13583: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_923_fu_15548_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13585: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_925_fu_15564_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13587: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_927_fu_15580_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13589: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_929_fu_15596_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13591: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_931_fu_15612_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13593: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_933_fu_15628_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13595: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_935_fu_15644_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13597: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_937_fu_15660_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13599: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_91_fu_3666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13601: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_939_fu_15676_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13603: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_941_fu_15692_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13605: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_943_fu_15708_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13607: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_945_fu_15724_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13609: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_947_fu_15740_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13611: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_949_fu_15756_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13613: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_951_fu_15772_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13615: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_953_fu_15788_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13617: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_955_fu_15804_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13619: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_957_fu_15820_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13621: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_93_fu_3690_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13623: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_959_fu_15836_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13625: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_961_fu_15852_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13627: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_963_fu_15868_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13629: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_965_fu_15884_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13631: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_967_fu_15900_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13633: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_969_fu_15916_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13635: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_971_fu_15932_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13637: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_973_fu_15948_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13639: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_975_fu_15964_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13641: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_977_fu_15980_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13643: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_95_fu_3714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13645: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_981_fu_16590_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13647: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_983_fu_16606_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13649: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_985_fu_16622_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13651: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_987_fu_16638_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13653: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_989_fu_16654_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13655: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_991_fu_16670_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13657: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_993_fu_16686_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13659: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_995_fu_16702_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13661: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_997_fu_16718_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13663: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_999_fu_16734_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13665: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_99_fu_4332_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13667: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1001_fu_16750_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13669: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1003_fu_16766_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13671: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1005_fu_16782_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13673: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1007_fu_16798_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13675: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1009_fu_16814_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13677: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1011_fu_16830_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13679: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1013_fu_16846_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13681: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1015_fu_16862_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13683: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1017_fu_16878_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13685: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1019_fu_16894_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13687: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_101_fu_4348_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13689: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_9_fu_2682_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13691: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1021_fu_16910_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13693: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1023_fu_16926_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13695: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1025_fu_16942_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13697: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1027_fu_16958_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13699: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1029_fu_16974_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13701: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1031_fu_16990_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13703: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1033_fu_17006_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13705: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1035_fu_17022_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13707: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1037_fu_17038_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13709: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1039_fu_17054_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13711: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_103_fu_4364_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13713: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1041_fu_17070_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13715: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1043_fu_17086_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13717: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1045_fu_17102_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13719: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1047_fu_17118_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13721: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1049_fu_17134_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13723: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1051_fu_17150_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13725: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1053_fu_17166_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13727: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1055_fu_17182_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13729: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1057_fu_17198_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13731: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1059_fu_17214_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13733: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_105_fu_4380_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13735: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1061_fu_17230_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13737: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1063_fu_17246_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13739: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1065_fu_17262_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13741: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1067_fu_17278_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13743: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1069_fu_17294_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13745: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1071_fu_17310_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13747: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1073_fu_17326_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13749: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1075_fu_17342_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13751: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1079_fu_17952_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13753: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1081_fu_17968_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13755: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_107_fu_4396_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13757: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1083_fu_17984_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13759: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1085_fu_18000_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13761: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1087_fu_18016_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13763: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1089_fu_18032_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13765: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1091_fu_18048_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13767: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1093_fu_18064_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13769: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1095_fu_18080_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13771: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1097_fu_18096_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13773: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1099_fu_18112_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13775: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1101_fu_18128_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13777: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_109_fu_4412_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13779: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1103_fu_18144_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13781: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1105_fu_18160_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13783: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1107_fu_18176_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13785: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1109_fu_18192_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13787: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1111_fu_18208_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13789: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1113_fu_18224_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13791: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1115_fu_18240_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13793: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1117_fu_18256_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13795: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1119_fu_18272_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13797: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1121_fu_18288_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13799: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_111_fu_4428_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13801: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1123_fu_18304_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13803: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1125_fu_18320_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13805: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1127_fu_18336_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13807: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1129_fu_18352_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13809: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1131_fu_18368_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13811: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1133_fu_18384_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13813: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1135_fu_18400_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13815: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1137_fu_18416_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13817: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1139_fu_18432_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13819: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1141_fu_18448_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13821: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_113_fu_4444_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13823: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1143_fu_18464_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13825: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1145_fu_18480_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13827: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1147_fu_18496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13829: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1149_fu_18512_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13831: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1151_fu_18528_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13833: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1153_fu_18544_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13835: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1155_fu_18560_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13837: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1157_fu_18576_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13839: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1159_fu_18592_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13841: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1161_fu_18608_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13843: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_115_fu_4460_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13845: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1163_fu_18624_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13847: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1165_fu_18640_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13849: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1167_fu_18656_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13851: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1169_fu_18672_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13853: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1171_fu_18688_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13855: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1173_fu_18704_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13857: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1177_fu_19314_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13859: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1179_fu_19330_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13861: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1181_fu_19346_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13863: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1183_fu_19362_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13865: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_117_fu_4476_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13867: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1185_fu_19378_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13869: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1187_fu_19394_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13871: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1189_fu_19410_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13873: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1191_fu_19426_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13875: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1193_fu_19442_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13877: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1195_fu_19458_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13879: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1197_fu_19474_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13881: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1199_fu_19490_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13883: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1201_fu_19506_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13885: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1203_fu_19522_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13887: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_119_fu_4492_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13889: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1205_fu_19538_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13891: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1207_fu_19554_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13893: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1209_fu_19570_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13895: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1211_fu_19586_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13897: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1213_fu_19602_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13899: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1215_fu_19618_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13901: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1217_fu_19634_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13903: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1219_fu_19650_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13905: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1221_fu_19666_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13907: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1223_fu_19682_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13909: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_121_fu_4508_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13911: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_11_fu_2706_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13913: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1225_fu_19698_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1227_fu_19714_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13917: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1229_fu_19730_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13919: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1231_fu_19746_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13921: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1233_fu_19762_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13923: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1235_fu_19778_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13925: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1237_fu_19794_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13927: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1239_fu_19810_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13929: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1241_fu_19826_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13931: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1243_fu_19842_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13933: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_123_fu_4524_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13935: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1245_fu_19858_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13937: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1247_fu_19874_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13939: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1249_fu_19890_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13941: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1251_fu_19906_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13943: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1253_fu_19922_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13945: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1255_fu_19938_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13947: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1257_fu_19954_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13949: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1259_fu_19970_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13951: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1261_fu_19986_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13953: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1263_fu_20002_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13955: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_125_fu_4540_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13957: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1265_fu_20018_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13959: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1267_fu_20034_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13961: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1269_fu_20050_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13963: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1271_fu_20066_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13965: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1275_fu_20676_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13967: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1277_fu_20692_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13969: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1279_fu_20708_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13971: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1281_fu_20724_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13973: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1283_fu_20740_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13975: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1285_fu_20756_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13977: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_127_fu_4556_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13979: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1287_fu_20772_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13981: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1289_fu_20788_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13983: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1291_fu_20804_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13985: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1293_fu_20820_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13987: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1295_fu_20836_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13989: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1297_fu_20852_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13991: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1299_fu_20868_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13993: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1301_fu_20884_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13995: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1303_fu_20900_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13997: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1305_fu_20916_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:13999: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_129_fu_4572_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14001: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1307_fu_20932_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14003: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1309_fu_20948_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14005: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1311_fu_20964_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14007: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1313_fu_20980_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14009: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1315_fu_20996_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14011: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1317_fu_21012_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14013: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1319_fu_21028_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14015: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1321_fu_21044_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14017: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1323_fu_21060_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14019: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1325_fu_21076_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14021: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_131_fu_4588_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14023: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1327_fu_21092_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14025: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1329_fu_21108_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14027: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1331_fu_21124_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14029: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1333_fu_21140_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14031: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1335_fu_21156_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14033: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1337_fu_21172_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14035: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1339_fu_21188_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14037: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1341_fu_21204_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14039: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1343_fu_21220_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14041: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1345_fu_21236_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14043: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_133_fu_4604_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14045: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1347_fu_21252_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14047: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1349_fu_21268_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14049: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1351_fu_21284_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14051: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1353_fu_21300_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14053: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1355_fu_21316_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14055: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1357_fu_21332_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14057: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1359_fu_21348_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14059: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1361_fu_21364_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14061: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1363_fu_21380_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14063: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1365_fu_21396_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14065: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_135_fu_4620_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14067: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1367_fu_21412_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14069: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1369_fu_21428_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14071: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1373_fu_22038_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14073: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1375_fu_22054_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14075: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1377_fu_22070_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14077: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1379_fu_22086_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14079: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1381_fu_22102_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14081: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1383_fu_22118_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14083: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1385_fu_22134_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14085: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1387_fu_22150_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14087: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_137_fu_4636_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14089: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1389_fu_22166_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14091: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1391_fu_22182_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14093: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1393_fu_22198_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14095: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1395_fu_22214_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14097: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1397_fu_22230_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14099: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1399_fu_22246_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14101: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1401_fu_22262_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14103: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1403_fu_22278_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14105: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1405_fu_22294_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14107: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1407_fu_22310_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14109: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_139_fu_4652_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14111: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1409_fu_22326_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14113: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1411_fu_22342_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14115: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1413_fu_22358_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14117: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1415_fu_22374_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14119: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1417_fu_22390_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14121: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1419_fu_22406_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14123: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1421_fu_22422_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14125: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1423_fu_22438_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14127: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1425_fu_22454_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14129: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1427_fu_22470_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14131: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_141_fu_4668_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14133: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_13_fu_2730_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14135: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1429_fu_22486_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14137: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1431_fu_22502_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14139: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1433_fu_22518_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14141: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1435_fu_22534_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14143: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1437_fu_22550_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14145: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1439_fu_22566_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14147: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1441_fu_22582_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14149: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1443_fu_22598_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14151: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1445_fu_22614_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14153: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1447_fu_22630_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14155: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_143_fu_4684_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14157: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1449_fu_22646_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14159: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1451_fu_22662_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14161: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1453_fu_22678_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14163: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1455_fu_22694_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14165: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1457_fu_22710_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14167: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1459_fu_22726_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14169: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1461_fu_22742_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14171: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1463_fu_22758_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14173: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1465_fu_22774_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14175: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1467_fu_22790_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14177: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_145_fu_4700_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14179: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1471_fu_23400_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14181: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1473_fu_23416_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14183: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1475_fu_23432_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14185: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1477_fu_23448_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14187: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1479_fu_23464_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14189: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1481_fu_23480_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14191: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1483_fu_23496_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14193: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1485_fu_23512_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14195: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1487_fu_23528_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14197: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1489_fu_23544_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14199: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_147_fu_4716_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14201: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1491_fu_23560_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14203: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1493_fu_23576_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14205: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1495_fu_23592_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14207: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1497_fu_23608_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14209: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1499_fu_23624_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14211: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1501_fu_23640_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14213: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1503_fu_23656_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14215: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1505_fu_23672_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14217: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1507_fu_23688_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14219: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1509_fu_23704_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14221: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_149_fu_4732_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14223: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1511_fu_23720_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14225: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1513_fu_23736_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14227: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1515_fu_23752_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14229: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1517_fu_23768_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14231: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1519_fu_23784_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14233: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1521_fu_23800_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14235: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1523_fu_23816_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14237: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1525_fu_23832_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14239: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1527_fu_23848_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14241: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1529_fu_23864_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14243: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_151_fu_4748_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14245: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1531_fu_23880_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14247: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1533_fu_23896_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14249: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1535_fu_23912_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14251: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1537_fu_23928_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14253: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1539_fu_23944_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14255: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1541_fu_23960_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14257: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1543_fu_23976_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14259: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1545_fu_23992_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14261: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1547_fu_24008_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14263: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1549_fu_24024_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14265: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_153_fu_4764_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14267: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1551_fu_24040_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14269: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1553_fu_24056_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14271: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1555_fu_24072_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14273: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1557_fu_24088_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14275: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1559_fu_24104_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14277: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1561_fu_24120_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14279: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1563_fu_24136_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14281: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1565_fu_24152_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14283: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_155_fu_4780_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14285: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_157_fu_4796_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14287: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_159_fu_4812_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14289: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_161_fu_4828_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14291: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_15_fu_2754_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14293: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_163_fu_4844_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14295: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_165_fu_4860_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14297: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_167_fu_4876_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14299: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_169_fu_4892_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14301: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_171_fu_4908_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14303: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_173_fu_4924_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14305: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_175_fu_4940_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14307: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_177_fu_4956_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14309: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_179_fu_4972_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14311: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_181_fu_4988_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14313: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_17_fu_2778_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14315: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_183_fu_5004_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14317: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_185_fu_5020_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14319: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_187_fu_5036_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14321: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_189_fu_5052_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14323: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_191_fu_5068_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14325: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_193_fu_5084_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14327: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_197_fu_5694_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14329: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_199_fu_5710_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14331: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_201_fu_5726_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14333: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_203_fu_5742_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14335: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_19_fu_2802_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14337: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1_fu_2586_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14339: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_165_reg_28885' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14341: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_166_reg_28890' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14343: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_168_fu_24940_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14345: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_169_reg_30094' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14347: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_172_reg_28895' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14349: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_174_reg_28900' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14351: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_175_fu_24962_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14353: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_177_reg_28905' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14355: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_179_reg_28910' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14357: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_180_fu_24978_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14359: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_18_reg_28615' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14361: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_181_fu_24988_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14363: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_183_reg_28915' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14365: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_185_reg_28920' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14367: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_186_fu_25004_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14369: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_188_reg_28925' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14371: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_189_reg_28930' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14373: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_190_reg_28935' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14375: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_192_fu_25029_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14377: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_193_fu_25039_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14379: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_194_reg_30099' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14381: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_19_reg_28620' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14383: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_489_fu_9186_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14385: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_196_reg_28940_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14387: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_199_reg_28945_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14389: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_202_reg_28950' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14391: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_204_reg_28955' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14393: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_205_reg_30104' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14395: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_208_reg_28960' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14397: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_210_reg_28965' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14399: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_211_fu_25073_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14401: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_213_reg_28970' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14403: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_21_fu_24466_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14405: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_214_reg_28975' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14407: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_215_reg_28980' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14409: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_217_fu_25098_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14411: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_218_reg_30109' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14413: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_221_reg_28985' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14415: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_223_reg_28990' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14417: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_224_fu_25120_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14419: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_226_reg_28995' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14421: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_228_reg_29000' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14423: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_229_fu_25136_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14425: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_22_reg_30049' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14427: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_230_fu_25146_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14429: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_232_reg_29005' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14431: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_234_reg_29010' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14433: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_235_fu_25162_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14435: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_237_reg_29015' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14437: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_238_reg_29020' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14439: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_239_reg_29025' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14441: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_241_fu_25187_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14443: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_242_fu_25197_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14445: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_243_reg_30114' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14447: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_25_reg_28625' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14449: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_587_fu_10548_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14451: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_245_reg_29030_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14453: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_248_reg_29035_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14455: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_251_reg_29040' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14457: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_253_reg_29045' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14459: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_254_reg_30119' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14461: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_257_reg_29050' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14463: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_259_reg_29055' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14465: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_260_fu_25231_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14467: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_262_reg_29060' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14469: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_27_reg_28630' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14471: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_263_reg_29065' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14473: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_264_reg_29070' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14475: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_266_fu_25256_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14477: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_267_reg_30124' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14479: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_270_reg_29075' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14481: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_272_reg_29080' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14483: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_273_fu_25278_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14485: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_275_reg_29085' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14487: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_277_reg_29090' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14489: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_278_fu_25294_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14491: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_28_fu_24488_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14493: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_279_fu_25304_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14495: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_281_reg_29095' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14497: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_283_reg_29100' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14499: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_284_fu_25320_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14501: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_286_reg_29105' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14503: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_287_reg_29110' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14505: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_288_reg_29115' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14507: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_290_fu_25345_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14509: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_291_fu_25355_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14511: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_292_reg_30129' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14513: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_30_reg_28635' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14515: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_685_fu_11910_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14517: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_294_reg_29120_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14519: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_297_reg_29125_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14521: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_300_reg_29130' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14523: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_302_reg_29135' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14525: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_303_reg_30134' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14527: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_306_reg_29140' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14529: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_308_reg_29145' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14531: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_309_fu_25389_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14533: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_311_reg_29150' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14535: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_32_reg_28640' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14537: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_312_reg_29155' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14539: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_313_reg_29160' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14541: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_315_fu_25414_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14543: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_316_reg_30139' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14545: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_319_reg_29165' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14547: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_321_reg_29170' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14549: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_322_fu_25436_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14551: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_324_reg_29175' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14553: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_326_reg_29180' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14555: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_327_fu_25452_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14557: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_33_fu_24504_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14559: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_reg_28580_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14561: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_328_fu_25462_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14563: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_330_reg_29185' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14565: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_332_reg_29190' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14567: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_333_fu_25478_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14569: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_335_reg_29195' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14571: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_336_reg_29200' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14573: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_337_reg_29205' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14575: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_339_fu_25503_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14577: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_340_fu_25513_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14579: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_341_reg_30144' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14581: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_34_fu_24514_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14583: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_783_fu_13272_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14585: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_343_reg_29210_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14587: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_346_reg_29215_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14589: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_349_reg_29220' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14591: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_351_reg_29225' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14593: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_352_reg_30149' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14595: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_355_reg_29230' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14597: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_357_reg_29235' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14599: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_358_fu_25547_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14601: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_360_reg_29240' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14603: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_36_reg_28645' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14605: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_361_reg_29245' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14607: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_362_reg_29250' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14609: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_364_fu_25572_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14611: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_365_reg_30154' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14613: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_368_reg_29255' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14615: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_370_reg_29260' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14617: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_371_fu_25594_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14619: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_373_reg_29265' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14621: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_375_reg_29270' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14623: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_376_fu_25610_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14625: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_38_reg_28650' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14627: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_377_fu_25620_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14629: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_379_reg_29275' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14631: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_381_reg_29280' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14633: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_382_fu_25636_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14635: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_384_reg_29285' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14637: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_385_reg_29290' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14639: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_386_reg_29295' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14641: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_388_fu_25661_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14643: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_389_fu_25671_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14645: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_390_reg_30159' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14647: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_39_fu_24530_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14649: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_881_fu_14634_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14651: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_392_reg_29300_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14653: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_395_reg_29305_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14655: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_398_reg_29310' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14657: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_400_reg_29315' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14659: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_401_reg_30164' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14661: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_404_reg_29320' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14663: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_406_reg_29325' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14665: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_407_fu_25705_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14667: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_409_reg_29330' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14669: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_41_reg_28655' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14671: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_410_reg_29335' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14673: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_411_reg_29340' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14675: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_413_fu_25730_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14677: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_414_reg_30169' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14679: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_417_reg_29345' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14681: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_419_reg_29350' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14683: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_420_fu_25752_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14685: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_422_reg_29355' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14687: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_424_reg_29360' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14689: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_425_fu_25768_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14691: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_42_reg_28660' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14693: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_426_fu_25778_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14695: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_428_reg_29365' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14697: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_430_reg_29370' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14699: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_431_fu_25794_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14701: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_433_reg_29375' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14703: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_434_reg_29380' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14705: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_435_reg_29385' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14707: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_437_fu_25819_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14709: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_438_fu_25829_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14711: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_439_reg_30174' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14713: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_43_reg_28665' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14715: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_979_fu_15996_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14717: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_441_reg_29390_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14719: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_444_reg_29395_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14721: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_447_reg_29400' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14723: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_449_reg_29405' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14725: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_450_reg_30179' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14727: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_453_reg_29410' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14729: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_455_reg_29415' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14731: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_456_fu_25863_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14733: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_458_reg_29420' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14735: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_45_fu_24555_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14737: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_459_reg_29425' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14739: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_460_reg_29430' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14741: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_462_fu_25888_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14743: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_463_reg_30184' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14745: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_466_reg_29435' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14747: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_468_reg_29440' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14749: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_469_fu_25910_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14751: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_471_reg_29445' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14753: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_473_reg_29450' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14755: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_474_fu_25926_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14757: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_46_fu_24565_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14759: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_475_fu_25936_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14761: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_477_reg_29455' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14763: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_479_reg_29460' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14765: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_480_fu_25952_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14767: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_482_reg_29465' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14769: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_483_reg_29470' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14771: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_484_reg_29475' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14773: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_486_fu_25977_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14775: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_487_fu_25987_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14777: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_488_reg_30189' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14779: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_47_reg_30054' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14781: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_3_reg_28585_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14783: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1077_fu_17358_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14785: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_490_reg_29480_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14787: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_493_reg_29485_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14789: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_496_reg_29490' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14791: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_498_reg_29495' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14793: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_499_reg_30194' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14795: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_502_reg_29500' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14797: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_504_reg_29505' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14799: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_505_fu_26021_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14801: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_507_reg_29510' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14803: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_195_fu_5100_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14805: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_508_reg_29515' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14807: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_509_reg_29520' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14809: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_511_fu_26046_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14811: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_512_reg_30199' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14813: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_515_reg_29525' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14815: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_517_reg_29530' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14817: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_518_fu_26068_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14819: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_520_reg_29535' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14821: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_522_reg_29540' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14823: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_523_fu_26084_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14825: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_49_reg_28670_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14827: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_524_fu_26094_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14829: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_526_reg_29545' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14831: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_528_reg_29550' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14833: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_529_fu_26110_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14835: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_531_reg_29555' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14837: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_532_reg_29560' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14839: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_533_reg_29565' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14841: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_535_fu_26135_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14843: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_536_fu_26145_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14845: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_537_reg_30204' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14847: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_52_reg_28675_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14849: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1175_fu_18720_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14851: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_539_reg_29570_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14853: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_542_reg_29575_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14855: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_545_reg_29580' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14857: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_547_reg_29585' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14859: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_548_reg_30209' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14861: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_551_reg_29590' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14863: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_553_reg_29595' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14865: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_554_fu_26179_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14867: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_556_reg_29600' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14869: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_55_reg_28680' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14871: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_557_reg_29605' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14873: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_558_reg_29610' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14875: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_560_fu_26204_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14877: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_561_reg_30214' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14879: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_564_reg_29615' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14881: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_566_reg_29620' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14883: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_567_fu_26226_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14885: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_569_reg_29625' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14887: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_571_reg_29630' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14889: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_572_fu_26242_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14891: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_57_reg_28685' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14893: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_573_fu_26252_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14895: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_575_reg_29635' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14897: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_577_reg_29640' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14899: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_578_fu_26268_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14901: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_580_reg_29645' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14903: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_581_reg_29650' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14905: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_582_reg_29655' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14907: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_584_fu_26293_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14909: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_585_fu_26303_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14911: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_586_reg_30219' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14913: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_58_reg_30059' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14915: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1273_fu_20082_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14917: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_588_reg_29660_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14919: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_591_reg_29665_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14921: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_594_reg_29670' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14923: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_596_reg_29675' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14925: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_597_reg_30224' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14927: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_600_reg_29680' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14929: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_602_reg_29685' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14931: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_603_fu_26337_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14933: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_605_reg_29690' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14935: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_61_reg_28690' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14937: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_606_reg_29695' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14939: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_607_reg_29700' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14941: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_609_fu_26362_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14943: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_610_reg_30229' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14945: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_613_reg_29705' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14947: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_615_reg_29710' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14949: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_616_fu_26384_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14951: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_618_reg_29715' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14953: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_620_reg_29720' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14955: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_621_fu_26400_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14957: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_63_reg_28695' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14959: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_622_fu_26410_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14961: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_624_reg_29725' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14963: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_626_reg_29730' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14965: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_627_fu_26426_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14967: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_629_reg_29735' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14969: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_630_reg_29740' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14971: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_631_reg_29745' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14973: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_633_fu_26451_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14975: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_634_fu_26461_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14977: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_635_reg_30234' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14979: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_64_fu_24599_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14981: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1371_fu_21444_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14983: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_637_reg_29750_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14985: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_640_reg_29755_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14987: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_643_reg_29760' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14989: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_645_reg_29765' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14991: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_646_reg_30239' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14993: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_649_reg_29770' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14995: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_651_reg_29775' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14997: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_652_fu_26495_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:14999: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_654_reg_29780' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15001: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_66_reg_28700' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15003: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_6_reg_28590' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15005: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_655_reg_29785' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15007: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_656_reg_29790' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15009: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_658_fu_26520_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15011: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_659_reg_30244' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15013: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_662_reg_29795' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15015: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_664_reg_29800' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15017: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_665_fu_26542_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15019: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_667_reg_29805' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15021: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_669_reg_29810' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15023: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_670_fu_26558_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15025: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_67_reg_28705' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15027: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_671_fu_26568_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15029: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_673_reg_29815' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15031: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_675_reg_29820' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15033: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_676_fu_26584_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15035: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_678_reg_29825' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15037: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_679_reg_29830' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15039: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_680_reg_29835' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15041: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_682_fu_26609_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15043: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_683_fu_26619_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15045: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_684_reg_30249' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15047: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_68_reg_28710' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15049: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1469_fu_22806_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15051: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_686_reg_29840_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15053: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_689_reg_29845_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15055: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_692_reg_29850' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15057: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_694_reg_29855' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15059: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_695_reg_30254' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15061: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_698_reg_29860' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15063: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_700_reg_29865' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15065: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_701_fu_26653_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15067: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_703_reg_29870' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15069: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_70_fu_24624_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15071: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_704_reg_29875' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15073: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_705_reg_29880' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15075: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_707_fu_26678_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15077: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_708_reg_30259' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15079: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_711_reg_29885' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15081: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_713_reg_29890' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15083: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_714_fu_26700_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15085: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_716_reg_29895' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15087: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_718_reg_29900' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15089: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_719_fu_26716_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15091: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_71_reg_30064' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15093: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_720_fu_26726_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15095: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_722_reg_29905' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15097: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_724_reg_29910' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15099: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_725_fu_26742_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15101: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_727_reg_29915' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15103: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_728_reg_29920' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15105: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_729_reg_29925' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15107: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_731_fu_26767_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15109: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_732_fu_26777_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15111: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_733_reg_30264' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15113: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_74_reg_28715' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15115: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_1567_fu_24168_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15117: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_735_reg_29930_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15119: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_738_reg_29935_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15121: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_741_reg_29940' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15123: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_743_reg_29945' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15125: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_744_reg_30269' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15127: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_747_reg_29950' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15129: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_749_reg_29955' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15131: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_750_fu_26811_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15133: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_752_reg_29960' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15135: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_76_reg_28720' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15137: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_753_reg_29965' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15139: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_754_reg_29970' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15141: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_756_fu_26836_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15143: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_757_reg_30274' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15145: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_760_reg_29975' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15147: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_762_reg_29980' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15149: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_763_fu_26858_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15151: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_765_reg_29985' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15153: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_767_reg_29990' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15155: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_768_fu_26874_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15157: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_77_fu_24646_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15159: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_769_fu_26884_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15161: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_771_reg_29995' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15163: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_773_reg_30000' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15165: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_774_fu_26900_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15167: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_776_reg_30005' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15169: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_777_reg_30010' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15171: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_778_reg_30015' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15173: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_780_fu_26925_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15175: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_781_fu_26935_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15177: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_782_reg_30279' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15179: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_79_reg_28725' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15181: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_81_reg_28730' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15183: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_82_fu_24662_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15185: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_8_reg_28595' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15187: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_83_fu_24672_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15189: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_85_reg_28735' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15191: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_87_reg_28740' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15193: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_88_fu_24688_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15195: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_90_reg_28745' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15197: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_91_reg_28750' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15199: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_92_reg_28755' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15201: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_94_fu_24713_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15203: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_95_fu_24723_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15205: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_96_reg_30069' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15207: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_9_reg_30044' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15209: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_293_fu_6462_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15211: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_98_reg_28760_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15213: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_101_reg_28765_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15215: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_104_reg_28770' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15217: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_106_reg_28775' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15219: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_107_reg_30074' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15221: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_110_reg_28780' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15223: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_112_reg_28785' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15225: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_113_fu_24757_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15227: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_115_reg_28790' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15229: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_12_reg_28600' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15231: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_116_reg_28795' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15233: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_117_reg_28800' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15235: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_119_fu_24782_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15237: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_120_reg_30079' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15239: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_123_reg_28805' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15241: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_125_reg_28810' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15243: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_126_fu_24804_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15245: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_128_reg_28815' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15247: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_130_reg_28820' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15249: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_131_fu_24820_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15251: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_14_reg_28605' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15253: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_132_fu_24830_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15255: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_134_reg_28825' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15257: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_136_reg_28830' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15259: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_137_fu_24846_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15261: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_139_reg_28835' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15263: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_140_reg_28840' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15265: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_141_reg_28845' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15267: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_143_fu_24871_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15269: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_144_fu_24881_p2' generates 4 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15271: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_145_reg_30084' generates 5 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15273: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_15_fu_24441_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15275: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_391_fu_7824_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15277: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_147_reg_28850_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15279: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_150_reg_28855_pp0_iter1_reg' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15281: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_153_reg_28860' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15283: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_155_reg_28865' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15285: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_156_reg_30089' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15287: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_159_reg_28870' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15289: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_161_reg_28875' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15291: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_162_fu_24915_p2' generates 3 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15293: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_164_reg_28880' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15295: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'add_ln886_17_reg_28610' generates 2 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0_Matrix_Vector_Activate_Stream_Batch.v:15297: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'xor_ln1065_97_fu_3738_p2' generates 1 bits.\n",
- "%Warning-WIDTH: /scratch/users/mirzam/build_files/code_gen_ipgen_MatrixVectorActivation_0_iop5muwc/project_MatrixVectorActivation_0/sol1/impl/verilog//MatrixVectorActivation_0.v:223: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_3_rt383eh7'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_3_rt383eh7/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_3.cpp > VStreamingFIFO_3__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_3__ALLcls.o VStreamingFIFO_3__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_3__Trace.cpp VStreamingFIFO_3__Syms.cpp VStreamingFIFO_3__Trace__Slow.cpp > VStreamingFIFO_3__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_3__ALLsup.o VStreamingFIFO_3__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_3__ALL.a ...\n",
- "ar r VStreamingFIFO_3__ALL.a VStreamingFIFO_3__ALLcls.o VStreamingFIFO_3__ALLsup.o\n",
- "ranlib VStreamingFIFO_3__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_3__ALL.a -o VStreamingFIFO_3 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_3_rt383eh7'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_3__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_1_dg7i0xin'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_1_dg7i0xin/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_1.cpp > VStreamingFIFO_1__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_1__ALLcls.o VStreamingFIFO_1__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_1__Trace.cpp VStreamingFIFO_1__Syms.cpp VStreamingFIFO_1__Trace__Slow.cpp > VStreamingFIFO_1__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_1__ALLsup.o VStreamingFIFO_1__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_1__ALL.a ...\n",
- "ar r VStreamingFIFO_1__ALL.a VStreamingFIFO_1__ALLcls.o VStreamingFIFO_1__ALLsup.o\n",
- "ranlib VStreamingFIFO_1__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_1__ALL.a -o VStreamingFIFO_1 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_1_dg7i0xin'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_1__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_2_mmspz0ul'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_2_mmspz0ul/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_2.cpp > VStreamingFIFO_2__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_2__ALLcls.o VStreamingFIFO_2__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_2__Trace.cpp VStreamingFIFO_2__Syms.cpp VStreamingFIFO_2__Trace__Slow.cpp > VStreamingFIFO_2__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_2__ALLsup.o VStreamingFIFO_2__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_2__ALL.a ...\n",
- "ar r VStreamingFIFO_2__ALL.a VStreamingFIFO_2__ALLcls.o VStreamingFIFO_2__ALLsup.o\n",
- "ranlib VStreamingFIFO_2__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_2__ALL.a -o VStreamingFIFO_2 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_2_mmspz0ul'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_2__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingDataWidthConverter_Batch_0_wz4bxmnr'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingDataWidthConverter_Batch_0_wz4bxmnr/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingDataWidthConverter_Batch_0.cpp > VStreamingDataWidthConverter_Batch_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingDataWidthConverter_Batch_0__ALLcls.o VStreamingDataWidthConverter_Batch_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingDataWidthConverter_Batch_0__Trace.cpp VStreamingDataWidthConverter_Batch_0__Syms.cpp VStreamingDataWidthConverter_Batch_0__Trace__Slow.cpp > VStreamingDataWidthConverter_Batch_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingDataWidthConverter_Batch_0__ALLsup.o VStreamingDataWidthConverter_Batch_0__ALLsup.cpp\n",
- " Archiving VStreamingDataWidthConverter_Batch_0__ALL.a ...\n",
- "ar r VStreamingDataWidthConverter_Batch_0__ALL.a VStreamingDataWidthConverter_Batch_0__ALLcls.o VStreamingDataWidthConverter_Batch_0__ALLsup.o\n",
- "ranlib VStreamingDataWidthConverter_Batch_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingDataWidthConverter_Batch_0__ALL.a -o VStreamingDataWidthConverter_Batch_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingDataWidthConverter_Batch_0_wz4bxmnr'\n",
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_1_9d48l5_d'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_1_9d48l5_d/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_1.cpp > VMatrixVectorActivation_1__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_1__ALLcls.o VMatrixVectorActivation_1__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_1__Trace.cpp VMatrixVectorActivation_1__Syms.cpp VMatrixVectorActivation_1__Trace__Slow.cpp > VMatrixVectorActivation_1__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_1__ALLsup.o VMatrixVectorActivation_1__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_1__ALL.a ...\n",
- "ar r VMatrixVectorActivation_1__ALL.a VMatrixVectorActivation_1__ALLcls.o VMatrixVectorActivation_1__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_1__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_1__ALL.a -o VMatrixVectorActivation_1 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_1_9d48l5_d'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingDataWidthConverter_Batch_0__ALL.a\n",
- "ar: creating VMatrixVectorActivation_1__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_Thresholding_Batch_0_lji2im9r'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_Thresholding_Batch_0_lji2im9r/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VThresholding_Batch_0.cpp > VThresholding_Batch_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VThresholding_Batch_0__ALLcls.o VThresholding_Batch_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VThresholding_Batch_0__Trace.cpp VThresholding_Batch_0__Syms.cpp VThresholding_Batch_0__Trace__Slow.cpp > VThresholding_Batch_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VThresholding_Batch_0__ALLsup.o VThresholding_Batch_0__ALLsup.cpp\n",
- " Archiving VThresholding_Batch_0__ALL.a ...\n",
- "ar r VThresholding_Batch_0__ALL.a VThresholding_Batch_0__ALLcls.o VThresholding_Batch_0__ALLsup.o\n",
- "ranlib VThresholding_Batch_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VThresholding_Batch_0__ALL.a -o VThresholding_Batch_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_Thresholding_Batch_0_lji2im9r'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VThresholding_Batch_0__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_0_kzagmadb'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_0_kzagmadb/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_0.cpp > VStreamingFIFO_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_0__ALLcls.o VStreamingFIFO_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VStreamingFIFO_0__Trace.cpp VStreamingFIFO_0__Syms.cpp VStreamingFIFO_0__Trace__Slow.cpp > VStreamingFIFO_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VStreamingFIFO_0__ALLsup.o VStreamingFIFO_0__ALLsup.cpp\n",
- " Archiving VStreamingFIFO_0__ALL.a ...\n",
- "ar r VStreamingFIFO_0__ALL.a VStreamingFIFO_0__ALLcls.o VStreamingFIFO_0__ALLsup.o\n",
- "ranlib VStreamingFIFO_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VStreamingFIFO_0__ALL.a -o VStreamingFIFO_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_StreamingFIFO_0_kzagmadb'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VStreamingFIFO_0__ALL.a\n"
- ]
- },
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_0_6xq7qv9u'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_0_6xq7qv9u/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_0.cpp > VMatrixVectorActivation_0__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_0__ALLcls.o VMatrixVectorActivation_0__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VMatrixVectorActivation_0__Trace.cpp VMatrixVectorActivation_0__Syms.cpp VMatrixVectorActivation_0__Trace__Slow.cpp > VMatrixVectorActivation_0__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o VMatrixVectorActivation_0__ALLsup.o VMatrixVectorActivation_0__ALLsup.cpp\n",
- " Archiving VMatrixVectorActivation_0__ALL.a ...\n",
- "ar r VMatrixVectorActivation_0__ALL.a VMatrixVectorActivation_0__ALLcls.o VMatrixVectorActivation_0__ALLsup.o\n",
- "ranlib VMatrixVectorActivation_0__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o VMatrixVectorActivation_0__ALL.a -o VMatrixVectorActivation_0 -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_MatrixVectorActivation_0_6xq7qv9u'\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating VMatrixVectorActivation_0__ALL.a\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.transformation.fpgadataflow.insert_dwc import InsertDWC\n",
"from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO\n",
@@ -5363,7 +402,7 @@
},
{
"cell_type": "code",
- "execution_count": 16,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -5376,37 +415,9 @@
},
{
"cell_type": "code",
- "execution_count": 17,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "make: Entering directory '/scratch/users/mirzam/build_files/pyverilator_ipstitched_grv0u_x9'\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o pyverilator_wrapper.o /scratch/users/mirzam/build_files/pyverilator_ipstitched_grv0u_x9/pyverilator_wrapper.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated.o /usr/share/verilator/include/verilated.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vfinn_design_wrapper.cpp > Vfinn_design_wrapper__ALLcls.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o Vfinn_design_wrapper__ALLcls.o Vfinn_design_wrapper__ALLcls.cpp\n",
- "/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vfinn_design_wrapper__Trace.cpp Vfinn_design_wrapper__Syms.cpp Vfinn_design_wrapper__Trace__Slow.cpp > Vfinn_design_wrapper__ALLsup.cpp\n",
- "g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC --std=c++11 -c -o Vfinn_design_wrapper__ALLsup.o Vfinn_design_wrapper__ALLsup.cpp\n",
- " Archiving Vfinn_design_wrapper__ALL.a ...\n",
- "ar r Vfinn_design_wrapper__ALL.a Vfinn_design_wrapper__ALLcls.o Vfinn_design_wrapper__ALLsup.o\n",
- "ranlib Vfinn_design_wrapper__ALL.a\n",
- "g++ -fPIC -shared pyverilator_wrapper.o verilated.o verilated_vcd_c.o Vfinn_design_wrapper__ALL.a -o Vfinn_design_wrapper -lm -lstdc++ 2>&1 | c++filt\n",
- "make: Leaving directory '/scratch/users/mirzam/build_files/pyverilator_ipstitched_grv0u_x9'\n",
- "Results are the same!\n"
- ]
- },
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ar: creating Vfinn_design_wrapper__ALL.a\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"output_dict = oxe.execute_onnx(model_for_rtlsim, input_dict)\n",
"output_rtlsim = output_dict[list(output_dict.keys())[0]]\n",
diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb
index 69ac1f771..85a4e9556 100644
--- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb
+++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb
@@ -57,7 +57,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -156,7 +156,7 @@
},
{
"cell_type": "code",
- "execution_count": 4,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -171,18 +171,9 @@
},
{
"cell_type": "code",
- "execution_count": 5,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Input shape for 1 batch: torch.Size([1000, 593])\n",
- "Label shape for 1 batch: torch.Size([1000])\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"count = 0\n",
"for x,y in train_quantized_loader:\n",
@@ -204,17 +195,9 @@
},
{
"cell_type": "code",
- "execution_count": 6,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Target device: cuda\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"device = torch.device(\"cuda\" if torch.cuda.is_available() else \"cpu\")\n",
"print(\"Target device: \" + str(device))"
@@ -236,7 +219,7 @@
},
{
"cell_type": "code",
- "execution_count": 7,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -304,7 +287,7 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -334,7 +317,7 @@
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -388,7 +371,7 @@
},
{
"cell_type": "code",
- "execution_count": 11,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -406,7 +389,7 @@
},
{
"cell_type": "code",
- "execution_count": 12,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -417,19 +400,9 @@
},
{
"cell_type": "code",
- "execution_count": 13,
- "metadata": {
- "scrolled": true
- },
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "Training loss = 0.131165 test accuracy = 0.809102: 100%|███████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████| 10/10 [02:24<00:00, 14.43s/it]\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import numpy as np\n",
"from sklearn.metrics import accuracy_score\n",
@@ -454,24 +427,9 @@
},
{
"cell_type": "code",
- "execution_count": 14,
- "metadata": {
- "scrolled": true
- },
- "outputs": [
- {
- "data": {
- "image/png": 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tPippq6Q1yevaNL/DROjuzDA4PMqGV/rLXYqZ2VlLLTgk1QJ3ANcAS4DrJS0Zt9qLwFsiogv4GLAiaR8G3h8RlwJvBH5v3LZ/GRFLk9eDaX2HidKdzQAeKdfMqkOaRxyXAxsjYlNEDAL3AsvzV4iIRyJibzL7GJBN2rdHxJPJdD/wLNCRYq2p6pw1nZlN9R56xMyqQprB0QFsyZvv4dR//N8DfG18o6SFwGuBx/Oab01Ob90taWahnUm6WdJqSat7e3tLLn4iSaK7M+NLcs2sKhQVHJJmSKpJpl8t6R2S6k+3WYG2grdPS3obueD44Lj2ZuCrwPsioi9p/hxwEbAU2A58qtA+I2JFRCyLiGXt7e2nKTV9XdkMz+/o59DgcLlLMTM7K8UecTwMTJPUAXwb+C3gb0+zTQ/QmTefBbaNX0lSF3AXsDwidue115MLjS9FxH1j7RGxIyJGImIU+AK5U2IVb2lnG6MB67f2nX5lM7MKVmxwKCIOAb8I/L+IeBe5Du9TWQUslrRIUgNwHbDyuJ1KC4D7gBsi4vm8dgF/AzwbEZ8et838vNl3AeuL/A5l1TXWQe5+DjOb5OqKXE+SrgDeTe6U0mm3jYhhSbcCDwG1wN0R8bSkW5LldwIfAWYDn81lBcMRsQy4ErgBeErSmmSXH06uoPqEpKXkTnttBt5b5HcoqznNjXRkprPGV1aZ2SRXbHC8D/gQcH/yx/9C4D9Pt1Hyh/7BcW135k3fBNxUYLsfULiPhIi4ociaK053p+8gN7PJr6jgiIjvAd8DSDrJd0XEH6RZWDXqzmZ48KlX2H3gCLObG8tdjpnZGSn2qqovS2qVNAN4Btgg6U/SLa36HB0pd6svyzWzyavYzvElyeWw7yR36mkBuT4IK8FrOtqQ3EFuZpNbscFRn1we+07ggYgY4iT3ZNjJNTfWsXhus28ENLNJrdjg+Dy5K5hmAA9LugDwDQlnoCubYe2WfUQ4d81scioqOCLi/0ZER0RcGzkvAW9Lubaq1N2ZYffBQXr2DpS7FDOzM1Js53ibpE+Pjf0k6VPkjj6sRN3ZNsCPkjWzyavYU1V3A/3ArySvPuCLaRVVzS6Z10pDbY2HWDezSavYGwAviohfypv/H3l3dFsJGupqWHJ+q6+sMrNJq9gjjgFJbxqbkXQl4JP0Z6g728ZTW/czMuoOcjObfIoNjluAOyRtlrQZ+GsmyRhRlai7M8OhwRFe6D1Q7lLMzEpW7FVVayOiG+gCuiLitcBPp1pZFRsbKXeNT1eZ2SRU0hMAI6Iv74FKf5xCPVPChXNm0NJY534OM5uUzubRsQVHr7XTq6kRl2XbfEmumU1KZxMc7tk9C92dGZ7d3sfhoZFyl2JmVpJTXo4rqZ/CASFgeioVTRHd2QzDo8Gz2/t47YKZ5S7HzKxop3uKX8u5KmSq6e7M3UG+dss+B4eZTSpnc6rKzsK81mnMbWl0P4eZTToOjjKRRFc242eQm9mk4+Aoo6WdbWzqPcj+gaFyl2JmVrRUg0PS1ZI2SNoo6bYCy98taV3yekRS9+m2lTRL0jcl/Th5n7QdBGM3Aq73o2TNbBJJLTgk1QJ3ANcAS4DrJS0Zt9qLwFsiogv4GLCiiG1vA74dEYuBbyfzk1JXMsS67yA3s8kkzSOOy4GNEbEpIgaBe4Hl+StExCMRsTeZfQzIFrHtcuCeZPoeco+znZQyTQ0smjODde7nMLNJJM3g6AC25M33JG0n8x7ga0Vse15EbAdI3ucW2pmkm8cePNXb23sG5Z8bXdk21m7xqSozmzzSDI5CQ5IUvNtc0tvIBccHS932ZCJiRUQsi4hl7e3tpWx6TnVnM7zSd5gdfYfLXYqZWVHSDI4eoDNvPgtsG7+SpC7gLmB5ROwuYtsdkuYn284Hdk5w3edU/o2AZmaTQZrBsQpYLGmRpAbgOmBl/gqSFgD3ATdExPNFbrsSuDGZvhF4IMXvkLqfOL+N2hr5UbJmNmkU++jYkkXEsKRbgYeAWuDuiHha0i3J8juBjwCzgc9KAhhOTi8V3DbZ9e3AVyS9B3gZ+OW0vsO5MK2+lovPa/Ed5GY2aaQWHAAR8SDw4Li2O/OmbwJuKnbbpH03cNXEVlpe3Z0Z/mPdNiKCJEDNzCqW7xyvAEs72+g7PMzm3YfKXYqZ2Wk5OCrA2B3k7iA3s8nAwVEBFs9tZnp9rTvIzWxScHBUgLraGl7T0eojDjObFBwcFaI7m+HpbX0MjYyWuxQzs1NycFSIrs4MR4ZH2fBKf7lLMTM7JQdHhVg61kHufg4zq3AOjgrROWs6M5vqWecBD82swjk4KsTYo2R9xGFmlc7BUUG6OzM8v6OfQ4PD5S7FzOykHBwVpDvbxmjA+q195S7FzOykHBwVZOwOcj8R0MwqmYOjgrS3NNKRme5nkJtZRXNwVJjuzjZ3kJtZRXNwVJjubIYtewbYc3Cw3KWYmRXk4KgwXb4R0MwqnIOjwlyWbUPCNwKaWcVycFSY5sY6XtXe7CMOM6tYDo4K1N2ZYV3PPiKi3KWYmZ3AwVGBurNt7DowyNZ9A+UuxczsBKkGh6SrJW2QtFHSbQWWXyLpUUlHJH0gr/1iSWvyXn2S3pcs+6ikrXnLrk3zO5RDd2cGgLXu5zCzClSX1o4l1QJ3AG8HeoBVklZGxDN5q+0B/gB4Z/62EbEBWJq3n63A/Xmr/GVEfDKt2svtknmtNNTWsK5nHz/XNb/c5ZiZHSfNI47LgY0RsSkiBoF7geX5K0TEzohYBQydYj9XAS9ExEvplVpZGupquPT8Vt9BbmYVKc3g6AC25M33JG2lug74x3Ftt0paJ+luSTMLbSTpZkmrJa3u7e09g48tr6XZNtZv3c/IqDvIzayypBkcKtBW0l9BSQ3AO4B/zmv+HHARuVNZ24FPFdo2IlZExLKIWNbe3l7Kx1aErmyGg4MjvNB7oNylmJkdJ83g6AE68+azwLYS93EN8GRE7BhriIgdETESEaPAF8idEqs6xzrI95W1DjOz8dIMjlXAYkmLkiOH64CVJe7jesadppKU31v8LmD9WVVZoS6cM4OWxjrfCGhmFSe1q6oiYljSrcBDQC1wd0Q8LemWZPmdkuYBq4FWYDS55HZJRPRJaiJ3RdZ7x+36E5KWkjvttbnA8qpQUyMuy7b5klwzqzipBQdARDwIPDiu7c686VfIncIqtO0hYHaB9hsmuMyK1d2Z4a7vb+Lw0AjT6mvLXY6ZGeA7xytad7aNoZHg2e1+lKyZVQ4HRwUb6yBf1+PTVWZWORwcFWxe6zTaWxp9ZZWZVRQHRwWTRHc24yurzKyiODgqXHe2jRd6D9J3+FSjspiZnTsOjgo31s/xlPs5zKxCODgqXFe2DfAzyM2scjg4KlymqYGFs5v4lyd6+O6GnX4qoJmVnYNjErjtmks5eGSY3/ziKq75q+/z1Sd6GBweLXdZZjZFaSr8C3bZsmWxevXqcpdxVgaHR3lgzVa+8P1NPL/jAPNap/Hbb1rI9ZcvoGVafbnLM7MqJOmJiFh2QruDY3KJCL67oZfPP/wCj23aQ0tjHb/2hgX81pWLmNc2rdzlmVkVcXBUSXDkW9ezj88/vImvPbWd2hrxju4Obn7zhVw8r6XcpZlZFXBwVGFwjHl59yHu/uGL/NOqLQwMjfDWi9u5+c0XcsWFs5EKPU/LzOz0HBxVHBxj9h4c5B8ee4l7Ht3MrgODXNbRxs1vvpBrXjOPulpfB2FmpXFwTIHgGHN4aIT7ntzKXd/fxKZdB+mcNZ33XLmIX3l9J00NqY6kb2ZVxMExhYJjzOho8M1nd7Di4U088dJeMk313PDGC7jxpxYyp7mx3OWZWYVzcEzB4Mi3evMePv/wJr717A7qa2v4pddl+Z3/togL25vLXZqZVaiTBYfPW0wRyxbOYtnCWbzQe4C7vv8iX32yh3tXvczbLz2P977lQn7yglnlLtHMJgkfcUxRvf1H+LtHN/N3j77E/oEhfvKCmdz85gt5+6XnUVPjK7HM7ORHHKleaiPpakkbJG2UdFuB5ZdIelTSEUkfGLdss6SnJK2RtDqvfZakb0r6cfI+M83vUK3aWxp5/89ezKMf+mk++gtL2NF3mPf+/RP8zKe/x5cff5nDQyPlLtHMKlRqRxySaoHngbcDPcAq4PqIeCZvnbnABcA7gb0R8cm8ZZuBZRGxa9x+PwHsiYjbkzCaGREfPFUtPuI4veGRUb62/hVWPLyJp7buZ05zAzdesZAbrriATFNDucszszIoxxHH5cDGiNgUEYPAvcDy/BUiYmdErAJKeUrRcuCeZPoecqFjZ6mutoZf6D6flbdeyZd/5w28pqONT33zea74P9/hoyufZsueQ+Uu0cwqRJqd4x3Alrz5HuANJWwfwDckBfD5iFiRtJ8XEdsBImJ7ctRyAkk3AzcDLFiwoNTapyxJ/NRFc/ipi+aw4ZV+Vjy8iS89/hJ/9+hmrr1sPj932Xwund/KgllN7gsxm6LSDI5Cf1VKOS92ZURsS4Lhm5Kei4iHi904CZoVkDtVVcLnWuLieS186le6+ZP/fjFf/OGLfPnxl/n3ddsBmNFQyyXzW7l0fgtL5rdx6fwWLpnXyvSG2jJXbWZpSzM4eoDOvPkssK3YjSNiW/K+U9L95E59PQzskDQ/OdqYD+ycwJqtgHlt0/jQtZfyR29/Nc/v6OeZbX08u72PZ7f388CPtvEPj70MQI1g4ZwZXDq/lSVjr/NbmdvS6DGzzKpImsGxClgsaRGwFbgO+LViNpQ0A6iJiP5k+meB/5ksXgncCNyevD8w0YVbYdPqa+nKZujKZo62RQQ9ewd4+miY9LF2yz7+IzkyAZg1o4ElY0cn57dy6fxWLmpvpt7jZ5lNSqnexyHpWuAzQC1wd0R8XNItABFxp6R5wGqgFRgFDgBLgDnA/clu6oAvR8THk33OBr4CLABeBn45Ivacqg5fVXXu7R8Y4rkkSJ5Jjk427Og/+uTChtoaFp/XfPToZOy9rckPpTKrFB5yxMFRdsMjo2zadTAXJtvGAqWPXQcGj67TkZme9JskYXJ+K50z3RFvVg4ecsTKrq62hlef18Krz2th+dKOo+07+w/z7Pb8vpM+vvPcTkaTf9PMaKjl0iRILk1OeS2aM4O26fXuOzErAx9xWEU6PDRyQkf8s9v76D8yfHSdlsY6OmZOp3NWE9mZ0+mcmbwn834Wu9nZ8RGHTSqn6oh/dnsfL+85RM/eAXr2HuLl3Yf44cZdHBo8fpiUTFP90UAZHy7ZmU2+dNjsDDk4bNKQROesXAiMFxHsPTREz95DbNmTC5QtyfTzO/r5znM7OZJ0zI+Z09xAdtxRyliwdMycTmOdg8WsEAeHVQVJzJrRwKwZDccdpYyJCHoPHDkaKmNHK1v2DPDU1v089PQrDI1E3v7gvJZpBUOlc1YT89qm+XJim7IcHDYlSGJuyzTmtkzjJy84cUDlkdFgR99hevYOsCU5DbZl7yF69h7iv17cwwNrBo521gPU1ojzWhrJNDXQOr2Otun1x71ax79PO7asoc6BY5Obg8OMXBCcn5nO+ZnpXL7oxIdaDY2M8sr+w7kw2ZMLlW37DrN/YJD9A0Ns3nWI/QND7B8YYuA0Q9JPr69NQqXuuKDJD5f80Ml/Tauv8ZVkVnYODrMi1NfWHOtfuejU6w4Oj7J/YIi+w0NHw6Rv3Hv+a9u+3OXIfQNDx101VrgOnXAkM7OpnvaWxtwRVWvjcdMtjXUOGptwDg6zCdZQV0N7S+4PeKmGR0bpPzx8XOjkAmd43HwumPYeGuSF3gP09h85ofMfYFp9zbEgaWnMvVqnHa1vbrJs9owG32RpRXNwmFWQutoaZs5oYOaM0h6eFRH0HR6mt/8wO/uOsLP/CDuT6d4DR9jZd4Tnd/Tzg4276D984lFNbY2Y09xwNGDGQqW99fjAmdPc4KvNzMFhVg0kHe0HedXcllOuOzA4Qm8SLLn3YyGzs/8I2/YfZm3PPnYfHKTQ/cGZpvqjRyq5cGmkvbmRWTMaaGqoZXpDXe69vpYZjcl0Qy1N9bXU+Uq0quDgMJtipjfUsmB2Ewtmn3g/TL7hkVF2HxxMAuVwLmDypnv7j/DiroPs7D983KXMp9JQW5MLkbEwaailqb7uhLYZDfltdTTV5y+vK7j9ub5aLSKIOPaQoYgg4GjYVvPVcw4OMyuorraG81qncV7rNKDtpOtFBPsODbFvYIhDg8MMDI5wKHkNDA1z8MjIsbahY8tz78McGhxh76FBtu47vq1Qn80p660R0xtqqa+tOe6P+Nh0rliS9uP/yAd5IVCgLX8fxY7S1NRQm+tLam482qfU3tx49AKG9uZcX9Ps5oZJd0+Qg8PMzoqkM+qXOZ2R0WBgaOTEMBoc4eBxbcn0UG7ZSHLDjZR7DOnYVWVjF5cJ5S3LW578n/zlx/ZzfBvSse2TZWP7kHLhsn9g6OiR2Y93HuCRF3azf2Co4HedNaPhaMCM9THlh83YdKUM7OngMLOKVFsjmhvraG6snj9TR4ZH2HVgMNe31HeY3gO5YDn6OnCEx188SO+BI0efXZOvoTZ3ldyc8Ucy+UczSfu0+vQuYqie/4+YmVW4xrpaOjLT6chMP+V6x66SOxYo44OmZ+8h1mzZe9KLGFqm1dHe0sj/ftdlvPHC2RP6PRwcZmYV5vir5JpPue7YRQzjj1zGrpzLpPBUTQeHmdkkdvxFDOfG5OrKNzOzsnNwmJlZSVINDklXS9ogaaOk2wosv0TSo5KOSPpAXnunpP+U9KykpyX9Yd6yj0raKmlN8ro2ze9gZmbHS62PQ1ItcAfwdqAHWCVpZUQ8k7faHuAPgHeO23wYeH9EPCmpBXhC0jfztv3LiPhkWrWbmdnJpXnEcTmwMSI2RcQgcC+wPH+FiNgZEauAoXHt2yPiyWS6H3gW6EixVjMzK1KawdEBbMmb7+EM/vhLWgi8Fng8r/lWSesk3S3pxMe55ba7WdJqSat7e3tL/VgzMzuJNIOj0H3xRY7ykuxAaga+CrwvIvqS5s+Re5TOUmA78KlC20bEiohYFhHL2tvbS/lYMzM7hTSDowfozJvPAtuK3VhSPbnQ+FJE3DfWHhE7ImIkIkaBL5A7JWZmZudImjcArgIWS1oEbAWuA36tmA2VG8Xrb4BnI+LT45bNj4jtyey7gPWn298TTzyxS9JLpRSfZw6w6wy3rUb+PY7xb3E8/x7Hq4bf44JCjYpixwg+A8mlsp8BaoG7I+Ljkm4BiIg7Jc0DVgOtwChwAFgCdAHfB55K2gE+HBEPSvp7cqepAtgMvDcvSNL4DqsjYlla+59s/Hsc49/ieP49jlfNv0eqQ45ExIPAg+Pa7sybfoXcKazxfkDhPhIi4oaJrNHMzErjO8fNzKwkDo7TW1HuAiqMf49j/Fscz7/H8ar290i1j8PMzKqPjzjMzKwkDg4zMyuJg+MUTje671RxqtGKpzJJtZJ+JOnfy11LuUnKSPoXSc8l/51cUe6aykXSHyX/O1kv6R8lnbsnLJ0jDo6TyBvd9xpy95ZcL2lJeasqm7HRii8F3gj83hT+LfL9IbkBOA3+Cvh6RFwCdDNFfxdJHeRG/F4WEa8hdw/bdeWtauI5OE7utKP7ThUerfhEkrLAzwF3lbuWcpPUCryZ3GgPRMRgROwra1HlVQdMl1QHNFHCUEuThYPj5CZkdN9qc5LRiqeizwB/yrGRDaayC4Fe4IvJqbu7JM0od1HlEBFbgU8CL5MbhHV/RHyjvFVNPAfHyZ316L7V5iSjFU85kn4e2BkRT5S7lgpRB7wO+FxEvBY4CEzJPsHkMQ/LgUXA+cAMSb9e3qomnoPj5M5qdN9qc7LRiqeoK4F3SNpM7hTmT0v6h/KWVFY9QE9EjB2F/gu5IJmKfgZ4MSJ6I2IIuA/4qTLXNOEcHCd3dHRfSQ3kOrhWlrmmsjjVaMVTUUR8KCKyEbGQ3H8X34mIqvtXZbGSMee2SLo4aboKeOYUm1Szl4E3SmpK/ndzFVV4oUCqgxxOZhExLOlW4CGOje77dJnLKpcrgRuApyStSdo+nAxiaQbw+8CXkn9kbQJ+q8z1lEVEPC7pX4AnyV2N+COqcOgRDzliZmYl8akqMzMriYPDzMxK4uAwM7OSODjMzKwkDg4zMyuJg8OsCJIOJO8LJf3aBO/7w+PmH5nI/ZtNNAeHWWkWAiUFRzLS8qkcFxwRUXV3Glt1cXCYleZ24L9JWpM8d6FW0l9IWiVpnaT3Akh6a/IMky8DTyVt/yrpieRZDTcnbbeTG0l1jaQvJW1jRzdK9r1e0lOSfjVv39/Ne/7Fl5K7lJF0u6Rnklo+ec5/HZsSfOe4WWluAz4QET8PkATA/oh4vaRG4IeSxkZDvRx4TUS8mMz/dkTskTQdWCXpqxFxm6RbI2Jpgc/6RWApuedbzEm2eThZ9lrgJ8iNn/ZD4EpJzwDvAi6JiJCUmdivbpbjIw6zs/OzwG8kQ7E8DswGFifL/isvNAD+QNJa4DFyA2gu5tTeBPxjRIxExA7ge8Dr8/bdExGjwBpyp9D6gMPAXZJ+ETh0lt/NrCAHh9nZEfD7EbE0eS3Ke/7CwaMrSW8lN3LqFRHRTW4Mo9M9UrTQ0P5jjuRNjwB1ETFM7ijnq8A7ga+X8D3MiubgMCtNP9CSN/8Q8LvJsPNIevVJHmLUBuyNiEOSLiH3CN4xQ2Pbj/Mw8KtJP0o7uafs/dfJCkuel9KWDD75PnKnucwmnPs4zEqzDhhOTjn9LblnbS8Enkw6qHvJ/Wt/vK8Dt0haB2wgd7pqzApgnaQnI+Ldee33A1cAa8k9ROxPI+KVJHgKaQEekDSN3NHKH53RNzQ7DY+Oa2ZmJfGpKjMzK4mDw8zMSuLgMDOzkjg4zMysJA4OMzMriYPDzMxK4uAwM7OS/H98iA8C+mcx5AAAAABJRU5ErkJggg==\n",
- "text/plain": [
- "<Figure size 432x288 with 1 Axes>"
- ]
- },
- "metadata": {
- "needs_background": "light"
- },
- "output_type": "display_data"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"%matplotlib inline\n",
"import matplotlib.pyplot as plt\n",
@@ -482,22 +440,9 @@
},
{
"cell_type": "code",
- "execution_count": 15,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "image/png": 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fvt+HetXkWUuHctB36e5XHGzb4ewjIlIVuTtT52/gt68tJinJeOCyAZx3fNugy6pUMcegmXUH/gDUBf7h7rPjVZSISJB2FRTxm6mLmbZgI4M7N+WeMf1p17hu0GVVuvJOUqe6e0HEqj8Bvyd0P8JLQP/4liYiUvky1m7ntimZbNpVwE/P7MnNI7tX6xPR5SmvB/GGmT3l7k+Hl4uAzoQCoiTehYmIVKbiklLu/yCL+z9YSfsmabx041AGdmwSdFmBKi8gRgE3mdnbwF+A/wFuBdKAyyuhNhGRSpG9fS+3v5DJ3HU7uGhAO/44uk+1mDL0aJV3kroEeMDMngZ+B7QBfuvuqyqrOBGReHs9cwO/mboYgIlj+jO6f9THvtVI5Z2DGAL8DCgE/hfYB/zFzHKAP7l7XuWUKCJS8XYXFPH715fw6vwNDOrUhHsv7U+HpmlBl5VQyhtimgRcDNQHHnb3YcAYMzsVeBE4qxLqExGpcPPX7+C2KZnk7NjL7Wf0YMLI7qQka4LNssoLiBJCJ6XTCPUiAHD3mcDM+JYlIlLxSkqdhz7M4t73V9K6YSov3jCU9M5Ngy4rYZUXEJcBNxAKh6sqpxwRkfjYsHMfd0zJ5Iu12/l+v7b86YLjaFRXJ6LLU95J6hXATyuxFhGRuPjPwo386tVFlJQ6//xhPy4c0A6zmnlvw+E46KCbmf3nUI1j2UdEJCj5+4v52UsLmPDcfLq2qM+btw3nooHtFQ4xKm+I6WQzm1bOdgOOreB6REQqxILsndw2ZT7rtu9lwsju3HZGD2rpRPRhKS8gRsfQvvDQu4iIVJ6SUufhWav45/QVtGxQhynXn8iQrs2CLqtKKu8chK5UEpEq5au8ffzkhQXMXr2Nc/u24X8v7EujNJ2IPlI146HmUuWUlDrb9uynZcPUoEuRKuLtxV/xi1cWUVRSyt8uPp5LBulcw9HSgJwkpD/9Zykn3fUB/134VdClSILbW1jML19dyI3PzKNTszT+e+twfpjeQeFQAQ7ZgzCz84A33b20EuoRYVNeAc99vp6UZOOW5+ext/B4LqnGE8PLkVu8IY9bp8xnzdZ8bhrRjTvO6EntFP3dW1Fi+STHACvN7G9m1jveBYk8PGsVJe68Pv5kTurWnJ+9vJCnZ68NuixJIKWlziOzVnPhQ5+wd38Jz143hF+M6qVwqGCH7EG4+xVm1hAYCzxuZg48Djzv7rvLa2tmo4CJQDLwqLvfFWWfEcC9QC1gq7ufGl6/FthN6JEfxQebVFuqly27Q72Hiwa045jWDXj0R+lMeG4ev319CfmFJdx4aregS6yxNuUV8NCMLLblhy5eNPh6GCf0O1HX8/V6+9Y+hNtYeMnsm2NQZl8rc4wvv9rNF2u3M6pPa/56UV+a1Ktd4e9XYjxJ7e67zOwVQtON3g5cCPzMzO5z9/ujtTGzZOBB4EwgB5hjZtPcfWnEPo2Bh4BR7r7ezFqWOcxId996mO9JqrBHZq2mqKSU8SO7A5BaK5l/XTGIO17I5K63vmTv/mLuOLOnxpcrUUmp89Tstdw9fQWFJaV0aFIXh9DUYd/8B3eP+B0OLLmHfojY70A7//oYHvF75P5l14cW6qQk89eL+jLmBJ1riKdYzkGcD/wY6AY8DQx29y1mlgYsA6IGBDAYyHL31eHjTCF0b8XSiH0uA1519/UA7r7lSN+IVH1b9+znmc/Wc0H/dnRuXu/r9bWSk5g4ZgB1ayVz3wdZ5BeW8Jtze+uLoRIsysnjV1MXsWhDHqf0bMGfRvehU7N6h24o1UIsPYhLgHvcfVbkSnffa2Y/LqddOyA7YjkHGFJmn55ALTObATQAJrr7UwdeApgeHtJ62N0nR3sRMxsHjAPo2LFjDG9HEtWjH62hoLiE8ad1/8625CTj/35wPPXqpPDvj9ewt7CEv1xwHEk1dK7geNtdUMTd01fw1Oy1NKtfh/vHDuC849solGuYWALi98DX1xqaWV2glbuvdff3y2kX7V+Sl1lOAQYBpxMavpptZp+FHxQ4zN03hoed3jWzL8uGFEA4OCYDpKenlz2+VBHb8wt5avZazj++Ld1a1I+6T1KS8fvzj6Vu7WT+NWMVBUUl/P3i4/Uc/wrk7ry9eBN/eGMJW3bv54ohnfifs47RU09rqFgC4iXgpIjlkvC6Ew7RLgeIvDaxPbAxyj5b3T0fyDezWUA/YIW7b4TQsJOZTSU0ZPWdgJDq4bGP17CvqIQJUXoPkcyMX4zqRf06Kfz9neXsLSzmvrEDqJOSXEmVVl/Z2/fy+2lL+ODLLfRu05BJVwxiQMcmQZclAYrlT68Ud4+cMKgQiOWSgTlADzPrYma1CV0uW/bhf68Dw80sJXxOYwiwzMzqmVkDADOrB3wPWBzDa0oVlLe3iCc+Xcs5x7WhZ6sGMbUZP7I7vz3vWN5ZsplxT81lX2FJnKusvopKSpk0cxXfu2cWn63exm/O7c0bE4YpHCSmHkSumX3f3acBmNlo4JBXFrl7sZlNAN4hdJnrY+6+xMxuDG+f5O7LzOxtYCFQSuhS2MVm1hWYGh7vTAGec/e3j+QNSuJ77JM17NlffMjeQ1nXntyFerWT+eXURVz9+Bf8++oTqF9HT485HHPXbefXUxfz5abdnHlsK/7w/T60a1w36LIkQZh7+cP2ZtYNeBZoS+i8QjZwlbtnxb+8w5Oenu4ZGRlBlyGHYVdBEcPu+oCTujXj4SuP7FaX1zM38JMXF9C3XSOevGawHs4Wg7y9Rdz19pc8/8V62jRK5Q/f78NZfVoHXZYEwMzmHuw+s1hulFsFnGhm9QkFSrk3x4kcjic/WcvugmJuOa3HER9jdP92pNZK5pbn5jPmkc94+trBNK9fpwKrrD7cndczN/Ln/y5le34h157chTvO7Kmel0QV078KMzsX6AOkHrjMzd3/Xxzrkhpgz/5iHv14DWf0bslx7Rod1bHO6tOaR36Uzg1PZ3Dpw7N59roTad1IT4KNtGZrPr99bTEfZ22lX/tGPHHN4KP+3KV6O+RJajObBFwK3EJoiOkSoFOc65Ia4KnZa8nbV3RUvYdIp/ZswZPXDGbzrv1c8vCnZG/fWyHHrer2F5cw8b2VnHXvLBZk7+T/je7DqzcPUzjIIcVyFdNJ7n4VsMPd/wgM5duXr4octvz9xTz60RpGHNOCfh0aV9hxh3RtxjPXDWHXvmIumTSbVbl7KuzYVdHsVds4e+JH3PPeCs48thXv/fRUrhramWTdYCgxiCUgCsL/3WtmbYEioEv8SpKa4NnP17E9v7DCeg+R+ndozJRxJ1JcWsqlD89m2Ve7Kvw1Et22Pfv5yYuZjH3kM4pKSnnimhN48LKBtNIETHIYYgmIN8IP1fs7MA9YCzwfx5qkmttXWMLkWasZ3qM5gzrF51r73m0a8sINQ0lJSmLM5M/IzN4Zl9dJNKWlzgtz1nP6P2cyLXMjN4/oxvTbT2XEMWWfgylyaOUGhJklAe+7+053f4XQuYde7v67SqlOqqXnvljP1j2F3Hp6xfceInVrUZ+XbhxKo7q1uPyRz/h89ba4vl7QVm7ezZjJn/GLVxbRo2V93rxtOD8f1Yu6tXWXuRyZcgMiPIvc3RHL+909L+5VSbVVUFTCpJmrGNq1GSd0bhr31+vQNI0XbxhK60ap/OjxL5i5Ijfur1nZ9hWW8Pd3vuSc+z5i+ebd/N8P+vLCuKEx35UucjCxDDFNN7MfmB7jKBXghTnZ5O7eH/feQ6TWjVJ54YahdG1en+ufzOCdJZsq7bXjbcbyLXzv3pk8+OEqzj++Le//9FQuPaGjnnIrFSKWgPgJoYfz7TezXWa228xq3lk/OWr7i0v414xVDO7clBO7xr/3EKl5/To8f/2JHNu2ITc/O4/XMzdU6utXtC27Chj/3DyufnwOtZKSeO66Ifzz0v66QVAqVCx3UqufKhXipYwcNu0q4B+X9AtkXoFGabV45rohXPfkHG5/IZO9hSWMHVy15hApKXWe/Xwdf397OfuLS7n9jB7cNKKbnmYrcRHLjHKnRFsfbW4GkYMpLC7lXzNWMbBjY4Z1bxZYHfXrpPDENYO58Zm5/PLVRewtLOHak6vGVdtLNubxq6mLWZC9k5O6NePPFxxH14PMnSFSEWJ51MbPIn5PJTQvw1zgtLhUJNXSq/Ny2LBzH3+58LjAZyVLrZXMw1cO4rbnM/nTf5ayr7CY8SO7B15XWe5O9vZ9zF2/nU+ytjF1/gYa163FPZf244L+7RKuXql+YhliOj9y2cw6AH+LW0VS7RSVlPLgjCz6tW/EqT1bBF0OEJr0/oHLBvCzlxfyj+kryC8s4ednHRPol25BUQlLNuYxd92O8M9Otu7ZD4R6Ppee0IGfn3UMjdNimY5F5OgdySMcc4DjKroQqb5em7+B7O37+MP5fRLqr96U5CTuvqTf11OY7t1fzO/P71NpVwBt2V3AvHU7mbtuO3PX7WDxhl0UlpQC0LFpGsN7NGdgpyakd2pCz1YN9HgMqXSxnIO4n2/mkk4C+gML4liTVCPFJaU8+GEWfdo25LReiXc3b1KS8ZcLjiOtVjKPfryGvYUl3PWD4yv8y7ik1Fm+aTdz1+9gXriHsD78MMHayUn0bd+Iq4d1ZmDHJgzs1JiWDfRIDAleLD2IyBl4ioHn3f2TONUj1cwbCzeydtteHr5yUEL1HiKZGb8+tzf16qQw8f2V7Csq4Z5L+1MrOZarwKPbVVDE/PU7mbsuFAjz1+8gPzwtavP6dUjv1IQrT+zEwE5NOK5dQ12FJAkploB4GShw9xIAM0s2szR317OUpVwlpc79H2TRq3UDzuzdKuhyymVm3HFmT9JqJ/PXt76koKiEBy4bSGqtQ39xuzvrtu0NnTcI9xCWb96NOyQZ9GrdkIsGtmdQpyYM6tSE9k3qJmxYikSKJSDeB84ADjw3uS4wHTgpXkVJ9fDfRV+xOjefhy4fWGXu7L3h1G6k1U7mt68v4don5/DIVemk1f72/00KikpYtOGbk8nz1u1gW34hAA1SUxjYsQnn9G3DoE5N6NehsWZrkyorln+5qe7+9UP13X2PmaXFsSapBkpLnfvfX0mPlvUZVcXmOr5yaGfq1k7h5y8v4Kp/f8H/XXx86PxBOBCWbMyjqCR0Wq5r83qM7NXy695B9xb1q0wYihxKLAGRb2YD3X0egJkNAvbFcnAzGwVMBJKBR939rij7jADuBWoBW9391FjbSuJ6e8kmVm7Zw31jB1TJL8yLB7Wnbq1kbpsyn9PvnglAnZQk+rVvzLUnd2VQpyYM7NiYZnq0hVRjsQTE7cBLZrYxvNyG0BSk5TKzZOBB4ExCl8bOMbNp7r40Yp/GwEPAKHdfb2YtY20riau01Lnv/ZV0bVGPc/u2CbqcI3bu8W1o3SiVRTk76d+xCce2aUjtlCM/cS1S1cRyo9wcM+sFHENoTuov3b0ohmMPBrLcfTWAmU0BRgORX/KXAa+6+/rwa205jLaSoN5dtpkvN+3mnkv7Vflr9w8MHYnURIf8c8jMxgP13H2xuy8C6pvZzTEcux2QHbGcE14XqSfQxMxmmNlcM7vqMNoeqG+cmWWYWUZubvV71n9V4x7qPXRulsb5x7cNuhwROQqx9Jevd/edBxbcfQdwfQztov3p6GWWU4BBwLnAWcBvzaxnjG0P1DPZ3dPdPb1Fi8R4jENN9sGXW1iycRfjR3Yn5SjuIxCR4MVyDiLJzMzdHb4+PxDLw2BygA4Ry+2BjVH22eru+YROhs8C+sXYVhLMgd5Dh6Z1uWBA1A6fiFQhsfyJ9w7wopmdbmanAc8Db8fQbg7Qw8y6mFltYAwwrcw+rwPDzSwlfOnsEGBZjG0lwcxckcuCnDzGj+h+VHchi0hiiKUH8QtgHHAToaGf6cAjh2rk7sVmNoFQwCQDj7n7EjO7Mbx9krsvM7O3gYVAKaHLWRcDRGt72O9OKo27M/H9lbRrXJeLBrYPuhwRqQAWHjmKvYHZycBYdx8fn5KOXHp6umdkZBx6R6lwH6/cyhX//pw/X3AcV5zYKehyRCRGZjbX3dOjbYvpGQBm1h8YS+j+hzXAqxVWnVR5od7DClo3TOWSdPUeRKqLgwZE+GqiMYSCYRvwAqEex8hKqk2qiM9Wb2fO2h388ft99FRSkWqkvB7El8BHwPnungVgZndUSlVSpdz3/kpaNKjDpSd0OPTOIlJllHepyQ+ATcCHZvaImZ1O9PsTpAb7Ys12Zq/exg2ndI3p0dgiUnUcNCDcfaq7Xwr0AmYAdwCtzOxfZva9SqpPEtz9H6ykef3aXD5EJ6ZFqptDXqzu7vnu/qy7n0fohrVM4M54FyaJb+66HXy0civXD+9K3drqPYhUN4d1N5O7b3f3h939tHgVJFXH/R+spElaLV3WKlJN6XZXOSILsncyY3ku1w3vSj3NmCZSLSkg5Ijc/8FKGtWtxVVD1XsQqa4UEHLYFm/I471lW7j25C40SK0VdDkiEicKCDls93+wkgapKfzopM5BlyIicaSAkMOy7KtdvLNkM9cM60Kjuuo9iFRnCgg5LA98kEX9Oin8eFjnoEsRkThTQEjMVmzezZuLv+JHJ3WicVosc0aJSFWmgJCYPfBBFnVrJXPtyV2DLkVEKoECQmKStWUPbyzcyJVDO9G0nnoPIjWBAkJi8tCHWdRJSeL64eo9iNQUCgg5pLVb83ktcwNXDOlE8/p1gi5HRCqJAkIO6aEZWdRKTmLcKeo9iNQkCggpV/b2vbw6bwNjB3ekZcPUoMsRkUoU14Aws1FmttzMsszsO48IN7MRZpZnZpnhn99FbFtrZovC6zPiWacc3EMzVpFkxo2ndgu6FBGpZHF7DKeZJQMPAmcCOcAcM5vm7kvL7PpReK6JaEa6+9Z41Sjl27BzHy/PzWbMCR1p3Ui9B5GaJp49iMFAlruvdvdCYAowOo6vJxVs0oxVANw4Qr0HkZoongHRDsiOWM4JrytrqJktMLO3zKxPxHoHppvZXDMbd7AXMbNxZpZhZhm5ubkVU7mwKa+AF+Zkc/GgDrRrXDfockQkAPGc6cWirPMyy/OATu6+x8zOAV4DeoS3DXP3jWbWEnjXzL5091nfOaD7ZGAyQHp6etnjyxGaNHMVpe7crN6DSI0Vzx5EDtAhYrk9sDFyB3ff5e57wr+/CdQys+bh5Y3h/24BphIaspJKsGVXAc9/sZ6LBrajQ9O0oMsRkYDEMyDmAD3MrIuZ1QbGANMidzCz1mZm4d8Hh+vZZmb1zKxBeH094HvA4jjWKhEmz1pNcakzfmT3oEsRkQDFbYjJ3YvNbALwDpAMPObuS8zsxvD2ScDFwE1mVgzsA8a4u5tZK2BqODtSgOfc/e141SrfWL5pN898vo7R/dvSqVm9oMsRkQCZe/UZtk9PT/eMDN0ycSQWZO/koRlZTF+6mXq1U3jjlpPp0lwBIVLdmdlcd0+Pti2eJ6klwbk7n67axkMzsvgkaxsNU1OYMLI7V5/UmWZ65pJIjaeAqIFKS513l23moRmrWJC9kxYN6vDLs3tx2ZCONEjVNKIiEqKAqEGKSkqZlrmRSTNXsXLLHjo0rcufLziOiwe1J7VWctDliUiCUUDUAAVFJbwwJ5vJs1azYec+erVuwMQx/Tm3bxtSkvW8RhGJTgFRjeXtK+KZz9bx2Mdr2JZfyKBOTfh/o/twWq+WhK8QExE5KAVENZS7ez+PfbKGZ2avY/f+Yk7p2YLxI7oxuEtTBYOIxEwBUY1kb9/L5FmreTEjm8KSUs45rg03jejGce0aBV2aiFRBCohqYMXm3fxrxiqmLdhIksFFA9pzw6ld6dqiftCliUgVpoCowuav38FDM1bx7tLN1K2VzNUndea64V1o00hPXxWRo6eAqGLcnY+ztvLQh6uYvXobjerW4tbTe3D1SZ1pWq920OWJSDWigKgiSkudd5Zs4qEZq1i0IY+WDerw63N6M3ZIR+rX0f+MIlLx9M2S4AqLS3ktcwOTZq5idW4+nZql8deL+nLRwHbUSdHNbSISPwqIBLWvsIQpc9bzyKzVbMwroHebhtw/dgDn9G1DcpIuVRWR+FNAJJi8vUU8NXstj3+6lu35hZzQuQl/ubAvI45poXsYRKRSKSASxL7CEu77YCVPz17Hnv3FjDymBTeP7M4JnZsGXZqI1FAKiASwKncP45+dx5ebdnPe8aGb2/q01c1tIhIsBUTA3liwkTtfWUjtlCSeuOYERhzTMuiSREQABURg9heX8Of/LOPpz9YxqFMT7h87gLaNdYObiCQOBUQAsrfv5eZn57FoQx7XD+/Cz0f1opYeuy0iCUYBUcneXbqZn76YiQMPXzmIs/q0DrokEZGo4vpnq5mNMrPlZpZlZndG2T7CzPLMLDP887tY21Y1RSWl/O+by7j+qQw6Nkvjv7cMVziISEKLWw/CzJKBB4EzgRxgjplNc/elZXb9yN3PO8K2VcJXefuY8Nx85q7bwZUnduLX5/bWFJ8ikvDiOcQ0GMhy99UAZjYFGA3E8iV/NG0TyqwVudz+QiYFRSVMHNOf0f3bBV2SiEhM4jnE1A7IjljOCa8ra6iZLTCzt8ysz2G2xczGmVmGmWXk5uZWRN0VoqTU+ef05fzo8S9oUb8O0yacrHAQkSolnj2IaM+F8DLL84BO7r7HzM4BXgN6xNg2tNJ9MjAZID09Peo+lS13935umzKfT1dt4+JB7fnT6OOoW1tDSiJStcQzIHKADhHL7YGNkTu4+66I3980s4fMrHksbRPVZ6u3ccvz89m1r4i/XXw8P0zvcOhGIiIJKJ4BMQfoYWZdgA3AGOCyyB3MrDWw2d3dzAYTGvLaBuw8VNtEU1rq/GvmKu6evpzOzerx1I8H07tNw6DLEhE5YnELCHcvNrMJwDtAMvCYuy8xsxvD2ycBFwM3mVkxsA8Y4+4ORG0br1qP1o78Qn7yYiYfLs/l3OPbcNdFfWmQWivoskREjoqFvo+rh/T0dM/IyKjU15y/fgcTnptP7u79/Pa83lxxYic9lltEqgwzm+vu6dG26U7qI+TuPP7JWv761jJaNUzl5ZuGcnz7xkGXJSJSYRQQR2BXQRG/eHkhby3exBm9W3H3Jf1olKYhJRGpXhQQh2nxhjzGPzePnB37+NU5vbh+eFcNKYlItaSAiJG78/wX2fzhjSU0TavNC+NOJF2zvYlINaaAiEH+/mJ+89pips7fwPAezbn30v40q18n6LJEROJKAXEIKzfv5qZn57Eqdw8/ObMn40d2JzlJQ0oiUv0pIMrx6rwcfj11MfXqJPPMtUMY1r150CWJiFQaBUQUBUUl/PGNJTz/RTaDuzTlgbEDaNkwNeiyREQqlQKijLVb87n52Xks/WoXN4/oxk/O7EmKpgMVkRpIARHhrUVf8bOXF5KcZDx2dTqn9WoVdEkiIoFRQACFxaX89a1lPP7JWvp3aMwDlw2gfZO0oMsSEQlUjQ+IvL1FXPX4FyzI3smPh3XhzrN7UTtFQ0oiIjU+IBqkptCpaRo3ntKVs/u2CbocEZGEUeMDIinJuG/sgKDLEBFJOBpLERGRqBQQIiISlQJCRESiUkCIiEhUCggREYlKASEiIlEpIEREJCoFhIiIRGXuHnQNFcbMcoF1R9i8ObC1AsupyvRZfJs+j2/T5/GN6vBZdHL3FtE2VKuAOBpmluHu6UHXkQj0WXybPo9v0+fxjer+WWiISUREolJAiIhIVAqIb0wOuoAEos/i2/R5fJs+j29U689C5yBERCQq9SBERCQqBYSIiERV4wPCzEaZ2XIzyzKzO4OuJ0hm1sHMPjSzZWa2xMxuC7qmoJlZspnNN7P/BF1L0MyssZm9bGZfhv+NDA26piCZ2R3h/58sNrPnzSw16JoqWo0OCDNLBh4EzgaOBcaa2bHBVhWoYuCn7t4bOBEYX8M/D4DbgGVBF5EgJgJvu3svoB81+HMxs3bArUC6ux8HJANjgq2q4tXogAAGA1nuvtrdC4EpwOiAawqMu3/l7vPCv+8m9AXQLtiqgmNm7YFzgUeDriVoZtYQOAX4N4C7F7r7zkCLCl4KUNfMUoA0YGPA9VS4mh4Q7YDsiOUcavAXYiQz6wwMAD4PuJQg3Qv8HCgNuI5E0BXIBR4PD7k9amb1gi4qKO6+AfgHsB74Cshz9+nBVlXxanpAWJR1Nf66XzOrD7wC3O7uu4KuJwhmdh6wxd3nBl1LgkgBBgL/cvcBQD5QY8/ZmVkTQqMNXYC2QD0zuyLYqipeTQ+IHKBDxHJ7qmE38XCYWS1C4fCsu78adD0BGgZ838zWEhp6PM3Mngm2pEDlADnufqBH+TKhwKipzgDWuHuuuxcBrwInBVxThavpATEH6GFmXcysNqGTTNMCrikwZmaExpiXufs/g64nSO7+S3dv7+6dCf27+MDdq91fiLFy901AtpkdE151OrA0wJKCth440czSwv+/OZ1qeNI+JegCguTuxWY2AXiH0FUIj7n7koDLCtIw4EpgkZllhtf9yt3fDK4kSSC3AM+G/5haDVwTcD2BcffPzexlYB6hq//mUw0fu6FHbYiISFQ1fYhJREQOQgEhIiJRKSBERCQqBYSIiESlgBARkagUECJhZrYn/N/OZnZZBR/7V2WWP63I44vEgwJC5Ls6A4cVEOEnA5fnWwHh7tXurlupfhQQIt91FzDczDLDz/xPNrO/m9kcM1toZjcAmNmI8PwZzwGLwuteM7O54XkCxoXX3UXoqZ+ZZvZseN2B3oqFj73YzBaZ2aURx54RMf/Cs+E7djGzu8xsabiWf1T6pyM1Ro2+k1rkIO4E/sfdzwMIf9HnufsJZlYH+MTMDjy5czBwnLuvCS//2N23m1ldYI6ZveLud5rZBHfvH+W1LgL6E5pfoXm4zazwtgFAH0LPB/sEGGZmS4ELgV7u7mbWuGLfusg31IMQObTvAVeFHz/yOdAM6BHe9kVEOADcamYLgM8IPQiyB+U7GXje3UvcfTMwEzgh4tg57l4KZBIa+toFFACPmtlFwN6jfG8iB6WAEDk0A25x9/7hny4Rz/7P/3onsxGEnvI51N37EXo+z6GmoYz2yPkD9kf8XgKkuHsxoV7LK8AFwNuH8T5EDosCQuS7dgMNIpbfAW4KPwodM+t5kMlyGgE73H2vmfUiNG3rAUUH2pcxC7g0fJ6jBaFZ2744WGHhuToahR+geDuh4SmRuNA5CJHvWggUh4eKniA0F3NnYF74RHEuob/ey3obuNHMFgLLCQ0zHTAZWGhm89z98oj1U4GhwAJCk1X93N03hQMmmgbA62aWSqj3cccRvUORGOhpriIiEpWGmEREJCoFhIiIRKWAEBGRqBQQIiISlQJCRESiUkCIiEhUCggREYnq/wPNsrzQPvNmRgAAAABJRU5ErkJggg==\n",
- "text/plain": [
- "<Figure size 432x288 with 1 Axes>"
- ]
- },
- "metadata": {
- "needs_background": "light"
- },
- "output_type": "display_data"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"acc_per_epoch = [np.mean(acc_per_epoch) for acc_per_epoch in running_test_acc]\n",
"display_loss_plot(acc_per_epoch, title=\"Test accuracy\", ylabel=\"Accuracy [%]\")"
@@ -505,27 +450,16 @@
},
{
"cell_type": "code",
- "execution_count": 16,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "0.8091021716950881"
- ]
- },
- "execution_count": 16,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"test(model, test_quantized_loader)"
]
},
{
"cell_type": "code",
- "execution_count": 17,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -544,20 +478,9 @@
},
{
"cell_type": "code",
- "execution_count": 18,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "<All keys matched successfully>"
- ]
- },
- "execution_count": 18,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import torch\n",
"\n",
@@ -572,22 +495,9 @@
},
{
"cell_type": "code",
- "execution_count": 19,
- "metadata": {
- "scrolled": true
- },
- "outputs": [
- {
- "data": {
- "text/plain": [
- "0.9188772287810328"
- ]
- },
- "execution_count": 19,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"# Move the model back to it's target device\n",
"model.to(device)\n",
@@ -614,7 +524,7 @@
},
{
"cell_type": "code",
- "execution_count": 20,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -631,20 +541,9 @@
},
{
"cell_type": "code",
- "execution_count": 21,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "(64, 593)"
- ]
- },
- "execution_count": 21,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"from copy import deepcopy\n",
"\n",
@@ -656,20 +555,9 @@
},
{
"cell_type": "code",
- "execution_count": 22,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "(64, 600)"
- ]
- },
- "execution_count": 22,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import numpy as np\n",
"\n",
@@ -680,20 +568,9 @@
},
{
"cell_type": "code",
- "execution_count": 23,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "torch.Size([64, 600])"
- ]
- },
- "execution_count": 23,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"modified_model[0].weight.data = torch.from_numpy(W_new)\n",
"modified_model[0].weight.shape"
@@ -743,7 +620,7 @@
},
{
"cell_type": "code",
- "execution_count": 25,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -774,20 +651,9 @@
},
{
"cell_type": "code",
- "execution_count": 26,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "0.9188772287810328"
- ]
- },
- "execution_count": 26,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"test_padded_bipolar(model_for_export, test_quantized_loader)"
]
@@ -806,19 +672,9 @@
},
{
"cell_type": "code",
- "execution_count": 27,
- "metadata": {
- "scrolled": true
- },
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Model saved to cybsec-mlp-ready.onnx\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"import brevitas.onnx as bo\n",
"from brevitas.quant_tensor import QuantTensor\n",
diff --git a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb
index a0fef1ab6..07c8dbb1b 100644
--- a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb
+++ b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb
@@ -20,7 +20,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -58,7 +58,7 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -77,85 +77,9 @@
},
{
"cell_type": "code",
- "execution_count": 3,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "['__class__',\n",
- " '__delattr__',\n",
- " '__dict__',\n",
- " '__dir__',\n",
- " '__doc__',\n",
- " '__eq__',\n",
- " '__format__',\n",
- " '__ge__',\n",
- " '__getattribute__',\n",
- " '__gt__',\n",
- " '__hash__',\n",
- " '__init__',\n",
- " '__init_subclass__',\n",
- " '__le__',\n",
- " '__lt__',\n",
- " '__module__',\n",
- " '__ne__',\n",
- " '__new__',\n",
- " '__reduce__',\n",
- " '__reduce_ex__',\n",
- " '__repr__',\n",
- " '__setattr__',\n",
- " '__sizeof__',\n",
- " '__str__',\n",
- " '__subclasshook__',\n",
- " '__weakref__',\n",
- " '_model_proto',\n",
- " 'analysis',\n",
- " 'check_all_tensor_shapes_specified',\n",
- " 'check_compatibility',\n",
- " 'cleanup',\n",
- " 'find_consumer',\n",
- " 'find_consumers',\n",
- " 'find_direct_predecessors',\n",
- " 'find_direct_successors',\n",
- " 'find_producer',\n",
- " 'find_upstream',\n",
- " 'get_all_tensor_names',\n",
- " 'get_finn_nodes',\n",
- " 'get_initializer',\n",
- " 'get_metadata_prop',\n",
- " 'get_node_index',\n",
- " 'get_nodes_by_op_type',\n",
- " 'get_non_finn_nodes',\n",
- " 'get_tensor_datatype',\n",
- " 'get_tensor_fanout',\n",
- " 'get_tensor_layout',\n",
- " 'get_tensor_shape',\n",
- " 'get_tensor_sparsity',\n",
- " 'get_tensor_valueinfo',\n",
- " 'graph',\n",
- " 'is_fork_node',\n",
- " 'is_join_node',\n",
- " 'make_empty_exec_context',\n",
- " 'make_new_valueinfo_name',\n",
- " 'model',\n",
- " 'rename_tensor',\n",
- " 'save',\n",
- " 'set_initializer',\n",
- " 'set_metadata_prop',\n",
- " 'set_tensor_datatype',\n",
- " 'set_tensor_layout',\n",
- " 'set_tensor_shape',\n",
- " 'set_tensor_sparsity',\n",
- " 'temporary_fix_oldstyle_domain',\n",
- " 'transform']"
- ]
- },
- "execution_count": 3,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"dir(model_for_sim)"
]
@@ -169,24 +93,9 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Input tensor name: 0\n",
- "Output tensor name: 73\n",
- "Input tensor shape: [1, 600]\n",
- "Output tensor shape: [1, 1]\n",
- "Input tensor datatype: BIPOLAR\n",
- "Output tensor datatype: FLOAT32\n",
- "List of node operator types in the graph: \n",
- "['Mul', 'Add', 'Div', 'MatMul', 'Mul', 'Add', 'BatchNormalization', 'MultiThreshold', 'Mul', 'MatMul', 'Mul', 'Add', 'BatchNormalization', 'MultiThreshold', 'Mul', 'MatMul', 'Mul', 'Add', 'BatchNormalization', 'MultiThreshold', 'Mul', 'MatMul', 'Mul', 'Add', 'MultiThreshold']\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"from finn.core.datatype import DataType\n",
"\n",
@@ -226,7 +135,7 @@
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -262,38 +171,9 @@
},
{
"cell_type": "code",
- "execution_count": 7,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Serving 'cybsec-mlp-verification.onnx' at http://0.0.0.0:8081\n"
- ]
- },
- {
- "data": {
- "text/html": [
- "\n",
- " <iframe\n",
- " width=\"100%\"\n",
- " height=\"400\"\n",
- " src=\"http://localhost:8081/\"\n",
- " frameborder=\"0\"\n",
- " allowfullscreen\n",
- " ></iframe>\n",
- " "
- ],
- "text/plain": [
- "<IPython.lib.display.IFrame at 0x7f3be619b2b0>"
- ]
- },
- "execution_count": 7,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"from finn.util.visualization import showInNetron\n",
"\n",
@@ -311,20 +191,9 @@
},
{
"cell_type": "code",
- "execution_count": 8,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "torch.Size([100, 593])"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"import numpy as np\n",
"from torch.utils.data import TensorDataset\n",
@@ -356,20 +225,9 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "<All keys matched successfully>"
- ]
- },
- "execution_count": 9,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "outputs": [],
"source": [
"input_size = 593 \n",
"hidden1 = 64 \n",
@@ -409,7 +267,7 @@
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -441,7 +299,7 @@
},
{
"cell_type": "code",
- "execution_count": 11,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -476,17 +334,9 @@
},
{
"cell_type": "code",
- "execution_count": 12,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stderr",
- "output_type": "stream",
- "text": [
- "ok 100 nok 0: 100%|██████████| 100/100 [00:21<00:00, 4.72it/s]\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"import numpy as np\n",
"from tqdm import trange\n",
@@ -511,17 +361,9 @@
},
{
"cell_type": "code",
- "execution_count": 13,
+ "execution_count": null,
"metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Verification succeeded. Brevitas and FINN-ONNX execution outputs are identical\n"
- ]
- }
- ],
+ "outputs": [],
"source": [
"if ok == n_verification_inputs:\n",
" print(\"Verification succeeded. Brevitas and FINN-ONNX execution outputs are identical\")\n",
diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
index 5221c69f6..980a770fe 100644
--- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
+++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
@@ -106,7 +106,7 @@
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -140,41 +140,9 @@
},
{
"cell_type": "code",
- "execution_count": 2,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Building dataflow accelerator from cybsec-mlp-ready.onnx\n",
- "Intermediate outputs will be generated in /scratch/users/mirzam/build_files\n",
- "Final outputs will be generated in output_estimates_only\n",
- "Build log is at output_estimates_only/build_dataflow.log\n",
- "Running step: step_qonnx_to_finn [1/8]\n",
- "Running step: step_tidy_up [2/8]\n",
- "Running step: step_streamline [3/8]\n",
- "Running step: step_convert_to_hls [4/8]\n",
- "Running step: step_create_dataflow_partition [5/8]\n",
- "Running step: step_target_fps_parallelization [6/8]\n",
- "Running step: step_apply_folding_config [7/8]\n",
- "Running step: step_generate_estimate_reports [8/8]\n",
- "Completed successfully\n",
- "CPU times: user 3.41 s, sys: 2.49 s, total: 5.91 s\n",
- "Wall time: 2.07 s\n"
- ]
- },
- {
- "data": {
- "text/plain": [
- "0"
- ]
- },
- "execution_count": 2,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"%%time\n",
"build.build_dataflow_cfg(model_file, cfg_estimates)"
@@ -189,37 +157,18 @@
},
{
"cell_type": "code",
- "execution_count": 3,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "auto_folding_config.json intermediate_models time_per_step.json\r\n",
- "build_dataflow.log\t report\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ls {estimates_output_dir}"
]
},
{
"cell_type": "code",
- "execution_count": 4,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "estimate_layer_config_alternatives.json estimate_network_performance.json\r\n",
- "estimate_layer_cycles.json\t\t op_and_param_counts.json\r\n",
- "estimate_layer_resources.json\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ls {estimates_output_dir}/report"
]
@@ -233,23 +182,9 @@
},
{
"cell_type": "code",
- "execution_count": 5,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "{\r\n",
- " \"critical_path_cycles\": 252,\r\n",
- " \"max_cycles\": 64,\r\n",
- " \"max_cycles_node_name\": \"MatrixVectorActivation_1\",\r\n",
- " \"estimated_throughput_fps\": 1562500.0,\r\n",
- " \"estimated_latency_ns\": 2520.0\r\n",
- "}"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! cat {estimates_output_dir}/report/estimate_network_performance.json"
]
@@ -263,7 +198,7 @@
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -276,23 +211,9 @@
},
{
"cell_type": "code",
- "execution_count": 7,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "{'MatrixVectorActivation_0': 60,\n",
- " 'MatrixVectorActivation_1': 64,\n",
- " 'MatrixVectorActivation_2': 64,\n",
- " 'MatrixVectorActivation_3': 64}"
- ]
- },
- "execution_count": 7,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"read_json_dict(estimates_output_dir + \"/report/estimate_layer_cycles.json\")"
]
@@ -308,44 +229,9 @@
},
{
"cell_type": "code",
- "execution_count": 8,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "{'MatrixVectorActivation_0': {'BRAM_18K': 36,\n",
- " 'BRAM_efficiency': 0.11574074074074074,\n",
- " 'LUT': 8184,\n",
- " 'URAM': 0,\n",
- " 'URAM_efficiency': 1,\n",
- " 'DSP': 0},\n",
- " 'MatrixVectorActivation_1': {'BRAM_18K': 4,\n",
- " 'BRAM_efficiency': 0.1111111111111111,\n",
- " 'LUT': 1217,\n",
- " 'URAM': 0,\n",
- " 'URAM_efficiency': 1,\n",
- " 'DSP': 0},\n",
- " 'MatrixVectorActivation_2': {'BRAM_18K': 4,\n",
- " 'BRAM_efficiency': 0.1111111111111111,\n",
- " 'LUT': 1217,\n",
- " 'URAM': 0,\n",
- " 'URAM_efficiency': 1,\n",
- " 'DSP': 0},\n",
- " 'MatrixVectorActivation_3': {'BRAM_18K': 1,\n",
- " 'BRAM_efficiency': 0.006944444444444444,\n",
- " 'LUT': 341,\n",
- " 'URAM': 0,\n",
- " 'URAM_efficiency': 1,\n",
- " 'DSP': 0},\n",
- " 'total': {'BRAM_18K': 45.0, 'LUT': 10959.0, 'URAM': 0.0, 'DSP': 0.0}}"
- ]
- },
- "execution_count": 8,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"read_json_dict(estimates_output_dir + \"/report/estimate_layer_resources.json\")"
]
@@ -377,7 +263,7 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -411,50 +297,9 @@
},
{
"cell_type": "code",
- "execution_count": 10,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Building dataflow accelerator from cybsec-mlp-ready.onnx\n",
- "Intermediate outputs will be generated in /scratch/users/mirzam/build_files\n",
- "Final outputs will be generated in output_ipstitch_ooc_rtlsim\n",
- "Build log is at output_ipstitch_ooc_rtlsim/build_dataflow.log\n",
- "Running step: step_qonnx_to_finn [1/17]\n",
- "Running step: step_tidy_up [2/17]\n",
- "Running step: step_streamline [3/17]\n",
- "Running step: step_convert_to_hls [4/17]\n",
- "Running step: step_create_dataflow_partition [5/17]\n",
- "Running step: step_target_fps_parallelization [6/17]\n",
- "Running step: step_apply_folding_config [7/17]\n",
- "Running step: step_generate_estimate_reports [8/17]\n",
- "Running step: step_hls_codegen [9/17]\n",
- "Running step: step_hls_ipgen [10/17]\n",
- "Running step: step_set_fifo_depths [11/17]\n",
- "Running step: step_create_stitched_ip [12/17]\n",
- "Running step: step_measure_rtlsim_performance [13/17]\n",
- "Running step: step_out_of_context_synthesis [14/17]\n",
- "Running step: step_synthesize_bitfile [15/17]\n",
- "Running step: step_make_pynq_driver [16/17]\n",
- "Running step: step_deployment_package [17/17]\n",
- "Completed successfully\n",
- "CPU times: user 7.89 s, sys: 1.84 s, total: 9.73 s\n",
- "Wall time: 13min 18s\n"
- ]
- },
- {
- "data": {
- "text/plain": [
- "0"
- ]
- },
- "execution_count": 10,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"%%time\n",
"build.build_dataflow_cfg(model_file, cfg_stitched_ip)"
@@ -476,23 +321,9 @@
},
{
"cell_type": "code",
- "execution_count": 11,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "all_verilog_srcs.txt\t\t finn_vivado_stitch_proj.xpr\r\n",
- "data\t\t\t\t ip\r\n",
- "finn_vivado_stitch_proj.cache\t make_project.sh\r\n",
- "finn_vivado_stitch_proj.gen\t make_project.tcl\r\n",
- "finn_vivado_stitch_proj.hw\t vivado.jou\r\n",
- "finn_vivado_stitch_proj.ip_user_files vivado.log\r\n",
- "finn_vivado_stitch_proj.srcs\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ls {rtlsim_output_dir}/stitched_ip"
]
@@ -506,18 +337,9 @@
},
{
"cell_type": "code",
- "execution_count": 12,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "estimate_layer_resources_hls.json rtlsim_performance.json\r\n",
- "ooc_synth_and_timing.json\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! ls {rtlsim_output_dir}/report"
]
@@ -531,35 +353,9 @@
},
{
"cell_type": "code",
- "execution_count": 13,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "{\r\n",
- " \"vivado_proj_folder\": \"/scratch/users/mirzam/build_files/synth_out_of_context_ltsrdo5z/results_finn_design_wrapper\",\r\n",
- " \"LUT\": 7234.0,\r\n",
- " \"LUTRAM\": 44.0,\r\n",
- " \"FF\": 10233.0,\r\n",
- " \"DSP\": 0.0,\r\n",
- " \"BRAM\": 22.0,\r\n",
- " \"BRAM_18K\": 0.0,\r\n",
- " \"BRAM_36K\": 22.0,\r\n",
- " \"URAM\": 0.0,\r\n",
- " \"Carry\": 339.0,\r\n",
- " \"WNS\": 0.712,\r\n",
- " \"Delay\": 0.712,\r\n",
- " \"vivado_version\": 2022.1,\r\n",
- " \"vivado_build_no\": 3526262.0,\r\n",
- " \"\": 0,\r\n",
- " \"fmax_mhz\": 107.66580534022394,\r\n",
- " \"estimated_throughput_fps\": 1682278.208440999\r\n",
- "}"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! cat {rtlsim_output_dir}/report/ooc_synth_and_timing.json"
]
@@ -573,26 +369,9 @@
},
{
"cell_type": "code",
- "execution_count": 14,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "{\r\n",
- " \"cycles\": 213,\r\n",
- " \"runtime[ms]\": 0.00213,\r\n",
- " \"throughput[images/s]\": 469483.56807511736,\r\n",
- " \"DRAM_in_bandwidth[Mb/s]\": 35.2112676056338,\r\n",
- " \"DRAM_out_bandwidth[Mb/s]\": 0.05868544600938967,\r\n",
- " \"fclk[mhz]\": 100.0,\r\n",
- " \"N\": 1,\r\n",
- " \"latency_cycles\": 213\r\n",
- "}"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! cat {rtlsim_output_dir}/report/rtlsim_performance.json"
]
@@ -606,62 +385,9 @@
},
{
"cell_type": "code",
- "execution_count": 15,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "{\r\n",
- " \"Defaults\": {},\r\n",
- " \"StreamingFIFO_0\": {\r\n",
- " \"ram_style\": \"auto\",\r\n",
- " \"depth\": 32,\r\n",
- " \"impl_style\": \"rtl\"\r\n",
- " },\r\n",
- " \"MatrixVectorActivation_0\": {\r\n",
- " \"PE\": 16,\r\n",
- " \"SIMD\": 40,\r\n",
- " \"ram_style\": \"auto\",\r\n",
- " \"resType\": \"lut\",\r\n",
- " \"mem_mode\": \"decoupled\",\r\n",
- " \"runtime_writeable_weights\": 0\r\n",
- " },\r\n",
- " \"StreamingDataWidthConverter_Batch_0\": {\r\n",
- " \"impl_style\": \"hls\"\r\n",
- " },\r\n",
- " \"MatrixVectorActivation_1\": {\r\n",
- " \"PE\": 1,\r\n",
- " \"SIMD\": 64,\r\n",
- " \"ram_style\": \"auto\",\r\n",
- " \"resType\": \"lut\",\r\n",
- " \"mem_mode\": \"decoupled\",\r\n",
- " \"runtime_writeable_weights\": 0\r\n",
- " },\r\n",
- " \"StreamingDataWidthConverter_Batch_1\": {\r\n",
- " \"impl_style\": \"hls\"\r\n",
- " },\r\n",
- " \"MatrixVectorActivation_2\": {\r\n",
- " \"PE\": 1,\r\n",
- " \"SIMD\": 64,\r\n",
- " \"ram_style\": \"auto\",\r\n",
- " \"resType\": \"lut\",\r\n",
- " \"mem_mode\": \"decoupled\",\r\n",
- " \"runtime_writeable_weights\": 0\r\n",
- " },\r\n",
- " \"MatrixVectorActivation_3\": {\r\n",
- " \"PE\": 1,\r\n",
- " \"SIMD\": 1,\r\n",
- " \"ram_style\": \"auto\",\r\n",
- " \"resType\": \"lut\",\r\n",
- " \"mem_mode\": \"decoupled\",\r\n",
- " \"runtime_writeable_weights\": 0\r\n",
- " }\r\n",
- "}"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"! cat {rtlsim_output_dir}/final_hw_config.json"
]
@@ -677,7 +403,7 @@
},
{
"cell_type": "code",
- "execution_count": 17,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -712,49 +438,9 @@
},
{
"cell_type": "code",
- "execution_count": 18,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "Building dataflow accelerator from cybsec-mlp-ready.onnx\n",
- "Intermediate outputs will be generated in /tmp/finn_dev_ubuntu\n",
- "Final outputs will be generated in output_final\n",
- "Build log is at output_final/build_dataflow.log\n",
- "Running step: step_tidy_up [1/16]\n",
- "Running step: step_streamline [2/16]\n",
- "Running step: step_convert_to_hls [3/16]\n",
- "Running step: step_create_dataflow_partition [4/16]\n",
- "Running step: step_target_fps_parallelization [5/16]\n",
- "Running step: step_apply_folding_config [6/16]\n",
- "Running step: step_generate_estimate_reports [7/16]\n",
- "Running step: step_hls_codegen [8/16]\n",
- "Running step: step_hls_ipgen [9/16]\n",
- "Running step: step_set_fifo_depths [10/16]\n",
- "Running step: step_create_stitched_ip [11/16]\n",
- "Running step: step_measure_rtlsim_performance [12/16]\n",
- "Running step: step_make_pynq_driver [13/16]\n",
- "Running step: step_out_of_context_synthesis [14/16]\n",
- "Running step: step_synthesize_bitfile [15/16]\n",
- "Running step: step_deployment_package [16/16]\n",
- "Completed successfully\n",
- "CPU times: user 4.47 s, sys: 766 ms, total: 5.24 s\n",
- "Wall time: 22min 13s\n"
- ]
- },
- {
- "data": {
- "text/plain": [
- "0"
- ]
- },
- "execution_count": 18,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"#%%time\n",
"#build.build_dataflow_cfg(model_file, cfg)"
@@ -769,17 +455,9 @@
},
{
"cell_type": "code",
- "execution_count": 19,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "finn-accel.bit\tfinn-accel.hwh\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"#! ls {final_output_dir}/bitfile"
]
@@ -793,17 +471,9 @@
},
{
"cell_type": "code",
- "execution_count": 20,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "driver.py driver_base.py finn runtime_weights validate.py\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"#! ls {final_output_dir}/driver"
]
@@ -817,18 +487,9 @@
},
{
"cell_type": "code",
- "execution_count": 21,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "estimate_layer_resources_hls.json post_synth_resources.xml\r\n",
- "post_route_timing.rpt\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"#! ls {final_output_dir}/report"
]
@@ -842,17 +503,9 @@
},
{
"cell_type": "code",
- "execution_count": 22,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "bitfile driver\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"#! ls {final_output_dir}/deploy"
]
@@ -870,7 +523,7 @@
},
{
"cell_type": "code",
- "execution_count": 23,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -879,7 +532,7 @@
},
{
"cell_type": "code",
- "execution_count": 24,
+ "execution_count": null,
"metadata": {},
"outputs": [],
"source": [
@@ -888,38 +541,18 @@
},
{
"cell_type": "code",
- "execution_count": 25,
- "metadata": {},
- "outputs": [
- {
- "name": "stdout",
- "output_type": "stream",
- "text": [
- "driver.py\tfinn\t\t unsw_nb15_binarized.npz validate.py\r\n",
- "driver_base.py\truntime_weights validate-unsw-nb15.py\r\n"
- ]
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"#! ls {final_output_dir}/deploy/driver"
]
},
{
"cell_type": "code",
- "execution_count": 26,
- "metadata": {},
- "outputs": [
- {
- "data": {
- "text/plain": [
- "'/workspace/finn/notebooks/end2end_example/cybersecurity/deploy-on-pynq.zip'"
- ]
- },
- "execution_count": 26,
- "metadata": {},
- "output_type": "execute_result"
- }
- ],
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
"source": [
"#from shutil import make_archive\n",
"#make_archive('deploy-on-pynq', 'zip', final_output_dir+\"/deploy\")"
--
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