From e73a07190cdbe690a46136c603421b1d3dba8efb Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Fri, 19 Aug 2022 14:31:51 +0100
Subject: [PATCH] [IP stitch] make new lookup layer output external
---
src/finn/custom_op/fpgadataflow/lookup.py | 13 +++++++++----
.../fpgadataflow/create_stitched_ip.py | 17 +++++++++++++++++
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py
index 6425edd56..31344c9f1 100644
--- a/src/finn/custom_op/fpgadataflow/lookup.py
+++ b/src/finn/custom_op/fpgadataflow/lookup.py
@@ -279,7 +279,8 @@ class Lookup(HLSCustomOp):
"void "
+ self.onnx_node.name
+ "(hls::stream<T_SRC> &in0, hls::stream<T_DST> &out, "
- + "T_DST const *const mem, unsigned const size, unsigned &oob_count, bool &oob_irq)"
+ + "T_DST const *const mem, unsigned const size, "
+ + "unsigned &oob_count, bool &oob_irq)"
]
def pragmas(self):
@@ -298,8 +299,12 @@ class Lookup(HLSCustomOp):
elif mem_mode == "external":
my_pragmas.append("#pragma HLS INTERFACE m_axi offset=slave port=mem")
my_pragmas.append("#pragma HLS INTERFACE s_axilite port=mem bundle=control")
- my_pragmas.append("#pragma HLS INTERFACE s_axilite port=size bundle=control")
- my_pragmas.append("#pragma HLS INTERFACE s_axilite port=oob_count bundle=control")
+ my_pragmas.append(
+ "#pragma HLS INTERFACE s_axilite port=size bundle=control"
+ )
+ my_pragmas.append(
+ "#pragma HLS INTERFACE s_axilite port=oob_count bundle=control"
+ )
my_pragmas.append("#pragma HLS INTERFACE ap_none port=oob_irq")
else:
raise Exception("Unrecognized mem_mode: " + mem_mode)
@@ -471,5 +476,5 @@ class Lookup(HLSCustomOp):
if mem_mode == "external":
intf_names["axilite"] = ["s_axi_control"]
intf_names["aximm"] = [("m_axi_gmem", self.get_nodeattr("ext_mem_width"))]
- intf_names["oob_irq"] = ["ap_none"]
+ intf_names["ap_none"] = ["oob_irq"]
return intf_names
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 892ab09fd..5b0b0cb60 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -228,6 +228,22 @@ class CreateStitchedIP(Transformation):
)
self.s_axis_idx += 1
+ def connect_ap_none_external(self, node):
+ inst_name = node.name
+ node_inst = getCustomOp(node)
+ input_intf_names = node_inst.get_verilog_top_module_intf_names()["ap_none"]
+ # make external
+ for i in range(len(input_intf_names)):
+ input_intf_name = input_intf_names[i]
+ self.connect_cmds.append(
+ "make_bd_pins_external [get_bd_pins %s/%s]"
+ % (inst_name, input_intf_name)
+ )
+ self.connect_cmds.append(
+ "set_property name %s [get_bd_ports %s_0]"
+ % (input_intf_name, input_intf_name)
+ )
+
def insert_signature(self, checksum_count):
signature_vlnv = "AMD:user:axi_info_top:1.0"
signature_name = "axi_info_top0"
@@ -305,6 +321,7 @@ class CreateStitchedIP(Transformation):
ip_dirs += [ip_dir_value]
self.create_cmds += node_inst.code_generation_ipi()
self.connect_clk_rst(node)
+ self.connect_ap_none_external(node)
self.connect_axi(node)
for i in range(len(node.input)):
if not is_external_input(model, node, i):
--
GitLab