diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn
index 850d637de4d1384231a90dc5cdca532cb4dec5fd..41f10cb5c161ff8e2b8875ba471568cc9d2db91a 100644
--- a/docker/Dockerfile.finn
+++ b/docker/Dockerfile.finn
@@ -28,10 +28,6 @@
FROM pytorch/pytorch:1.7.1-cuda11.0-cudnn8-runtime
LABEL maintainer="Yaman Umuroglu <yamanu@xilinx.com>"
-
-# XRT version to be installed
-ARG XRT_DEB_VERSION="xrt_202010.2.7.766_18.04-amd64-xrt"
-
WORKDIR /workspace
# some Vitis deps require a timezone to be specified, which hangs in Docker
@@ -64,6 +60,7 @@ RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config
RUN locale-gen "en_US.UTF-8"
# install XRT
+ARG XRT_DEB_VERSION
RUN wget https://www.xilinx.com/bin/public/openDownload?filename=$XRT_DEB_VERSION.deb -O /tmp/$XRT_DEB_VERSION.deb
RUN apt install -y /tmp/$XRT_DEB_VERSION.deb
RUN rm /tmp/$XRT_DEB_VERSION.deb
diff --git a/docs/finn/getting_started.rst b/docs/finn/getting_started.rst
index 8a8a803a3d9c2a0bc780e8fd6b33cd20060a28a6..40425c119fafdcd03292b05c7a7e71310f767239 100644
--- a/docs/finn/getting_started.rst
+++ b/docs/finn/getting_started.rst
@@ -143,7 +143,7 @@ Supported FPGA Hardware
**Shell-integrated accelerator + driver:** For quick deployment, we target boards supported by `PYNQ <http://www.pynq.io/>`_ . For these platforms, we can build a full bitfile including DMAs to move data into and out of the FINN-generated accelerator, as well as a Python driver to launch the accelerator. We support the Pynq-Z1, Pynq-Z2, Ultra96, ZCU102 and ZCU104 boards.
.. warning::
- In previous FINN versions (v0.4b - v0.7) we had preliminary support for `Xilinx Alveo boards <https://www.xilinx.com/products/boards-and-kits/alveo.html>`_ using PYNQ and Vitis 2020.1, see instructions below for Alveo setup that works with older versions. Please note that with the new release with Vitis 2022.1, we do not have support for an automatic deployment on Alveo cards.
+ In previous FINN versions (v0.4b - v0.7) we had support for `Xilinx Alveo boards <https://www.xilinx.com/products/boards-and-kits/alveo.html>`_ using PYNQ and Vitis 2020.1, see instructions below for Alveo setup that works with older versions. Please note that with the new release with Vitis 2022.1, we do only have experimental support to automatically deployment for Alveo cards.
**Vivado IPI support for any Xilinx FPGA:** FINN generates a Vivado IP Integrator (IPI) design from the neural network with AXI stream (FIFO) in-out interfaces, which can be integrated onto any Xilinx FPGA as part of a larger system. It's up to you to take the FINN-generated accelerator (what we call "stitched IP" in the tutorials), wire it up to your FPGA design and send/receive neural network data to/from the accelerator.
@@ -167,9 +167,6 @@ Continue on the host side (replace the ``<PYNQ_IP>`` and ``<PYNQ_USERNAME>`` wit
Alveo first-time setup
**********************
-.. warning::
- Alveo cards are not automatically supported in the new FINN release with Vitis 2022.1. If you are looking for a build flow for Alveo inside of FINN, you will need to use older FINN versions (v0.4b - v0.7) with Vitis 2020.1.
-
We use *host* to refer to the PC running the FINN Docker environment, which will build the accelerator+driver and package it up, and *target* to refer to the PC where the Alveo card is installed. These two can be the same PC, or connected over the network -- FINN includes some utilities to make it easier to test on remote PCs too. Prior to first usage, you need to set up both the host and the target in the following manner:
On the target side:
diff --git a/docs/finn/hw_build.rst b/docs/finn/hw_build.rst
index e1e5411adb4078636ddd4c0087245f8c2a58c372..2a64b87943075ff004f79c9d457136e41e27723d 100644
--- a/docs/finn/hw_build.rst
+++ b/docs/finn/hw_build.rst
@@ -12,10 +12,6 @@ A model where all layers have been converted to HLS layers can be processed by
FINN to build a bitfile and driver targeting a Zynq system or to generate a Vivado IP Integrator (IPI)
design with AXI stream (FIFO) in-out interfaces, which can be integrated onto any Xilinx FPGA as part of a larger system.
-.. warning::
- With the new FINN release, we do not offer out-of-the box support for Alveo cards anymore.
- Please use an older FINN version (v04b - v0.7) and Vitis 2020.1 in case you want to use `VitisBuild`. The description for the `VitisBuild` below is still valid for older versions.
-
Hardware Build
==============
diff --git a/run-docker.sh b/run-docker.sh
index 3a83004a0ec18168c015a5152a18ec5bcfa47c9b..381be35293dddbabe077be2aeae609f8c5621842 100755
--- a/run-docker.sh
+++ b/run-docker.sh
@@ -86,7 +86,7 @@ SCRIPTPATH=$(dirname "$SCRIPT")
: ${ALVEO_BOARD="U250"}
: ${ALVEO_TARGET_DIR="/tmp"}
: ${PLATFORM_REPO_PATHS="/opt/xilinx/platforms"}
-: ${XRT_DEB_VERSION="xrt_202010.2.7.766_18.04-amd64-xrt"}
+: ${XRT_DEB_VERSION="xrt_202210.2.13.466_18.04-amd64-xrt"}
: ${FINN_HOST_BUILD_DIR="/tmp/$DOCKER_INST_NAME"}
: ${FINN_DOCKER_TAG="xilinx/finn:$(git describe --always --tags --dirty).$XRT_DEB_VERSION"}
: ${FINN_DOCKER_PREBUILT="0"}
diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py
index c90985ebc9932c56c840e34464b838f3141c79a8..4aba87216c8999612f748e989a945ceff33da167 100644
--- a/src/finn/util/basic.py
+++ b/src/finn/util/basic.py
@@ -61,7 +61,7 @@ alveo_part_map["U280"] = "xcu280-fsvh2892-2L-e"
alveo_default_platform = dict()
alveo_default_platform["U50"] = "xilinx_u50_gen3x16_xdma_201920_3"
alveo_default_platform["U200"] = "xilinx_u200_xdma_201830_2"
-alveo_default_platform["U250"] = "xilinx_u250_xdma_201830_2"
+alveo_default_platform["U250"] = "xilinx_u250_gen3x16_xdma_2_1_202010_1"
alveo_default_platform["U280"] = "xilinx_u280_xdma_201920_3"
diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py
index 782e18fbc38ec8e1a9cc1d2facaba5b38d3c947d..103f18b514c23c4e1ad35a85d020dc0481aa9c47 100644
--- a/tests/end2end/test_end2end_bnn_pynq.py
+++ b/tests/end2end/test_end2end_bnn_pynq.py
@@ -673,9 +673,6 @@ class TestEnd2End:
@pytest.mark.vitis
@pytest.mark.parametrize("kind", ["zynq", "alveo"])
def test_build(self, topology, wbits, abits, QONNX_export, kind):
- # temporarily adding skip for alveo builds
- if kind == "alveo":
- pytest.skip("Alveo tests temporarily excluded")
if kind == "alveo" and ("VITIS_PATH" not in os.environ):
pytest.skip("VITIS_PATH not set")
prev_chkpt_name = get_checkpoint_name(
@@ -698,9 +695,6 @@ class TestEnd2End:
@pytest.mark.vitis
@pytest.mark.parametrize("kind", ["zynq", "alveo"])
def test_make_pynq_driver(self, topology, wbits, abits, QONNX_export, kind):
- # temporarily adding skip for alveo builds
- if kind == "alveo":
- pytest.skip("Alveo tests temporarily excluded")
if kind == "alveo" and ("VITIS_PATH" not in os.environ):
pytest.skip("VITIS_PATH not set")
prev_chkpt_name = get_checkpoint_name(
@@ -715,9 +709,6 @@ class TestEnd2End:
@pytest.mark.parametrize("kind", ["zynq", "alveo"])
def test_deploy(self, topology, wbits, abits, QONNX_export, kind):
- # temporarily adding skip for alveo builds
- if kind == "alveo":
- pytest.skip("Alveo tests temporarily excluded")
prev_chkpt_name = get_checkpoint_name(
topology, wbits, abits, QONNX_export, "driver_" + kind
)
@@ -741,9 +732,6 @@ class TestEnd2End:
@pytest.mark.parametrize("kind", ["zynq", "alveo"])
def test_run_on_hw(self, topology, wbits, abits, QONNX_export, kind):
- # temporarily adding skip for alveo builds
- if kind == "alveo":
- pytest.skip("Alveo tests temporarily excluded")
prev_chkpt_name = get_checkpoint_name(
topology, wbits, abits, QONNX_export, "deploy_" + kind
)
@@ -768,9 +756,6 @@ class TestEnd2End:
@pytest.mark.parametrize("kind", ["zynq", "alveo"])
def test_throughput_hw(self, topology, wbits, abits, QONNX_export, kind):
- # temporarily adding skip for alveo builds
- if kind == "alveo":
- pytest.skip("Alveo tests temporarily excluded")
prev_chkpt_name = get_checkpoint_name(
topology, wbits, abits, QONNX_export, "deploy_" + kind
)
diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
index a3809e61304ef031407e7fbec0f9037382d999ad..80f2d724ad7ccbf563c23076155313bad1ecb336 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
@@ -335,8 +335,6 @@ def test_fpgadataflow_ipstitch_iodma_floorplan():
@pytest.mark.slow
@pytest.mark.vivado
@pytest.mark.vitis
-# temporarily marked as xfail
-@pytest.mark.xfail
def test_fpgadataflow_ipstitch_vitis_end2end(board, period_ns, extw):
if "VITIS_PATH" not in os.environ:
pytest.skip("VITIS_PATH not set")
@@ -348,6 +346,8 @@ def test_fpgadataflow_ipstitch_vitis_end2end(board, period_ns, extw):
assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
assert os.path.isfile(sdp_node.get_nodeattr("model"))
model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model"))
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(PrepareIP(fpga_part, period_ns))
model = model.transform(VitisBuild(fpga_part, period_ns, platform))
model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_vitis.onnx")
assert model.get_metadata_prop("platform") == "alveo"
diff --git a/tests/util/test_build_dataflow.py b/tests/util/test_build_dataflow.py
index d33a4f2fd6c974b13ac315c7ef621eacb04002c4..cdf69aebddc4d6af2288774acbff5dd8a52512b3 100644
--- a/tests/util/test_build_dataflow.py
+++ b/tests/util/test_build_dataflow.py
@@ -39,6 +39,7 @@ from finn.util.basic import make_build_dir
@pytest.mark.slow
@pytest.mark.vivado
+@pytest.mark.end2end
def test_end2end_build_dataflow_directory():
test_dir = make_build_dir("test_build_dataflow_directory_")
target_dir = test_dir + "/build_dataflow"