diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn
index dbafba247679895bcbaf385f0d33946c3f810945..f823d3c42b8f958d0d7961c0bdeb931686999fce 100644
--- a/docker/Dockerfile.finn
+++ b/docker/Dockerfile.finn
@@ -88,8 +88,6 @@ RUN pip install jupyter==1.0.0 --ignore-installed
RUN pip install markupsafe==2.0.1
RUN pip install matplotlib==3.3.1 --ignore-installed
RUN pip install pytest-dependency==0.5.1
-RUN pip install sphinx==5.0.2
-RUN pip install sphinx_rtd_theme==0.5.0
RUN pip install pytest-xdist[setproctitle]==2.4.0
RUN pip install pytest-parallel==0.1.0
RUN pip install "netron>=5.0.0"
diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile
index e3e5b5f7f93c312269f2c96942e44318875903e0..2954877c2a950cd865c7aab2d3a4f80115972037 100644
--- a/docker/jenkins/Jenkinsfile
+++ b/docker/jenkins/Jenkinsfile
@@ -5,8 +5,8 @@ node {
checkout scm
}
withEnv([
- "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.1_0420_0327/installs/lin64",
- "FINN_XILINX_VERSION=2022.1",
+ "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.2_1014_8888/installs/lin64",
+ "FINN_XILINX_VERSION=2022.2",
"FINN_DOCKER_TAG=xilinx/finn:jenkins",
"FINN_HOST_BUILD_DIR=/scratch/users/finn_ci",
"PLATFORM_REPO_PATHS=/opt/xilinx/platforms"
diff --git a/docker/quicktest.sh b/docker/quicktest.sh
index b4ad37232fa69754a86e9064d7592d7474e8617e..466fcfb09dcf782c8c0f431555439286bcc351d5 100755
--- a/docker/quicktest.sh
+++ b/docker/quicktest.sh
@@ -6,7 +6,7 @@ cd $FINN_ROOT
# check if command line argument is empty or not present
if [ -z $1 ]; then
echo "Running quicktest: not (vivado or slow or board) with pytest-xdist"
- python setup.py test --addopts "-m 'not (vivado or slow or vitis or board)' --dist=loadfile -n $PYTEST_PARALLEL"
+ python setup.py test --addopts "-m 'not (vivado or slow or vitis or board or notebooks)' --dist=loadfile -n $PYTEST_PARALLEL"
elif [ $1 = "main" ]; then
echo "Running main test suite: not (rtlsim or end2end) with pytest-xdist"
python setup.py test --addopts "-k 'not (rtlsim or end2end)' --dist=loadfile -n $PYTEST_PARALLEL"
diff --git a/docs/finn/getting_started.rst b/docs/finn/getting_started.rst
index 9b3111b70eae97a3644e1de23c368bd5b09f7927..c575ca7e3b3b04eb651fb1135d949baad038f1ad 100644
--- a/docs/finn/getting_started.rst
+++ b/docs/finn/getting_started.rst
@@ -107,9 +107,6 @@ These are summarized below:
* (optional) ``LOCALHOST_URL`` (default localhost) sets the base URL for accessing e.g. Netron from inside the container. Useful when running FINN remotely.
* (optional) ``NETRON_PORT`` (default 8081) changes the port for Netron inside Docker
* (optional) ``PYNQ_BOARD`` or ``ALVEO_BOARD`` specifies the type of PYNQ/Alveo board used (see "supported hardware" below) for the test suite
-* (optional) ``PYNQ_IP`` and ``PYNQ_PORT`` (or ``ALVEO_IP`` and ``ALVEO_PORT``) specify ip address and port number to access the PYNQ board / Alveo target
-* (optional) ``PYNQ_USERNAME`` and ``PYNQ_PASSWORD`` (or ``ALVEO_USERNAME`` and ``ALVEO_PASSWORD``) specify the PYNQ board / Alveo host access credentials for the test suite. For PYNQ, password is always needed to run as sudo. For Alveo, you can leave the password empty and place your ssh private key in the ``finn/ssh_keys`` folder to use keypair authentication.
-* (optional) ``PYNQ_TARGET_DIR`` (or ``ALVEO_TARGET_DIR``) specifies the target dir on the PYNQ board / Alveo host for the test suite
* (optional) ``IMAGENET_VAL_PATH`` specifies the path to the ImageNet validation directory for tests.
* (optional) ``FINN_DOCKER_PREBUILT`` (default 0) if set to 1 then skip Docker image building and use the image tagged with ``FINN_DOCKER_TAG``.
* (optional) ``FINN_DOCKER_TAG`` (autogenerated) specifies the Docker image tag to use.
diff --git a/docs/finn/img/rtl_swg_impl_styles.png b/docs/finn/img/rtl_swg_impl_styles.png
new file mode 100644
index 0000000000000000000000000000000000000000..265ff9b915e79f8e93ca4f987bb49e57f8a2bd3e
Binary files /dev/null and b/docs/finn/img/rtl_swg_impl_styles.png differ
diff --git a/docs/finn/internals.rst b/docs/finn/internals.rst
index add70d649c773061c5b9e1d91dcaa852dcc4cbac..d0c4cd20650a7cb1ef63f68ff559bebbba93ae05 100644
--- a/docs/finn/internals.rst
+++ b/docs/finn/internals.rst
@@ -205,3 +205,84 @@ Disadvantages:
How to set *mem_mode*
---------------------
When the nodes in the network are converted to HLS layers, the *mem_mode* can be passed. More detailed information about the transformations that prepare the network and the transformation that performs the conversion to HLS layers can be found in chapter :ref:`nw_prep`. The *mem_mode* is passed as argument. Note that if no argument is passed, the default is *const*.
+
+RTL ConvolutionInputGenerator
+=============================
+
+FINN implements convolution operations by pairing a ConvolutionInputGenerator (or "sliding window generator (SWG)") with an MVAU or VVAU (for depthwise convolution).
+This RTL version is an alternative to the original `HLS implementation <https://github.com/Xilinx/finn-hlslib/blob/master/slidingwindow.h>`_ and aims to improve on it in the following ways:
+
+* Support a wider range of hyperparameters without the fragmentation into 16+ separate HLS functions
+
+* Support additional degrees of parallelism (i.e., across the output window or multiple input samples) that are difficult to implement in HLS
+
+* Support additional features, such as dynamic feature map sizing
+
+* Improve resource efficiency
+
+
+The component is implemented by generating (System-)Verilog code for each individual instance, realized via the template + replacement dictionary mechanism found in other FINN components.
+Despite the HDL implementation, the component is managed by its own HLSCustomOp (!) named "ConvolutionInputGenerator_rtl". Naturally, HLS simulation & synthesis are not supported.
+
+The RTL SWG is currently disabled by default and can be enabled either in the corresponding HLS conversion transformation (:py:mod:`finn.transformation.fpgadataflow.convert_to_hls_layers.InferConvInpGen`) with `use_rtl_variant=True` or in the build configuration (:py:mod:`finn.builder.build_dataflow_config.DataflowBuildConfig.force_rtl_conv_inp_gen` set to True).
+
+Implementation styles
+---------------------
+Depending on the amount of parallelism requested, one of two implementation styles is selected. The following table defines folding parameters (marked in bold text) and supported configurations.
+
+.. list-table:: Parallelism configurations
+
+ * - **SIMD**
+ - **parallel_window**
+ - **M**
+ - MMV_in
+ - MMV_out
+ - Style
+ - Notes
+ * - < C
+ - 0
+ - 1
+ - 1
+ - 1
+ - default
+ - depthwise-aware
+ * - C
+ - 0
+ - 1
+ - 1
+ - 1
+ - default
+ - depthwise-agnostic
+ * - C
+ - 1
+ - 1
+ - 1
+ - K
+ - parallel
+ - depthwise-agnostic
+ * - C
+ - 1
+ - M
+ - M
+ - M*K
+ - parallel
+ - Currently unsupported
+
+(With C = #Channels, MMV_in = input samples (or "pixels") per cycle, MMV_out = output samples (or "pixels") per cycle, K = kernel_width * kernel_height.)
+
+The following diagram shows the operating principle of both styles, the "parallel" variant is pictured for a 2x2 kernel without dilation.
+
+.. image:: img/rtl_swg_impl_styles.png
+ :align: center
+
+The main difference lies in the buffer structure. If the output width is equal to the input width ("default mode"), an addressable circular buffer is used, which can be implemented either in LUTRAM, BRAM, or URAM resources. If parallel access to multiple window elements is required ("parallel mode"), the SWG generates a fixed structure of registers and line buffers to avoid memory port limitations and exploding multiplexing logic, while still featuring LUT-saving BRAM/URAM implementation for the line buffers.
+
+The "default" style also supports a dynamic mode, which provides an interface to change feature map dimensions, stride, or dilation at run-time. See `this pull request <https://github.com/Xilinx/finn/pull/688>`_ description for more information.
+
+Folding
+-------
+The RTL SWG is supported by the basic automatic folding algorithm in FINN (:py:mod:`finn.transformation.fpgadataflow.set_folding.SetFolding`). Consider the following implications:
+
+**MVAU:** Although it is recommended to unfold SIMD first, SIMD and PE can be set independently. Full (and balanced) parallelism is achieved by using the SWG in parallel window mode and setting MVAU SIMD and PE to their maximum values (SIMD = MW = C_in * K, PE = MH = C_out).
+
+**VVAU:** While the VVAU HLS component supports SIMD unfolding independently from PE, the RTL SWG requires full unfolding across the channel dimension (SIMD of the SWG = PE of the VVAU) before enabling window-parallelism. Unlike the MVAU, the VVAU can't accept datawidth-converted input from a fully-parallel SWG in this case due to the depthwise data layout. As a result, the VVAU should be unfolded by PE first (up to PE = C), followed by SIMD (up to SIMD = K).
diff --git a/docs/finn/source_code/finn.core.rst b/docs/finn/source_code/finn.core.rst
index afa1ecffa08213db6a282076c6fdf59694f9e13e..28cb47eaf70cade96a1146559cbbd92248923a34 100644
--- a/docs/finn/source_code/finn.core.rst
+++ b/docs/finn/source_code/finn.core.rst
@@ -54,14 +54,6 @@ finn.core.onnx\_exec
:undoc-members:
:show-inheritance:
-finn.core.remote\_exec
------------------------------
-
-.. automodule:: finn.core.remote_exec
- :members:
- :undoc-members:
- :show-inheritance:
-
finn.core.rtlsim\_exec
-----------------------------
diff --git a/docs/finn/source_code/finn.transformation.fpgadataflow.rst b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
index 9f8ec079309f16daa022e14317ebddfd7758d639..f7137ae347486692938a23acb1e1fb2798559b33 100644
--- a/docs/finn/source_code/finn.transformation.fpgadataflow.rst
+++ b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
@@ -173,6 +173,15 @@ finn.transformation.fpgadataflow.minimize\_accumulator\_width
:show-inheritance:
+finn.transformation.fpgadataflow.minimize\_weight\_bit\_width
+--------------------------------------------------------------
+
+.. automodule:: finn.transformation.fpgadataflow.minimize_weight_bit_width
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+
finn.transformation.fpgadataflow.prepare\_cppsim
-------------------------------------------------------
diff --git a/docs/finn/source_code/finn.util.rst b/docs/finn/source_code/finn.util.rst
index 7ba3b252abfa0086a8c0281eb9a792fb239d6ec3..aebd0604f4c555f2b1bc637bc4c3d94b35309722 100644
--- a/docs/finn/source_code/finn.util.rst
+++ b/docs/finn/source_code/finn.util.rst
@@ -99,14 +99,6 @@ finn.util.fpgadataflow
:undoc-members:
:show-inheritance:
-finn.util.gdrive
------------------------------
-
-.. automodule:: finn.util.gdrive
- :members:
- :undoc-members:
- :show-inheritance:
-
finn.util.hls
---------------
diff --git a/docs/img/finn-examples-header.png b/docs/img/finn-examples-header.png
deleted file mode 100644
index 50f8fa7761e10a958ed3567f268ef675cf1814f7..0000000000000000000000000000000000000000
Binary files a/docs/img/finn-examples-header.png and /dev/null differ
diff --git a/docs/img/imagenet.jpg b/docs/img/imagenet.jpg
deleted file mode 100644
index 5cdd5aa303d9add5fbe6270936da0e152eca0135..0000000000000000000000000000000000000000
Binary files a/docs/img/imagenet.jpg and /dev/null differ
diff --git a/fetch-repos.sh b/fetch-repos.sh
index 5b060f5bc83b9d9709fc7e34e855543b4690af5a..e039ca9144fbb45e39331045b1fcbc209825ba0d 100755
--- a/fetch-repos.sh
+++ b/fetch-repos.sh
@@ -27,12 +27,12 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349"
-FINN_EXP_COMMIT="9cbd2787b5160e2b44e0e8164a0df1457dbd5366"
-BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03"
+QONNX_COMMIT="20a34289cf2297d2b2bbbe75d6ac152ece86e3b4"
+FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c"
+BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa"
PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f"
CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4"
-HLSLIB_COMMIT="d27f6b6c5d8f1bb208db395659389603f63ad4be"
+HLSLIB_COMMIT="c17aa478ae574971d115afa9fa4d9c215857d1ac"
OMX_COMMIT="d1065a788219ca0eb54d5e57600b1f9d7f67d4cc"
AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b"
XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e"
diff --git a/finn-rtllib/axi_info/component.xml b/finn-rtllib/axi_info/component.xml
index d22637534ff1fac1e3659c5dca6620d2f044ab87..c7632e29156fbd9dcbe554089dcc89cc6440f505 100644
--- a/finn-rtllib/axi_info/component.xml
+++ b/finn-rtllib/axi_info/component.xml
@@ -197,6 +197,10 @@
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
+ </spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
@@ -228,7 +232,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>7d682dfc</spirit:value>
+ <spirit:value>c9da9874</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -244,7 +248,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>7d682dfc</spirit:value>
+ <spirit:value>c9da9874</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -258,7 +262,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>e11f9727</spirit:value>
+ <spirit:value>1e654f67</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -607,7 +611,7 @@
<spirit:file>
<spirit:name>hdl/axi_info_top.sv</spirit:name>
<spirit:fileType>systemVerilogSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_ec9ff0da</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_db6ccc10</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -692,17 +696,22 @@
</xilinx:taxonomies>
<xilinx:displayName>axi_info_top_v1_0</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
- <xilinx:coreRevision>5</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2022-05-30T14:16:13Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>6</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2023-05-24T06:36:33Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="919b2cd5"/>
+ <xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3233b5e1"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="c930e363"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5ec5459d"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="28f3ac69"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="bd3646cb"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="eab94b69"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ba692e87"/>
+ <xilinx:targetDRCs>
+ <xilinx:targetDRC xilinx:tool="ipi">
+ <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
+ </xilinx:targetDRC>
+ </xilinx:targetDRCs>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/finn-rtllib/axi_info/hdl/axi_info_top.sv b/finn-rtllib/axi_info/hdl/axi_info_top.sv
index ab2cfc8bed3fcb2308c85a81cd687f56780150cb..74aebe3ec717db7a3f9c485d44a2c883499ff038 100644
--- a/finn-rtllib/axi_info/hdl/axi_info_top.sv
+++ b/finn-rtllib/axi_info/hdl/axi_info_top.sv
@@ -38,7 +38,10 @@ module axi_info_top #(
bit [31:0] CHECKSUM_COUNT
)(
//- Global Control ------------------
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET ap_rst_n" *)
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input logic ap_clk,
+ (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input logic ap_rst_n,
//- AXI Lite ------------------------
diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml
index 63a8540a76a100201c67d7a1dcbaec15f10e1c0e..722da1d803f089d04af8a8ecb2b2f9eb6479364a 100644
--- a/finn-rtllib/memstream/component.xml
+++ b/finn-rtllib/memstream/component.xml
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>user</spirit:library>
+ <spirit:vendor>amd.com</spirit:vendor>
+ <spirit:library>finn</spirit:library>
<spirit:name>memstream</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -37,201 +37,6 @@
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_1</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_1_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_1_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_1_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_1" xilinx:dependency="$NSTREAMS>=2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_2</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_2_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_2_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_2_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_2" xilinx:dependency="$NSTREAMS>=3">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_3</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_3_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_3_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_3_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_3" xilinx:dependency="$NSTREAMS>=4">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_4</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_4_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_4_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_4_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_4" xilinx:dependency="$NSTREAMS>=5">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>m_axis_5</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_5_tdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_5_tvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m_axis_5_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_5" xilinx:dependency="$NSTREAMS = 6">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
<spirit:busInterface>
<spirit:name>s_axilite</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
@@ -393,16 +198,9 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axilite" xilinx:dependency="$CONFIG_EN = 1">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>aresetn</spirit:name>
+ <spirit:name>ap_rst_n</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
@@ -412,19 +210,19 @@
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>aresetn</spirit:name>
+ <spirit:name>ap_rst_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>aclk</spirit:name>
+ <spirit:name>ap_clk</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
@@ -434,18 +232,22 @@
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>aclk</spirit:name>
+ <spirit:name>ap_clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis_0:m_axis_1:m_axis_2:m_axis_3:m_axis_4:m_axis_5:s_axilite</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">m_axis_0:s_axilite</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -453,11 +255,13 @@
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>interface_aximm</spirit:name>
+ <spirit:displayName>interface_aximm</spirit:displayName>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
- <spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
- <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1) + 1)" spirit:minimum="4096" spirit:rangeType="long">65536</spirit:range>
- <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
+ <spirit:displayName>reg0</spirit:displayName>
+ <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
+ <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1) - 0 + 1)" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
+ <spirit:width spirit:format="long">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
@@ -468,15 +272,15 @@
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
- <spirit:language>Verilog</spirit:language>
- <spirit:modelName>memstream</spirit:modelName>
+ <spirit:language>SystemVerilog</spirit:language>
+ <spirit:modelName>memstream_axi_wrapper</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>1fc5a310</spirit:value>
+ <spirit:value>04464096</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -484,15 +288,27 @@
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
- <spirit:language>Verilog</spirit:language>
- <spirit:modelName>memstream</spirit:modelName>
+ <spirit:language>SystemVerilog</spirit:language>
+ <spirit:modelName>memstream_axi_wrapper</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>d02d9990</spirit:value>
+ <spirit:value>9e058959</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_implementation</spirit:name>
+ <spirit:displayName>Implementation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
+ <spirit:modelName>memstream_axi_wrapper</spirit:modelName>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>cd434062</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -506,7 +322,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>f960907f</spirit:value>
+ <spirit:value>6c92393d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -520,14 +336,14 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>d2aad2c5</spirit:value>
+ <spirit:value>923e7b90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
- <spirit:name>aclk</spirit:name>
+ <spirit:name>ap_clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -540,7 +356,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>aresetn</spirit:name>
+ <spirit:name>ap_rst_n</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -582,11 +398,11 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>awaddr</spirit:name>
+ <spirit:name>awprot</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">15</spirit:left>
+ <spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -602,11 +418,11 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>awprot</spirit:name>
+ <spirit:name>awaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">10</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -766,11 +582,11 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>araddr</spirit:name>
+ <spirit:name>arprot</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">15</spirit:left>
+ <spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -786,11 +602,11 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>arprot</spirit:name>
+ <spirit:name>araddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXILITE_ADDR_WIDTH')) - 1)">10</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -868,29 +684,6 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
- <spirit:port>
- <spirit:name>m_axis_0_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_0_afull" xilinx:dependency="$NSTREAMS>2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
<spirit:port>
<spirit:name>m_axis_0_tready</spirit:name>
<spirit:wire>
@@ -925,352 +718,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM0_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_1_afull" xilinx:dependency="$NSTREAMS>2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_1_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM1_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_2_afull" xilinx:dependency="$NSTREAMS>=3">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_2_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM2_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_3_afull" xilinx:dependency="$NSTREAMS>=4">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_3_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM3_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_4_afull" xilinx:dependency="$NSTREAMS>=5">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_4_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM4_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_afull</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_5_afull" xilinx:dependency="$NSTREAMS = 6">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_tready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_tvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>m_axis_5_tdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.STRM5_WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.WIDTH')) + 7) / 8) * 8) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -1285,129 +733,29 @@
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
- <spirit:name>CONFIG_EN</spirit:name>
- <spirit:displayName>Config En</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONFIG_EN">true</spirit:value>
+ <spirit:name>DEPTH</spirit:name>
+ <spirit:displayName>Depth</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEPTH">512</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
- <spirit:name>NSTREAMS</spirit:name>
- <spirit:displayName>Nstreams</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NSTREAMS">6</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>MEM_DEPTH</spirit:name>
- <spirit:displayName>Mem Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_DEPTH">13824</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>MEM_WIDTH</spirit:name>
- <spirit:displayName>Mem Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_WIDTH">32</spirit:value>
+ <spirit:name>WIDTH</spirit:name>
+ <spirit:displayName>Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
- <spirit:name>MEM_INIT</spirit:name>
- <spirit:displayName>Mem Init</spirit:displayName>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_INIT">./</spirit:value>
+ <spirit:name>INIT_FILE</spirit:name>
+ <spirit:displayName>Init File</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INIT_FILE"/>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
<spirit:name>RAM_STYLE</spirit:name>
<spirit:displayName>Ram Style</spirit:displayName>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RAM_STYLE">auto</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM0_WIDTH</spirit:name>
- <spirit:displayName>Strm0 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM0_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM1_WIDTH</spirit:name>
- <spirit:displayName>Strm1 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM1_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM2_WIDTH</spirit:name>
- <spirit:displayName>Strm2 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM2_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM3_WIDTH</spirit:name>
- <spirit:displayName>Strm3 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM3_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM4_WIDTH</spirit:name>
- <spirit:displayName>Strm4 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM4_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM5_WIDTH</spirit:name>
- <spirit:displayName>Strm5 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM5_WIDTH">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM0_DEPTH</spirit:name>
- <spirit:displayName>Strm0 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM0_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM1_DEPTH</spirit:name>
- <spirit:displayName>Strm1 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM1_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM2_DEPTH</spirit:name>
- <spirit:displayName>Strm2 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM2_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM3_DEPTH</spirit:name>
- <spirit:displayName>Strm3 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM3_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM4_DEPTH</spirit:name>
- <spirit:displayName>Strm4 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM4_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM5_DEPTH</spirit:name>
- <spirit:displayName>Strm5 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM5_DEPTH">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM0_OFFSET</spirit:name>
- <spirit:displayName>Strm0 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM0_OFFSET">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM1_OFFSET</spirit:name>
- <spirit:displayName>Strm1 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM1_OFFSET">2304</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM2_OFFSET</spirit:name>
- <spirit:displayName>Strm2 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM2_OFFSET">4608</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM3_OFFSET</spirit:name>
- <spirit:displayName>Strm3 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM3_OFFSET">6912</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM4_OFFSET</spirit:name>
- <spirit:displayName>Strm4 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM4_OFFSET">9216</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>STRM5_OFFSET</spirit:name>
- <spirit:displayName>Strm5 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STRM5_OFFSET">11520</spirit:value>
- </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>AXILITE_ADDR_WIDTH</spirit:name>
<spirit:displayName>Axilite Addr Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_ADDR_WIDTH" spirit:dependency="(2 + spirit:ceil(spirit:log(2,(spirit:decode(id('MODELPARAM_VALUE.MEM_DEPTH')) * (1 << spirit:ceil(spirit:log(2,((spirit:decode(id('MODELPARAM_VALUE.MEM_WIDTH')) + 31) / 32))))))))">16</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_ADDR_WIDTH" spirit:dependency="(spirit:ceil(spirit:log(2,(spirit:decode(id('MODELPARAM_VALUE.DEPTH')) * (2 ** spirit:ceil(spirit:log(2,((spirit:decode(id('MODELPARAM_VALUE.WIDTH')) + 31) / 32))))))) + 2)">11</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
@@ -1417,13 +765,6 @@
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_e2bd1cd0</spirit:name>
- <spirit:enumeration>auto</spirit:enumeration>
- <spirit:enumeration>distributed</spirit:enumeration>
- <spirit:enumeration>block</spirit:enumeration>
- <spirit:enumeration>ultra</spirit:enumeration>
- </spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
@@ -1433,71 +774,41 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/memstream.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:name>hdl/memstream.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/memstream_multiblock.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:name>hdl/memstream_axi.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/memstream_singleblock.v</spirit:name>
+ <spirit:name>hdl/memstream_axi_wrapper.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/mux.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/ramb18_sdp.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/ramb18_wf_dualport.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_9425c051</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_7caabca7</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>hdl/memstream.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:name>hdl/memstream.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/axilite_if.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:name>hdl/memstream_axi.sv</spirit:name>
+ <spirit:fileType>systemVerilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/memstream_singleblock.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/mux.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/ramb18_wf_dualport.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
- <spirit:logicalName>xil_defaultlib</spirit:logicalName>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/memstream_multiblock.v</spirit:name>
+ <spirit:name>hdl/axilite_if.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>hdl/ramb18_sdp.v</spirit:name>
+ <spirit:name>hdl/memstream_axi_wrapper.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
@@ -1508,7 +819,7 @@
<spirit:file>
<spirit:name>xgui/memstream_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_f960907f</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_32cad48d</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
@@ -1520,132 +831,32 @@
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
- <spirit:description>memstream_v1_0</spirit:description>
+ <spirit:description>memstream</spirit:description>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>CONFIG_EN</spirit:name>
- <spirit:displayName>Config En</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CONFIG_EN">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>NSTREAMS</spirit:name>
- <spirit:displayName>Nstreams</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NSTREAMS" spirit:minimum="1" spirit:maximum="6" spirit:rangeType="long">6</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>MEM_DEPTH</spirit:name>
- <spirit:displayName>Mem Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_DEPTH">13824</spirit:value>
+ <spirit:name>DEPTH</spirit:name>
+ <spirit:displayName>Depth</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEPTH">512</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>MEM_WIDTH</spirit:name>
- <spirit:displayName>Mem Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_WIDTH">32</spirit:value>
+ <spirit:name>WIDTH</spirit:name>
+ <spirit:displayName>Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WIDTH">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>MEM_INIT</spirit:name>
- <spirit:displayName>Mem Init</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_INIT">./</spirit:value>
+ <spirit:name>INIT_FILE</spirit:name>
+ <spirit:displayName>Init File</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INIT_FILE"/>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RAM_STYLE</spirit:name>
<spirit:displayName>Ram Style</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RAM_STYLE" spirit:choiceRef="choice_list_e2bd1cd0">auto</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM0_WIDTH</spirit:name>
- <spirit:displayName>Strm0 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM0_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM1_WIDTH</spirit:name>
- <spirit:displayName>Strm1 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM1_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM2_WIDTH</spirit:name>
- <spirit:displayName>Strm2 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM2_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM3_WIDTH</spirit:name>
- <spirit:displayName>Strm3 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM3_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM4_WIDTH</spirit:name>
- <spirit:displayName>Strm4 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM4_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM5_WIDTH</spirit:name>
- <spirit:displayName>Strm5 Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_WIDTH">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM0_DEPTH</spirit:name>
- <spirit:displayName>Strm0 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM0_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM1_DEPTH</spirit:name>
- <spirit:displayName>Strm1 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM1_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM2_DEPTH</spirit:name>
- <spirit:displayName>Strm2 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM2_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM3_DEPTH</spirit:name>
- <spirit:displayName>Strm3 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM3_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM4_DEPTH</spirit:name>
- <spirit:displayName>Strm4 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM4_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM5_DEPTH</spirit:name>
- <spirit:displayName>Strm5 Depth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_DEPTH">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM0_OFFSET</spirit:name>
- <spirit:displayName>Strm0 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM0_OFFSET">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM1_OFFSET</spirit:name>
- <spirit:displayName>Strm1 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM1_OFFSET">2304</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM2_OFFSET</spirit:name>
- <spirit:displayName>Strm2 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM2_OFFSET">4608</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM3_OFFSET</spirit:name>
- <spirit:displayName>Strm3 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM3_OFFSET">6912</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM4_OFFSET</spirit:name>
- <spirit:displayName>Strm4 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM4_OFFSET">9216</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>STRM5_OFFSET</spirit:name>
- <spirit:displayName>Strm5 Offset</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STRM5_OFFSET">11520</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RAM_STYLE">auto</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AXILITE_ADDR_WIDTH</spirit:name>
<spirit:displayName>Axilite Addr Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXILITE_ADDR_WIDTH">16</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXILITE_ADDR_WIDTH">11</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -1656,52 +867,40 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_v1_0</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_axi_wrapper_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
- <xilinx:supportedFamilies>
- <xilinx:family xilinx:lifeCycle="Beta">aartix7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">akintex7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">artix7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">artix7l</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Beta">azynq</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">qzynqplus</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">versalprime</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">virtexupluse58g</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
- <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
- </xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>memstream_v1_0</xilinx:displayName>
+ <xilinx:displayName>memstream</xilinx:displayName>
+ <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
+ <xilinx:vendorDisplayName>AMD</xilinx:vendorDisplayName>
<xilinx:coreRevision>5</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2020-10-09T15:31:57Z</xilinx:coreCreationDateTime>
+ <xilinx:upgrades>
+ <xilinx:canUpgradeFrom>user.org:user:memstream_axi_wrapper:1.0</xilinx:canUpgradeFrom>
+ </xilinx:upgrades>
+ <xilinx:coreCreationDateTime>2023-05-24T06:34:57Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="nopcore"/>
+ </xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8f86a494"/>
- <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5a080bee"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d633e93f"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="2e562330"/>
- <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="134f154d"/>
- <xilinx:checksum xilinx:scope="parameters" xilinx:value="83e5a517"/>
+ <xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="aace24af"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="b683eac1"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7304ec2c"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="8c876e99"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6488ba6f"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="10eb550f"/>
+ <xilinx:targetDRCs>
+ <xilinx:targetDRC xilinx:tool="ipi">
+ <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
+ </xilinx:targetDRC>
+ </xilinx:targetDRCs>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl
index a68b85e1f5bdb3dc102f14eb4e3b8d82a86fa556..271f9df453265a7d21c36887300d1d60d3f4f4d0 100644
--- a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl
+++ b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl
@@ -1,2 +1,2 @@
# This file is automatically written. Do not modify.
-proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {MEM_DEPTH MEM_WIDTH } {expr 2+ceil(log($MEM_DEPTH*pow(2,ceil(log(($MEM_WIDTH+31)/32)/log(2))))/log(2))}
+proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr 2 + ceil(log($DEPTH*pow(2, ceil(log(($WIDTH+31)/32)/log(2))))/log(2))}
diff --git a/finn-rtllib/memstream/hdl/memstream.sv b/finn-rtllib/memstream/hdl/memstream.sv
new file mode 100644
index 0000000000000000000000000000000000000000..9cbef493a3e57f3c7e8caeb310d54281799ef6c9
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream.sv
@@ -0,0 +1,176 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream #(
+ int unsigned DEPTH,
+ int unsigned WIDTH,
+
+ parameter INIT_FILE = "",
+ parameter RAM_STYLE = "auto"
+)(
+ input logic clk,
+ input logic rst,
+
+ // Configuration and readback interface - compatible with ap_memory
+ input logic config_ce,
+ input logic config_we,
+ input logic [31 :0] config_address,
+ input logic [WIDTH-1:0] config_d0,
+
+ output logic config_rack,
+ output logic [WIDTH-1:0] config_q0,
+
+ // Continuous output stream
+ input logic ordy,
+ output logic ovld,
+ output logic [WIDTH-1:0] odat
+);
+
+ typedef logic [$clog2(DEPTH)-1:0] addr_t;
+ typedef logic [WIDTH -1:0] data_t;
+
+ uwire en; // Pipeline enable
+ uwire rollback; // Rollback stream reads if backpressure would block read back
+
+ // Counter with pre-computed last indication for val == DEPTH-1
+ typedef struct {
+ addr_t val;
+ logic lst;
+ } ptr_t;
+
+ // Counter history to facilitate pipeline rollback
+ ptr_t Ptr[3] = '{
+ 0: '{ val: 0, lst: DEPTH<2 },
+ default: '{ default: 'x }
+ };
+
+ //-----------------------------------------------------------------------
+ // Stage #0: Address & Op
+ logic Wr1 = 0; // Write
+ logic Rb1 = 0; // Read back
+ logic Rs1 = 0; // Read stream
+ data_t Data1 = 'x;
+ if(1) begin : blkStage1
+ // Increment for wrapping DEPTH-1 back to zero
+ localparam int unsigned WRAP_INC = 2**$bits(addr_t) - DEPTH + 1;
+
+ uwire ptr_t ptr_eff = rollback? Ptr[2] : Ptr[0];
+ uwire ptr_t ptr_nxt;
+ assign ptr_nxt.val = ptr_eff.val + (config_ce? 0 : !ptr_eff.lst? 1 : WRAP_INC);
+ assign ptr_nxt.lst =
+ DEPTH < 2? 1 :
+ config_ce? ptr_eff.lst :
+ ptr_eff.lst? 0 :
+ /* else */ ptr_eff.val == DEPTH-2;
+
+ always_ff @(posedge clk) begin
+ if(rst) Ptr[0] <= '{ val: 0, lst: DEPTH<2 };
+ else if(en) Ptr[0] <= ptr_nxt;
+ end
+
+ // Issue next Memory Operation
+ always_ff @(posedge clk) begin
+ if(rst) begin
+ Wr1 <= 0;
+ Rb1 <= 0;
+ Rs1 <= 0;
+ Ptr[1] <= '{ default : 'x };
+ Data1 <= 'x;
+ end
+ else if(en) begin
+ Wr1 <= 0;
+ Rb1 <= 0;
+ Rs1 <= 0;
+ if(config_ce) begin
+ if(config_we) Wr1 <= 1;
+ else Rb1 <= 1;
+ Ptr[1] <= '{ val: config_address, lst: 'x };
+ Data1 <= config_d0;
+ end
+ else begin
+ Rs1 <= 1;
+ Ptr[1] <= ptr_eff;
+ Data1 <= 'x;
+ end
+ end
+ end
+ end : blkStage1
+
+ //-----------------------------------------------------------------------
+ // Stage #2: Memory Access
+ logic Rb2 = 0;
+ logic Rs2 = 0;
+ data_t Data2 = 'x;
+ if(1) begin : blkStage2
+ (* RAM_STYLE = RAM_STYLE *)
+ data_t Mem[DEPTH];
+
+ // Optional Memory Initialization
+ if(INIT_FILE != "") initial $readmemh(INIT_FILE, Mem);
+
+ // Execute Memory Operation
+ uwire addr_t addr = Ptr[1].val;
+ always_ff @(posedge clk) begin
+ if(en) begin
+ if(Wr1) Mem[addr] <= Data1;
+ Data2 <= Mem[addr];
+ end
+ end
+
+ // Copy Output Designation
+ always_ff @(posedge clk) begin
+ if(rst) begin
+ Rb2 <= 0;
+ Rs2 <= 0;
+ Ptr[2] <= '{ default: 'x };
+ end
+ else if(en) begin
+ Rb2 <= Rb1;
+ Rs2 <= Rs1 && !rollback;
+ Ptr[2] <= Ptr[1];
+ end
+ end
+ end : blkStage2
+
+ //-----------------------------------------------------------------------
+ // Output Interfaces
+ assign config_rack = Rb2;
+ assign config_q0 = Data2;
+
+ assign ovld = Rs2;
+ assign odat = Data2;
+
+ uwire backpressure = Rs2 && !ordy;
+ assign rollback = backpressure && (Rb1 || config_ce);
+ assign en = !backpressure || Rb1 || config_ce;
+
+endmodule : memstream
diff --git a/finn-rtllib/memstream/hdl/memstream.v b/finn-rtllib/memstream/hdl/memstream.v
deleted file mode 100644
index 2cd955f8d1ff0dd5dfed8b004df7053573a43488..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/memstream.v
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module memstream
-#(
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
- parameter CONFIG_EN = 1,
- parameter NSTREAMS = 6,//1 up to 6
-
- parameter MEM_DEPTH = 13824,
- parameter MEM_WIDTH = 32,
- parameter MEM_INIT = "./",
- parameter RAM_STYLE = "auto",
-
- //widths per stream
- parameter STRM0_WIDTH = 32,
- parameter STRM1_WIDTH = 32,
- parameter STRM2_WIDTH = 32,
- parameter STRM3_WIDTH = 32,
- parameter STRM4_WIDTH = 32,
- parameter STRM5_WIDTH = 32,
-
- //depths per stream
- parameter STRM0_DEPTH = 2304,
- parameter STRM1_DEPTH = 2304,
- parameter STRM2_DEPTH = 2304,
- parameter STRM3_DEPTH = 2304,
- parameter STRM4_DEPTH = 2304,
- parameter STRM5_DEPTH = 2304,
-
- //offsets for each stream
- parameter STRM0_OFFSET = 0,
- parameter STRM1_OFFSET = 2304,
- parameter STRM2_OFFSET = 4608,
- parameter STRM3_OFFSET = 6912,
- parameter STRM4_OFFSET = 9216,
- parameter STRM5_OFFSET = 11520,
-
- parameter AXILITE_ADDR_WIDTH = 2+$clog2(MEM_DEPTH*(1<<$clog2((MEM_WIDTH+31)/32)))
-)
-
-(
- input aclk,
- input aresetn,
-
- output awready,
- input awvalid,
- input [AXILITE_ADDR_WIDTH-1:0] awaddr,
- input [2:0] awprot,
- //write data
- output wready,
- input wvalid,
- input [31:0] wdata,
- input [3:0] wstrb,
- //burst response
- input bready,
- output bvalid,
- output [1:0] bresp,
-
- //Read channels
- //read address
- output arready,
- input arvalid,
- input [AXILITE_ADDR_WIDTH-1:0] araddr,
- input [2:0] arprot,
- //read data
- input rready,
- output rvalid,
- output [1:0] rresp,
- output [31:0] rdata,
-
- //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
- input m_axis_0_afull,
- input m_axis_0_tready,
- output m_axis_0_tvalid,
- output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
-
- input m_axis_1_afull,
- input m_axis_1_tready,
- output m_axis_1_tvalid,
- output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata,
-
- input m_axis_2_afull,
- input m_axis_2_tready,
- output m_axis_2_tvalid,
- output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata,
-
- input m_axis_3_afull,
- input m_axis_3_tready,
- output m_axis_3_tvalid,
- output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata,
-
- input m_axis_4_afull,
- input m_axis_4_tready,
- output m_axis_4_tvalid,
- output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata,
-
- input m_axis_5_afull,
- input m_axis_5_tready,
- output m_axis_5_tvalid,
- output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata
-
-
-);
-
-wire [31:0] config_address;
-wire config_ce;
-wire config_we;
-wire config_rack;
-wire [MEM_WIDTH-1:0] config_d0;
-wire [MEM_WIDTH-1:0] config_q0;
-
-generate
-if(NSTREAMS <= 2) begin: singleblock
-
-
-memstream_singleblock
-#(
- .CONFIG_EN(CONFIG_EN),
- .NSTREAMS(NSTREAMS),
- .MEM_DEPTH(MEM_DEPTH),
- .MEM_WIDTH(MEM_WIDTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE),
-
- //widths per stream
- .STRM0_WIDTH(STRM0_WIDTH),
- .STRM1_WIDTH(STRM1_WIDTH),
-
- //depths per stream
- .STRM0_DEPTH(STRM0_DEPTH),
- .STRM1_DEPTH(STRM1_DEPTH),
-
- //offsets for each stream
- .STRM0_OFFSET(STRM0_OFFSET),
- .STRM1_OFFSET(STRM1_OFFSET)
-)
-mem
-(
- .aclk(aclk),
- .aresetn(aresetn),
-
- .config_address(config_address),
- .config_ce(config_ce),
- .config_we(config_we),
- .config_d0(config_d0),
- .config_q0(config_q0),
- .config_rack(config_rack),
-
- .m_axis_0_tready(m_axis_0_tready),
- .m_axis_0_tvalid(m_axis_0_tvalid),
- .m_axis_0_tdata(m_axis_0_tdata),
-
- .m_axis_1_tready(m_axis_1_tready),
- .m_axis_1_tvalid(m_axis_1_tvalid),
- .m_axis_1_tdata(m_axis_1_tdata)
-);
-
-assign m_axis_2_tvalid = 0;
-assign m_axis_2_tdata = 0;
-assign m_axis_3_tvalid = 0;
-assign m_axis_3_tdata = 0;
-assign m_axis_4_tvalid = 0;
-assign m_axis_4_tdata = 0;
-assign m_axis_5_tvalid = 0;
-assign m_axis_5_tdata = 0;
-
-end else begin: multiblock
-
-
-memstream_multiblock
-#(
- .CONFIG_EN(CONFIG_EN),
- .NSTREAMS(NSTREAMS),
- .MEM_DEPTH(MEM_DEPTH),
- .MEM_WIDTH(MEM_WIDTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE),
-
- //widths per stream
- .STRM0_WIDTH(STRM0_WIDTH),
- .STRM1_WIDTH(STRM1_WIDTH),
- .STRM2_WIDTH(STRM2_WIDTH),
- .STRM3_WIDTH(STRM3_WIDTH),
- .STRM4_WIDTH(STRM4_WIDTH),
- .STRM5_WIDTH(STRM5_WIDTH),
-
- //depths per stream
- .STRM0_DEPTH(STRM0_DEPTH),
- .STRM1_DEPTH(STRM1_DEPTH),
- .STRM2_DEPTH(STRM2_DEPTH),
- .STRM3_DEPTH(STRM3_DEPTH),
- .STRM4_DEPTH(STRM4_DEPTH),
- .STRM5_DEPTH(STRM5_DEPTH),
-
- //offsets for each stream
- .STRM0_OFFSET(STRM0_OFFSET),
- .STRM1_OFFSET(STRM1_OFFSET),
- .STRM2_OFFSET(STRM2_OFFSET),
- .STRM3_OFFSET(STRM3_OFFSET),
- .STRM4_OFFSET(STRM4_OFFSET),
- .STRM5_OFFSET(STRM5_OFFSET)
-)
-mem
-(
- .aclk(aclk),
- .aresetn(aresetn),
-
- .config_address(config_address),
- .config_ce(config_ce),
- .config_we(config_we),
- .config_d0(config_d0),
- .config_q0(config_q0),
-
- .m_axis_0_afull(m_axis_0_afull),
- .m_axis_0_tready(m_axis_0_tready),
- .m_axis_0_tvalid(m_axis_0_tvalid),
- .m_axis_0_tdata(m_axis_0_tdata),
-
- .m_axis_1_afull(m_axis_1_afull),
- .m_axis_1_tready(m_axis_1_tready),
- .m_axis_1_tvalid(m_axis_1_tvalid),
- .m_axis_1_tdata(m_axis_1_tdata),
-
- .m_axis_2_afull(m_axis_2_afull),
- .m_axis_2_tready(m_axis_2_tready),
- .m_axis_2_tvalid(m_axis_2_tvalid),
- .m_axis_2_tdata(m_axis_2_tdata),
-
- .m_axis_3_afull(m_axis_3_afull),
- .m_axis_3_tready(m_axis_3_tready),
- .m_axis_3_tvalid(m_axis_3_tvalid),
- .m_axis_3_tdata(m_axis_3_tdata),
-
- .m_axis_4_afull(m_axis_4_afull),
- .m_axis_4_tready(m_axis_4_tready),
- .m_axis_4_tvalid(m_axis_4_tvalid),
- .m_axis_4_tdata(m_axis_4_tdata),
-
- .m_axis_5_afull(m_axis_5_afull),
- .m_axis_5_tready(m_axis_5_tready),
- .m_axis_5_tvalid(m_axis_5_tvalid),
- .m_axis_5_tdata(m_axis_5_tdata)
-
-);
-
-
-end
-endgenerate
-
-axi4lite_if
-#(
- .ADDR_WIDTH(AXILITE_ADDR_WIDTH),
- .DATA_WIDTH(32),
- .IP_DATA_WIDTH(MEM_WIDTH)
-)
-config_if
-(
- //system signals
- .aclk(aclk),
- .aresetn(aresetn),
-
- //Write channels
- //write address
- .awready(awready),
- .awvalid(awvalid),
- .awaddr(awaddr),
- .awprot(awprot),
- //write data
- .wready(wready),
- .wvalid(wvalid),
- .wdata(wdata),
- .wstrb(wstrb),
- //burst response
- .bready(bready),
- .bvalid(bvalid),
- .bresp(bresp),
-
- //Read channels
- //read address
- .arready(arready),
- .arvalid(arvalid),
- .araddr(araddr),
- .arprot(arprot),
- //read data
- .rready(rready),
- .rvalid(rvalid),
- .rresp(rresp),
- .rdata(rdata),
-
- //IP-side interface
- .ip_en(config_ce),
- .ip_wen(config_we),
- .ip_addr(config_address),
- .ip_wdata(config_d0),
- .ip_rack(config_rack),
- .ip_rdata(config_q0)
-);
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/memstream_axi.sv b/finn-rtllib/memstream/hdl/memstream_axi.sv
new file mode 100644
index 0000000000000000000000000000000000000000..136bcb1d7e5d28a56e84302346f97b4844ebf69a
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream_axi.sv
@@ -0,0 +1,136 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream_axi #(
+ int unsigned DEPTH,
+ int unsigned WIDTH,
+
+ parameter INIT_FILE = "",
+ parameter RAM_STYLE = "auto",
+
+ localparam int unsigned AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2
+)(
+ // Global Control
+ input logic clk,
+ input logic rst,
+
+ // AXI-lite Write
+ output logic awready,
+ input logic awvalid,
+ input logic [2:0] awprot,
+ input logic [AXILITE_ADDR_WIDTH-1:0] awaddr,
+
+ output logic wready,
+ input logic wvalid,
+ input logic [31:0] wdata,
+ input logic [ 3:0] wstrb,
+
+ input logic bready,
+ output logic bvalid,
+ output logic [1:0] bresp,
+
+ // AXI-lite Read
+ output logic arready,
+ input logic arvalid,
+ input logic [2:0] arprot,
+ input logic [AXILITE_ADDR_WIDTH-1:0] araddr,
+
+ input logic rready,
+ output logic rvalid,
+ output logic [ 1:0] rresp,
+ output logic [31:0] rdata,
+
+ // Continuous output stream
+ input logic m_axis_0_tready,
+ output logic m_axis_0_tvalid,
+ output logic [((WIDTH+7)/8)*8-1:0] m_axis_0_tdata
+);
+
+ //-----------------------------------------------------------------------
+ // AXI-lite to ap_memory Adapter
+ uwire [31:0] config_address;
+ uwire config_ce;
+ uwire config_we;
+ uwire config_rack;
+ uwire [WIDTH-1:0] config_d0;
+ uwire [WIDTH-1:0] config_q0;
+ axi4lite_if #(
+ .ADDR_WIDTH(AXILITE_ADDR_WIDTH),
+ .DATA_WIDTH(32),
+ .IP_DATA_WIDTH(WIDTH)
+ ) config_if (
+ .aclk(clk), .aresetn(!rst),
+
+ // Write Channels
+ .awready, .awvalid, .awaddr, .awprot,
+ .wready, .wvalid, .wdata, .wstrb,
+ .bready, .bvalid, .bresp,
+
+ // Read Channels
+ .arready, .arvalid, .araddr, .arprot,
+ .rready, .rvalid, .rresp, .rdata,
+
+ // IP-side Interface
+ .ip_en(config_ce),
+ .ip_wen(config_we),
+ .ip_addr(config_address),
+ .ip_wdata(config_d0),
+ .ip_rack(config_rack),
+ .ip_rdata(config_q0)
+ );
+
+ //-----------------------------------------------------------------------
+ // Streaming Memory Backend
+ memstream #(
+ .DEPTH(DEPTH),
+ .WIDTH(WIDTH),
+ .INIT_FILE(INIT_FILE),
+ .RAM_STYLE(RAM_STYLE)
+ ) mem (
+ .clk, .rst,
+
+ .config_address,
+ .config_ce,
+ .config_we,
+ .config_d0,
+ .config_q0,
+ .config_rack,
+
+ .ordy(m_axis_0_tready),
+ .ovld(m_axis_0_tvalid),
+ .odat(m_axis_0_tdata[WIDTH-1:0])
+ );
+ if($bits(m_axis_0_tdata) > WIDTH) begin
+ assign m_axis_0_tdata[$left(m_axis_0_tdata):WIDTH] = '0;
+ end
+
+endmodule : memstream_axi
diff --git a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..13f5c82d6e1a3046ca9f2b227687f1c69204f24b
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v
@@ -0,0 +1,123 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream_axi_wrapper #(
+ parameter DEPTH = 512,
+ parameter WIDTH = 32,
+
+ parameter INIT_FILE = "",
+ parameter RAM_STYLE = "auto",
+
+ parameter AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2
+)(
+ // Global Control
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0, ASSOCIATED_RESET ap_rst_n" *)
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
+ input ap_clk,
+ (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
+ input ap_rst_n,
+
+ // AXI-lite Write
+ output awready,
+ input awvalid,
+ input [2:0] awprot,
+ input [AXILITE_ADDR_WIDTH-1:0] awaddr,
+
+ output wready,
+ input wvalid,
+ input [31:0] wdata,
+ input [ 3:0] wstrb,
+
+ input bready,
+ output bvalid,
+ output [1:0] bresp,
+
+ // AXI-lite Read
+ output arready,
+ input arvalid,
+ input [2:0] arprot,
+ input [AXILITE_ADDR_WIDTH-1:0] araddr,
+
+ input rready,
+ output rvalid,
+ output [ 1:0] rresp,
+ output [31:0] rdata,
+
+ // Continuous output stream
+ input m_axis_0_tready,
+ output m_axis_0_tvalid,
+ output [((WIDTH+7)/8)*8-1:0] m_axis_0_tdata
+);
+
+ localparam INIT_FILTERED =
+`ifdef SYNTHESIS
+ RAM_STYLE == "ultra"? "" :
+`endif
+ INIT_FILE;
+
+ memstream_axi #(
+ .DEPTH(DEPTH), .WIDTH(WIDTH),
+ .INIT_FILE(INIT_FILTERED),
+ .RAM_STYLE(RAM_STYLE)
+ ) core (
+ .clk(ap_clk), .rst(!ap_rst_n),
+
+ // AXI-lite Write
+ .awready(awready),
+ .awvalid(awvalid),
+ .awprot(awprot),
+ .awaddr(awaddr),
+ .wready(wready),
+ .wvalid(wvalid),
+ .wdata(wdata),
+ .wstrb(wstrb),
+ .bready(bready),
+ .bvalid(bvalid),
+ .bresp(bresp),
+
+ // AXI-lite Read
+ .arready(arready),
+ .arvalid(arvalid),
+ .arprot(arprot),
+ .araddr(araddr),
+ .rready(rready),
+ .rvalid(rvalid),
+ .rresp(rresp),
+ .rdata(rdata),
+
+ // Continuous output stream
+ .m_axis_0_tready(m_axis_0_tready),
+ .m_axis_0_tvalid(m_axis_0_tvalid),
+ .m_axis_0_tdata(m_axis_0_tdata)
+ );
+
+endmodule : memstream_axi_wrapper
diff --git a/finn-rtllib/memstream/hdl/memstream_multiblock.v b/finn-rtllib/memstream/hdl/memstream_multiblock.v
deleted file mode 100644
index 4e6167132da119d9e19a5f4b6a378311e74311c3..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/memstream_multiblock.v
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module memstream_multiblock
-#(
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
- parameter CONFIG_EN = 1,
- parameter NSTREAMS = 6,//1 up to 6
-
- parameter MEM_DEPTH = 13824,
- parameter MEM_WIDTH = 32,
- parameter MEM_INIT = "./",
- parameter RAM_STYLE = "auto",
-
- //widths per stream
- parameter STRM0_WIDTH = 32,
- parameter STRM1_WIDTH = 32,
- parameter STRM2_WIDTH = 32,
- parameter STRM3_WIDTH = 32,
- parameter STRM4_WIDTH = 32,
- parameter STRM5_WIDTH = 32,
-
- //depths per stream
- parameter STRM0_DEPTH = 2304,
- parameter STRM1_DEPTH = 2304,
- parameter STRM2_DEPTH = 2304,
- parameter STRM3_DEPTH = 2304,
- parameter STRM4_DEPTH = 2304,
- parameter STRM5_DEPTH = 2304,
-
- //offsets for each stream
- parameter STRM0_OFFSET = 0,
- parameter STRM1_OFFSET = 2304,
- parameter STRM2_OFFSET = 4608,
- parameter STRM3_OFFSET = 6912,
- parameter STRM4_OFFSET = 9216,
- parameter STRM5_OFFSET = 11520
-)
-
-(
- input aclk,
- input aresetn,
-
- //optional configuration interface compatible with ap_memory
- input [31:0] config_address,
- input config_ce,
- input config_we,
- input [31:0] config_d0,
- output [31:0] config_q0,
- output config_rack,
-
- //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
- input m_axis_0_afull,
- input m_axis_0_tready,
- output m_axis_0_tvalid,
- output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
-
- input m_axis_1_afull,
- input m_axis_1_tready,
- output m_axis_1_tvalid,
- output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata,
-
- input m_axis_2_afull,
- input m_axis_2_tready,
- output m_axis_2_tvalid,
- output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata,
-
- input m_axis_3_afull,
- input m_axis_3_tready,
- output m_axis_3_tvalid,
- output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata,
-
- input m_axis_4_afull,
- input m_axis_4_tready,
- output m_axis_4_tvalid,
- output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata,
-
- input m_axis_5_afull,
- input m_axis_5_tready,
- output m_axis_5_tvalid,
- output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata
-
-
-);
-
-//calculate number of RAMB18 blocks we need depth-wise
-localparam NMEMBLOCKS = (MEM_DEPTH+1023) / 1024; //ceil(MEM_DEPTH/1024)
-
-//calculate width of address for each block
-localparam BLOCKADRWIDTH = NMEMBLOCKS > 1 ? 10 : $clog2(MEM_DEPTH);
-
-//determine whether a stream needs to multiplex between memory blocks
-localparam STRM0_MUX = ((STRM0_OFFSET/1024) != ((STRM0_OFFSET+STRM0_DEPTH)/1024));
-localparam STRM1_MUX = ((STRM1_OFFSET/1024) != ((STRM1_OFFSET+STRM1_DEPTH)/1024));
-localparam STRM2_MUX = ((STRM2_OFFSET/1024) != ((STRM2_OFFSET+STRM2_DEPTH)/1024));
-localparam STRM3_MUX = ((STRM3_OFFSET/1024) != ((STRM3_OFFSET+STRM3_DEPTH)/1024));
-localparam STRM4_MUX = ((STRM4_OFFSET/1024) != ((STRM4_OFFSET+STRM4_DEPTH)/1024));
-localparam STRM5_MUX = ((STRM5_OFFSET/1024) != ((STRM5_OFFSET+STRM5_DEPTH)/1024));
-
-//determine what the base block of each stream is
-localparam STRM0_BLOCK = (STRM0_OFFSET/1024);
-localparam STRM1_BLOCK = (STRM1_OFFSET/1024);
-localparam STRM2_BLOCK = (STRM2_OFFSET/1024);
-localparam STRM3_BLOCK = (STRM3_OFFSET/1024);
-localparam STRM4_BLOCK = (STRM4_OFFSET/1024);
-localparam STRM5_BLOCK = (STRM5_OFFSET/1024);
-
-//determine what the end block of each stream is
-localparam STRM0_END_BLOCK = ((STRM0_OFFSET+STRM0_DEPTH-1)/1024);
-localparam STRM1_END_BLOCK = ((STRM1_OFFSET+STRM1_DEPTH-1)/1024);
-localparam STRM2_END_BLOCK = ((STRM2_OFFSET+STRM2_DEPTH-1)/1024);
-localparam STRM3_END_BLOCK = ((STRM3_OFFSET+STRM3_DEPTH-1)/1024);
-localparam STRM4_END_BLOCK = ((STRM4_OFFSET+STRM4_DEPTH-1)/1024);
-localparam STRM5_END_BLOCK = ((STRM5_OFFSET+STRM5_DEPTH-1)/1024);
-
-//determine the number of blocks spanned by each stream
-localparam STRM0_NBLOCKS = STRM0_END_BLOCK - STRM0_BLOCK + 1;
-localparam STRM1_NBLOCKS = STRM1_END_BLOCK - STRM1_BLOCK + 1;
-localparam STRM2_NBLOCKS = STRM2_END_BLOCK - STRM2_BLOCK + 1;
-localparam STRM3_NBLOCKS = STRM3_END_BLOCK - STRM3_BLOCK + 1;
-localparam STRM4_NBLOCKS = STRM4_END_BLOCK - STRM4_BLOCK + 1;
-localparam STRM5_NBLOCKS = STRM5_END_BLOCK - STRM5_BLOCK + 1;
-
-//TODO: check that memory width is equal to the widest stream
-//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?)
-initial begin
- if((NSTREAMS < 1) | (NSTREAMS > 6)) begin
- $display("Invalid setting for NSTREAMS, please set in range [1,6]");
- $finish();
- end
-end
-
-//invert reset
-wire rst;
-assign rst = ~aresetn;
-
-//WARNING: pipeline depth is larger than the number of streams per port so we have in-flight writes that may see not-ready when they get executed
-//solution: use prog-full to make sure we have an equal number of free slots in the stream to the read pipeline depth
-
-reg [$clog2(MEM_DEPTH)-1:0] strm0_addr = STRM0_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm1_addr = STRM1_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm2_addr = STRM2_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm3_addr = STRM3_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm4_addr = STRM4_OFFSET;
-reg [$clog2(MEM_DEPTH)-1:0] strm5_addr = STRM5_OFFSET;
-
-reg strm0_incr_en;
-reg strm1_incr_en;
-reg strm2_incr_en;
-reg strm3_incr_en;
-reg strm4_incr_en;
-reg strm5_incr_en;
-
-wire strm0_rst;
-wire strm1_rst;
-wire strm2_rst;
-wire strm3_rst;
-wire strm4_rst;
-wire strm5_rst;
-
-reg strm0_ready;
-reg strm1_ready;
-reg strm2_ready;
-reg strm3_ready;
-reg strm4_ready;
-reg strm5_ready;
-
-//arbiter: work on one stream at a time
-//multiplex each port between (up to) half of the streams
-reg [1:0] current_stream_porta = 0;
-reg [1:0] current_stream_portb = 0;
-
-always @(posedge aclk) begin
- if(rst)
- current_stream_porta <= 0;
- else case(current_stream_porta)
- 0: current_stream_porta <= strm2_ready ? 1 : strm4_ready ? 2 : 0;
- 1: current_stream_porta <= strm4_ready ? 2 : strm0_ready ? 0 : 1;
- 2: current_stream_porta <= strm0_ready ? 0 : strm2_ready ? 1 : 2;
- endcase
- if(rst)
- current_stream_portb <= 0;
- else case(current_stream_portb)
- 0: current_stream_portb <= strm3_ready ? 1 : strm5_ready ? 2 : 0;
- 1: current_stream_portb <= strm5_ready ? 2 : strm1_ready ? 0 : 1;
- 2: current_stream_portb <= strm1_ready ? 0 : strm3_ready ? 1 : 2;
- endcase
-end
-
-always @(posedge aclk) begin
- if(rst) begin
- strm0_incr_en <= 0;
- strm1_incr_en <= 0;
- strm2_incr_en <= 0;
- strm3_incr_en <= 0;
- strm4_incr_en <= 0;
- strm5_incr_en <= 0;
- end else begin
- strm0_incr_en <= (current_stream_porta == 0) & strm0_ready;
- strm1_incr_en <= (current_stream_portb == 0) & strm1_ready;
- strm2_incr_en <= (current_stream_porta == 1) & strm2_ready;
- strm3_incr_en <= (current_stream_portb == 1) & strm3_ready;
- strm4_incr_en <= (current_stream_porta == 2) & strm4_ready;
- strm5_incr_en <= (current_stream_portb == 2) & strm5_ready;
- end
-end
-
-assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));
-assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
-assign strm2_rst = strm2_incr_en & (strm2_addr == (STRM2_OFFSET + STRM2_DEPTH-1));
-assign strm3_rst = strm3_incr_en & (strm3_addr == (STRM3_OFFSET + STRM3_DEPTH-1));
-assign strm4_rst = strm4_incr_en & (strm4_addr == (STRM4_OFFSET + STRM4_DEPTH-1));
-assign strm5_rst = strm5_incr_en & (strm5_addr == (STRM5_OFFSET + STRM5_DEPTH-1));
-
-always @(posedge aclk) begin
- strm0_ready <= ~m_axis_0_afull;
- strm1_ready <= ~m_axis_1_afull & (NSTREAMS >= 2);
- strm2_ready <= ~m_axis_2_afull & (NSTREAMS >= 3);
- strm3_ready <= ~m_axis_3_afull & (NSTREAMS >= 4);
- strm4_ready <= ~m_axis_4_afull & (NSTREAMS >= 5);
- strm5_ready <= ~m_axis_5_afull & (NSTREAMS >= 6);
-end
-
-//one address counter per stream; more LUTs but keeps routing short and local
-always @(posedge aclk) begin
- if(strm0_rst | rst)
- strm0_addr <= STRM0_OFFSET;
- else if(strm0_incr_en)
- strm0_addr <= strm0_addr + 1;
- if(strm1_rst | rst)
- strm1_addr <= STRM1_OFFSET;
- else if(strm1_incr_en)
- strm1_addr <= strm1_addr + 1;
- if(strm2_rst | rst)
- strm2_addr <= STRM2_OFFSET;
- else if(strm2_incr_en)
- strm2_addr <= strm2_addr + 1;
- if(strm3_rst | rst)
- strm3_addr <= STRM3_OFFSET;
- else if(strm3_incr_en)
- strm3_addr <= strm3_addr + 1;
- if(strm4_rst | rst)
- strm4_addr <= STRM4_OFFSET;
- else if(strm4_incr_en)
- strm4_addr <= strm4_addr + 1;
- if(strm5_rst | rst)
- strm5_addr <= STRM5_OFFSET;
- else if(strm5_incr_en)
- strm5_addr <= strm5_addr + 1;
-end
-
-reg [$clog2(MEM_DEPTH)-1:0] addra;
-wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqa;
-
-reg [$clog2(MEM_DEPTH)-1:0] addrb;
-wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqb;
-
-wire [NMEMBLOCKS-1:0] we;
-
-reg [1:0] addr_select_porta;
-reg [1:0] addr_select_portb;
-
-//multiplex addresses of various streams into address ports of memory
-always @(posedge aclk) begin
- addr_select_porta <= current_stream_porta;
- case(addr_select_porta)
- 0: addra <= strm0_addr;
- 1: addra <= strm2_addr;
- 2: addra <= strm4_addr;
- endcase
- addr_select_portb <= current_stream_portb;
- case(addr_select_portb)
- 0: addrb <= strm1_addr;
- 1: addrb <= strm3_addr;
- 2: addrb <= strm5_addr;
- endcase
-end
-
-genvar g;
-generate for(g=0; g<NMEMBLOCKS; g=g+1) begin: blockports
-
-assign we[g] = (CONFIG_EN == 1) & config_ce & config_we & (config_address[31:BLOCKADRWIDTH] == g);
-
-ramb18_wf_dualport
-#(
- .ID(g),
- .DWIDTH(MEM_WIDTH),
- .AWIDTH(BLOCKADRWIDTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE)
-)
-ram
-(
- .clk(aclk),
-
- .wea(we[g]),
- .ena(1'b1),
- .enqa(1'b1),
- .addra(we[g] ? config_address[BLOCKADRWIDTH-1:0] : addra[BLOCKADRWIDTH-1:0]),
- .wdataa(config_d0),
- .rdqa(rdqa[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH]),
-
- .web(1'b0),
- .enb(1'b1),
- .enqb(1'b1),
- .addrb(addrb[BLOCKADRWIDTH-1:0]),
- .wdatab('d0),
- .rdqb(rdqb[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH])
-);
-
-end
-endgenerate
-
-integer i;
-
-generate if(NMEMBLOCKS > 1) begin: multiblock
-
-wire [MEM_WIDTH-1:0] rdqmux[5:0];
-
-reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblocka[2:0];
-reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblockb[2:0];
-
-always @(posedge aclk) begin
- rdblocka[0] <= addra[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
- rdblockb[0] <= addrb[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
- for(i=0; i<2; i=i+1) begin
- rdblocka[i+1] <= rdblocka[i];
- rdblockb[i+1] <= rdblockb[i];
- end
-end
-
-if(NSTREAMS >= 1) begin: en_strm0
- if(STRM0_MUX == 1) begin: mux0
- mux #(STRM0_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM0_BLOCK+STRM0_NBLOCKS)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH],rdqmux[0],rdblocka[1] - STRM0_BLOCK);
- end else begin: nomux0
- assign rdqmux[0] = rdqa[(STRM0_BLOCK+1)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH];
- end
- assign m_axis_0_tdata = rdqmux[0][STRM0_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 2) begin: en_strm1
- if(STRM1_MUX == 1) begin: mux1
- mux #(STRM1_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM1_BLOCK+STRM1_NBLOCKS)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH],rdqmux[1],rdblockb[1] - STRM1_BLOCK);
- end else begin: nomux1
- assign rdqmux[1] = rdqb[(STRM1_BLOCK+1)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH];
- end
- assign m_axis_1_tdata = rdqmux[1][STRM1_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 3) begin: en_strm2
- if(STRM2_MUX == 1) begin: mux2
- mux #(STRM2_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM2_BLOCK+STRM2_NBLOCKS)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH],rdqmux[2],rdblocka[1] - STRM2_BLOCK);
- end else begin: nomux2
- assign rdqmux[2] = rdqa[(STRM2_BLOCK+1)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH];
- end
- assign m_axis_2_tdata = rdqmux[2][STRM2_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 4) begin: en_strm3
- if(STRM3_MUX == 1) begin: mux3
- mux #(STRM3_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM3_BLOCK+STRM3_NBLOCKS)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH],rdqmux[3],rdblockb[1] - STRM3_BLOCK);
- end else begin: nomux3
- assign rdqmux[3] = rdqb[(STRM3_BLOCK+1)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH];
- end
- assign m_axis_3_tdata = rdqmux[3][STRM3_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 5) begin: en_strm4
- if(STRM4_MUX == 1) begin: mux4
- mux #(STRM4_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM4_BLOCK+STRM4_NBLOCKS)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH],rdqmux[4],rdblocka[1] - STRM4_BLOCK);
- end else begin: nomux4
- assign rdqmux[4] = rdqa[(STRM4_BLOCK+1)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH];
- end
- assign m_axis_4_tdata = rdqmux[4][STRM4_WIDTH-1:0];
-end
-
-if(NSTREAMS >= 6) begin: en_strm5
- if(STRM5_MUX == 1) begin: mux5
- mux #(STRM5_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM5_BLOCK+STRM5_NBLOCKS)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH],rdqmux[5],rdblockb[1] - STRM5_BLOCK);
- end else begin: nomux5
- assign rdqmux[5] = rdqb[(STRM5_BLOCK+1)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH];
- end
- assign m_axis_5_tdata = rdqmux[5][STRM5_WIDTH-1:0];
-end
-
-end else begin: singleblock
-
-if(NSTREAMS >= 1) begin: en_strm0_direct
- assign m_axis_0_tdata = rdqa[STRM0_WIDTH-1:0];
-end
-if(NSTREAMS >= 2) begin: en_strm1_direct
- assign m_axis_1_tdata = rdqb[STRM1_WIDTH-1:0];
-end
-if(NSTREAMS >= 3) begin: en_strm2_direct
- assign m_axis_2_tdata = rdqa[STRM2_WIDTH-1:0];
-end
-if(NSTREAMS >= 4) begin: en_strm3_direct
- assign m_axis_3_tdata = rdqb[STRM3_WIDTH-1:0];
-end
-if(NSTREAMS >= 5) begin: en_strm4_direct
- assign m_axis_4_tdata = rdqa[STRM4_WIDTH-1:0];
-end
-if(NSTREAMS >= 6) begin: en_strm5_direct
- assign m_axis_5_tdata = rdqb[STRM5_WIDTH-1:0];
-end
-
-end
-endgenerate
-
-//output to AXI Streams
-reg tvalid_pipe0[2:0];
-reg tvalid_pipe1[2:0];
-reg tvalid_pipe2[2:0];
-reg tvalid_pipe3[2:0];
-reg tvalid_pipe4[2:0];
-reg tvalid_pipe5[2:0];
-
-assign m_axis_0_tvalid = tvalid_pipe0[2];
-assign m_axis_1_tvalid = tvalid_pipe1[2];
-assign m_axis_2_tvalid = tvalid_pipe2[2];
-assign m_axis_3_tvalid = tvalid_pipe3[2];
-assign m_axis_4_tvalid = tvalid_pipe4[2];
-assign m_axis_5_tvalid = tvalid_pipe5[2];
-
-
-always @(posedge aclk) begin
- tvalid_pipe0[0] <= strm0_incr_en;
- tvalid_pipe1[0] <= strm1_incr_en;
- tvalid_pipe2[0] <= strm2_incr_en;
- tvalid_pipe3[0] <= strm3_incr_en;
- tvalid_pipe4[0] <= strm4_incr_en;
- tvalid_pipe5[0] <= strm5_incr_en;
- for(i=0; i<2; i=i+1) begin: srl
- tvalid_pipe0[i+1] <= tvalid_pipe0[i];
- tvalid_pipe1[i+1] <= tvalid_pipe1[i];
- tvalid_pipe2[i+1] <= tvalid_pipe2[i];
- tvalid_pipe3[i+1] <= tvalid_pipe3[i];
- tvalid_pipe4[i+1] <= tvalid_pipe4[i];
- tvalid_pipe5[i+1] <= tvalid_pipe5[i];
- end
-end
-
-//dummy read, for now
-assign config_q0 = 0;
-assign config_rack = config_ce & ~config_we;
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/memstream_singleblock.v b/finn-rtllib/memstream/hdl/memstream_singleblock.v
deleted file mode 100644
index c9b8770aaa58dc3355bc259e5c5fece702125490..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/memstream_singleblock.v
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- Implements a lightweight streamer for up to 2 streams in a single block of memory
-*/
-
-module memstream_singleblock
-#(
- parameter CONFIG_EN = 1,
- parameter NSTREAMS = 2,//1 up to 2
-
- parameter MEM_DEPTH = 512,
- parameter MEM_WIDTH = 32,
- parameter MEM_INIT = "./",
- parameter RAM_STYLE = "auto",
-
- //widths per stream
- parameter STRM0_WIDTH = 32,
- parameter STRM1_WIDTH = 32,
-
- //depths per stream
- parameter STRM0_DEPTH = 256,
- parameter STRM1_DEPTH = 256,
-
- //offsets for each stream
- parameter STRM0_OFFSET = 0,
- parameter STRM1_OFFSET = 256
-)
-
-(
- input aclk,
- input aresetn,
-
- //optional configuration interface compatible with ap_memory
- input [31:0] config_address,
- input config_ce,
- input config_we,
- input [MEM_WIDTH-1:0] config_d0,
- output [MEM_WIDTH-1:0] config_q0,
- output config_rack,
-
- //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
- input m_axis_0_tready,
- output m_axis_0_tvalid,
- output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
-
- input m_axis_1_tready,
- output m_axis_1_tvalid,
- output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata
-
-);
-
-
-//TODO: check that memory width is equal to the widest stream
-//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?)
-initial begin
- if((NSTREAMS < 1) | (NSTREAMS > 2)) begin
- $display("Invalid setting for NSTREAMS, please set in range [1,2]");
- $finish();
- end
-end
-
-//invert reset
-wire rst;
-assign rst = ~aresetn;
-
-wire strm0_incr_en;
-wire strm1_incr_en;
-
-assign strm0_incr_en = m_axis_0_tready | ~m_axis_0_tvalid;
-assign strm1_incr_en = m_axis_1_tready | ~m_axis_1_tvalid;
-
-reg rack_shift[1:0];
-
-generate
-if(MEM_DEPTH > 1) begin: use_ram
-
-//calculate width of memory address, with a minimum of 1 bit
-localparam BLOCKADRWIDTH = $clog2(MEM_DEPTH);
-
-reg [BLOCKADRWIDTH-1:0] strm0_addr = STRM0_OFFSET;
-wire strm0_rst;
-assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));
-
-//one address counter per stream; more LUTs but keeps routing short and local
-always @(posedge aclk) begin
- if(strm0_rst | rst)
- strm0_addr <= STRM0_OFFSET;
- else if(strm0_incr_en)
- strm0_addr <= strm0_addr + 1;
-end
-
-if(NSTREAMS == 1) begin: sdp
-
-ramb18_sdp
-#(
- .ID(0),
- .DWIDTH(MEM_WIDTH),
- .AWIDTH(BLOCKADRWIDTH),
- .DEPTH(MEM_DEPTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE)
-)
-ram
-(
- .clk(aclk),
-
- .ena(config_ce),
- .wea(config_we),
- .addra(config_address[BLOCKADRWIDTH-1:0]),
- .wdataa(config_d0),
-
- .enb(strm0_incr_en | config_ce),
- .enqb(strm0_incr_en | rack_shift[0]),
- .addrb(config_ce ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
- .rdqb(m_axis_0_tdata)
-);
-
-
-end else begin: tdp
-
-reg [BLOCKADRWIDTH-1:0] strm1_addr = STRM1_OFFSET;
-wire strm1_rst;
-assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
-
-always @(posedge aclk) begin
- if(strm1_rst | rst)
- strm1_addr <= STRM1_OFFSET;
- else if(strm1_incr_en)
- strm1_addr <= strm1_addr + 1;
-end
-
-ramb18_wf_dualport
-#(
- .ID(0),
- .DWIDTH(MEM_WIDTH),
- .AWIDTH(BLOCKADRWIDTH),
- .DEPTH(MEM_DEPTH),
- .MEM_INIT(MEM_INIT),
- .RAM_STYLE(RAM_STYLE)
-)
-ram
-(
- .clk(aclk),
-
- .wea(config_we),
- .ena(strm0_incr_en | config_ce),
- .enqa(strm0_incr_en | config_ce_r),
- .addra(config_we ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
- .wdataa(config_d0),
- .rdqa(m_axis_0_tdata),
-
- .web(1'b0),
- .enb(strm1_incr_en),
- .enqb(strm1_incr_en),
- .addrb(strm1_addr),
- .wdatab('d0),
- .rdqb(m_axis_1_tdata)
-);
-
-end
-
-end else begin: bypass
-
-reg [MEM_WIDTH-1:0] singleval[0:0];
-initial begin
- `ifdef SYNTHESIS
- $readmemh({MEM_INIT,"memblock_synth_0.dat"}, singleval, 0, 0);
- `else
- $readmemh({MEM_INIT,"memblock_sim_0.dat"}, singleval, 0, 0);
- `endif
-end
-
-always @(posedge aclk)
- if(config_ce & config_we)
- singleval[0] <= config_d0;
-
-assign m_axis_0_tdata = singleval[0];
-assign m_axis_1_tdata = singleval[0];
-
-end
-endgenerate
-
-//signal valid after 2 tready cycles after initialization
-//then stay valid
-reg [1:0] tvalid_pipe0 = 2'd0;
-reg [1:0] tvalid_pipe1 = 2'd0;
-
-assign m_axis_0_tvalid = tvalid_pipe0[1];
-assign m_axis_1_tvalid = tvalid_pipe1[1];
-
-always @(posedge aclk) begin
- if(rst) begin
- tvalid_pipe0 <= 0;
- end else if(strm0_incr_en) begin
- tvalid_pipe0[0] <= 1;
- tvalid_pipe0[1] <= tvalid_pipe0[0];
- end
-end
-
-always @(posedge aclk) begin
- if(rst) begin
- tvalid_pipe1 <= 0;
- end else if(strm1_incr_en) begin
- tvalid_pipe1[0] <= 1;
- tvalid_pipe1[1] <= tvalid_pipe1[0];
- end
-end
-
-always @(posedge aclk) begin
- rack_shift[0] <= config_ce & ~config_we;
- rack_shift[1] <= rack_shift[0];
-end
-
-assign config_rack = rack_shift[1];
-assign config_q0 = m_axis_0_tdata;
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/mux.v b/finn-rtllib/memstream/hdl/mux.v
deleted file mode 100644
index f7087f9735771a73aa532ae19baf18569e9de663..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/mux.v
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module mux
-#(
- parameter NINPUTS = 1,
- parameter WIDTH = 16
-)
-(
- input [NINPUTS*WIDTH-1:0] in,
- output [WIDTH-1:0] out,
- input [$clog2(NINPUTS)-1:0] sel
-);
-
-assign out = in >> (sel*WIDTH);
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/ramb18_sdp.v b/finn-rtllib/memstream/hdl/ramb18_sdp.v
deleted file mode 100644
index 8d2fbf9a988c0e9702e1ed83f2b4e79efb1c5a85..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/ramb18_sdp.v
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module ramb18_sdp
-#(
- parameter ID = 0,
- parameter DWIDTH = 18,
- parameter AWIDTH = 10,
- parameter DEPTH = 2**AWIDTH,
- parameter MEM_INIT = "",
- parameter RAM_STYLE = "auto"
-)
-(
- input clk,
-
- input ena,
- input wea,
- input [AWIDTH-1:0] addra,
- input [DWIDTH-1:0] wdataa,
-
- input enb,
- input enqb,
- input [AWIDTH-1:0] addrb,
- output reg [DWIDTH-1:0] rdqb
-);
-
-(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:DEPTH-1];
-reg [DWIDTH-1:0] rdatab;
-
-`ifdef SYNTHESIS
-reg [7:0] idx = ID;
-`else
-reg [15:0] idx;
-`endif
-
-//initialize memory
-initial begin
- //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT
- //ID can go up to 99
- if (ID < 0 && ID > 99) begin
- $display("ID out of range [0-99]");
- $finish();
- end
- //MEM_INIT path must be terminated by /
- `ifdef SYNTHESIS
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_synth_",idx+8'd48,".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_synth_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, DEPTH-1);
- `else
- $sformat(idx,"%0d",ID);
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_sim_",idx[7:0],".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_sim_",idx,".dat"}, mem, 0, DEPTH-1);
- `endif
-end
-
-//memory ports, with output pipeline register
-always @(posedge clk) begin
- if(wea)
- mem[addra] <= wdataa;
- if(enb)
- rdatab <= mem[addrb];
- if(enqb)
- rdqb <= rdatab;
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v b/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v
deleted file mode 100644
index c7850106ae4cad21f1230477ee86062411e531c8..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-module ramb18_wf_dualport
-#(
- parameter ID = 0,
- parameter DWIDTH = 18,
- parameter AWIDTH = 10,
- parameter DEPTH = 2**AWIDTH,
- parameter MEM_INIT = "",
- parameter RAM_STYLE = "auto"
-)
-(
- input clk,
-
- input wea,
- input ena,
- input enqa,
- input [AWIDTH-1:0] addra,
- input [DWIDTH-1:0] wdataa,
- output reg [DWIDTH-1:0] rdqa,
-
- input web,
- input enb,
- input enqb,
- input [AWIDTH-1:0] addrb,
- input [DWIDTH-1:0] wdatab,
- output reg [DWIDTH-1:0] rdqb
-);
-
-(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:DEPTH-1];
-reg [DWIDTH-1:0] rdataa;
-reg [DWIDTH-1:0] rdatab;
-
-`ifdef SYNTHESIS
-reg [7:0] idx = ID;
-`else
-reg [15:0] idx;
-`endif
-
-//initialize memory
-initial begin
- //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT
- //ID can go up to 99
- if (ID < 0 && ID > 99) begin
- $display("ID out of range [0-99]");
- $finish();
- end
- //MEM_INIT path must be terminated by /
- `ifdef SYNTHESIS
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_",idx+8'd48,".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, DEPTH-1);
- `else
- $sformat(idx,"%0d",ID);
- if (ID < 10)
- $readmemh({MEM_INIT,"memblock_",idx[7:0],".dat"}, mem, 0, DEPTH-1);
- else
- $readmemh({MEM_INIT,"memblock_",idx,".dat"}, mem, 0, DEPTH-1);
- `endif
-end
-
-//memory ports, with output pipeline register
-always @(posedge clk) begin
- if(ena) begin
- if(wea)
- mem[addra] <= wdataa;
- rdataa <= mem[addra];
- end
- if(enqa)
- rdqa <= rdataa;
-end
-always @(posedge clk) begin
- if(enb) begin
- if(web)
- mem[addrb] <= wdatab;
- rdatab <= mem[addrb];
- end
- if(enqb)
- rdqb <= rdatab;
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/sim/gen_memblocks.sh b/finn-rtllib/memstream/sim/gen_memblocks.sh
deleted file mode 100644
index b6e6b656ad1ea7846666108a1d4b79eae295490f..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/gen_memblocks.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/bash
-
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-NLINES=`cat $1 | wc -l`
-NBLOCKS=$(( ($NLINES + 1023) / 1024 ))
-rm memblock_*.dat
-
-for (( i=0; i<$NBLOCKS; i++ ))
-do
- START=$(( 1 + $i * 1024 ))
- tail -n +$START $1 | head -n 1024 >> memblock_$i.dat
-done
diff --git a/finn-rtllib/memstream/sim/golden.dat b/finn-rtllib/memstream/sim/golden.dat
deleted file mode 100644
index 1466271bcab961f742e242aea4241a4ffad02828..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/golden.dat
+++ /dev/null
@@ -1,9216 +0,0 @@
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diff --git a/finn-rtllib/memstream/sim/memstream_tb.sv b/finn-rtllib/memstream/sim/memstream_tb.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4b2e850415e88fdf820931e2d6b75f6aac2f7267
--- /dev/null
+++ b/finn-rtllib/memstream/sim/memstream_tb.sv
@@ -0,0 +1,212 @@
+/**
+ * Copyright (c) 2023, Xilinx
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of FINN nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Thomas B. Preußer <thomas.preusser@amd.com>
+ */
+
+module memstream_tb;
+ localparam int unsigned DEPTH = 256;
+ localparam int unsigned DATA_WIDTH = 32;
+
+ // Global Control
+ logic clk = 0;
+ always #5ns clk = !clk;
+ logic rst;
+
+ // Configuration Interface
+ logic [31:0] config_address;
+ logic config_ce;
+ logic config_we;
+ logic [DATA_WIDTH-1:0] config_d0;
+ uwire config_rack;
+ uwire [DATA_WIDTH-1:0] config_q0;
+
+ // Streamed Output
+ logic ordy;
+ uwire ovld;
+ uwire [DATA_WIDTH-1:0] odat;
+
+ initial begin
+ config_address = 'x;
+ config_ce = 0;
+ config_we = 0;
+ config_d0 = 'x;
+
+ ordy = 0;
+
+ rst = 1;
+ repeat(16) @(posedge clk);
+ rst <= 0;
+
+ // Write Parameters
+ config_ce <= 1;
+ config_we <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ config_address <= i;
+ config_d0 <= i;
+ @(posedge clk);
+ end
+ config_address <= 'x;
+ config_ce <= 0;
+ config_we <= 0;
+ config_d0 <= 'x;
+
+ rst <= 1;
+ @(posedge clk);
+ rst <= 0;
+
+ // One Round of Stream Read
+ ordy <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ @(posedge clk iff ovld);
+ assert(odat == i) else begin
+ $error("Unexpected output: %0d instead of %0d", odat, i);
+ $stop;
+ end
+ end
+ ordy <= 0;
+
+ // Full Parameter Readback
+ if(1) begin
+ automatic logic [DATA_WIDTH-1:0] Q[$] = {};
+
+ config_ce <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ config_address <= i;
+ @(posedge clk);
+ Q.push_back(i);
+
+ if(config_rack) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+ end
+ config_address <= 'x;
+ config_ce <= 0;
+
+ while(Q.size) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+
+ @(posedge clk iff config_rack);
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+ end
+
+ repeat(6) @(posedge clk);
+
+ // Another Round of Stream Read
+ ordy <= 1;
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ @(posedge clk iff ovld);
+ assert(odat == i) else begin
+ $error("Unexpected output: %0d instead of %0d", odat, i);
+ $stop;
+ end
+ end
+ ordy <= 0;
+
+ // A Round of Stream Read with intermittent Read Backs
+ if(1) begin
+ automatic logic [DATA_WIDTH-1:0] Q[$] = {};
+
+ for(int unsigned i = 0; i < DEPTH; i++) begin
+ do begin
+ // Randomly delayed Readiness
+ if($urandom()%5 != 0) ordy <= 1;
+
+ // Issue and Check Random Read Backs
+ if($urandom()%9 == 0) begin
+ automatic int unsigned addr = $urandom() % DEPTH;
+ config_ce <= 1;
+ config_address <= addr;
+ Q.push_back(addr);
+ end
+ @(posedge clk);
+ config_ce <= 0;
+ config_address <= 'x;
+
+ if(config_rack) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+
+ end while(!ovld || !ordy);
+ ordy <= 0;
+
+ assert(odat == i) else begin
+ $error("Unexpected output: %0d instead of %0d", odat, i);
+ $stop;
+ end
+ end
+
+ while(Q.size) begin
+ automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front();
+
+ @(posedge clk iff config_rack);
+ assert(config_q0 == exp) else begin
+ $error("Readback mismatch: %0d instead of %0d", config_q0, exp);
+ $stop;
+ end
+ end
+ end
+ ordy <= 0;
+
+ repeat(2) @(posedge clk);
+ $display("Test completed.");
+ $finish;
+ end
+
+ memstream #(
+ .DEPTH(DEPTH),
+ .WIDTH(DATA_WIDTH)
+ ) dut (
+ .clk, .rst,
+
+ .config_address,
+ .config_ce,
+ .config_we,
+ .config_d0,
+ .config_q0,
+ .config_rack,
+
+ .ordy,
+ .ovld,
+ .odat
+ );
+
+endmodule : memstream_tb
diff --git a/finn-rtllib/memstream/sim/tb_memstream.v b/finn-rtllib/memstream/sim/tb_memstream.v
deleted file mode 100644
index ad3efad5bd70c37a860ddb0ec5bff1c2e72c15f0..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/tb_memstream.v
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-`timescale 1ns/10ps
-
-module tb_memstream;
-
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
-parameter CONFIG_EN = 1;
-parameter NSTREAMS = 4;//1 up to 6
-
-parameter MEM_DEPTH = 9216;
-parameter MEM_WIDTH = 32;
-parameter MEM_INIT = "./";
-parameter MEM_CHECK = "golden.dat";
-
-//widths per stream
-parameter STRM0_WIDTH = 32;
-parameter STRM1_WIDTH = 32;
-parameter STRM2_WIDTH = 32;
-parameter STRM3_WIDTH = 32;
-parameter STRM4_WIDTH = 1;
-parameter STRM5_WIDTH = 1;
-
-//depths per stream
-parameter STRM0_DEPTH = 2304;
-parameter STRM1_DEPTH = 2304;
-parameter STRM2_DEPTH = 2304;
-parameter STRM3_DEPTH = 2304;
-parameter STRM4_DEPTH = 1;
-parameter STRM5_DEPTH = 1;
-
-//offsets for each stream
-parameter STRM0_OFFSET = 0;
-parameter STRM1_OFFSET = 2304;
-parameter STRM2_OFFSET = 4608;
-parameter STRM3_OFFSET = 6912;
-parameter STRM4_OFFSET = 0;
-parameter STRM5_OFFSET = 0;
-
-
-reg clk;
-reg rst;
-
-reg [31:0] config_address = 0;
-reg config_ce = 0;
-reg config_we = 0;
-reg [31:0] config_d0 = 0;
-wire [31:0] config_q0;
-
-//multiple wire AXI Streams
-reg m_axis_0_afull;
-reg m_axis_0_tready;
-wire m_axis_0_tvalid;
-wire [STRM0_WIDTH-1:0] m_axis_0_tdata;
-
-reg m_axis_1_afull;
-reg m_axis_1_tready;
-wire m_axis_1_tvalid;
-wire [STRM1_WIDTH-1:0] m_axis_1_tdata;
-
-reg m_axis_2_afull;
-reg m_axis_2_tready;
-wire m_axis_2_tvalid;
-wire [STRM2_WIDTH-1:0] m_axis_2_tdata;
-
-reg m_axis_3_afull;
-reg m_axis_3_tready;
-wire m_axis_3_tvalid;
-wire [STRM3_WIDTH-1:0] m_axis_3_tdata;
-
-reg m_axis_4_afull;
-reg m_axis_4_tready;
-wire m_axis_4_tvalid;
-wire [STRM4_WIDTH-1:0] m_axis_4_tdata;
-
-reg m_axis_5_afull;
-reg m_axis_5_tready;
-wire m_axis_5_tvalid;
-wire [STRM5_WIDTH-1:0] m_axis_5_tdata;
-
-reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0];
-integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5;
-integer done = 0;
-reg [5:0] rng;
-
-//clock
-initial begin
- clk = 0;
- forever #5 clk = ~clk;
-end
-
-initial begin
- rst = 1;
- config_ce = 0;
- m_axis_0_afull = 0;
- m_axis_1_afull = 0;
- m_axis_2_afull = 0;
- m_axis_3_afull = 0;
- m_axis_4_afull = 0;
- m_axis_5_afull = 0;
- m_axis_0_tready = 1;
- m_axis_1_tready = 1;
- m_axis_2_tready = 1;
- m_axis_3_tready = 1;
- m_axis_4_tready = 1;
- m_axis_5_tready = 1;
- repeat(100) @(negedge clk);
- rst = 0;
- #100
- fork
- begin
- $display("Starting to generate random AFULL");
- while(~done) begin
- rng = $random;
- m_axis_0_afull = rng[0];
- m_axis_1_afull = rng[1];
- m_axis_2_afull = rng[2];
- m_axis_3_afull = rng[3];
- m_axis_4_afull = rng[4];
- m_axis_5_afull = rng[5];
- @(negedge clk);
- end
- end
- join
-end
-
-
-//DUT
-memstream
-#(
- CONFIG_EN,
- NSTREAMS,
- MEM_DEPTH,
- MEM_WIDTH,
- MEM_INIT,
-
- //widths per stream
- STRM0_WIDTH,
- STRM1_WIDTH,
- STRM2_WIDTH,
- STRM3_WIDTH,
- STRM4_WIDTH,
- STRM5_WIDTH,
-
- //depths per stream
- STRM0_DEPTH,
- STRM1_DEPTH,
- STRM2_DEPTH,
- STRM3_DEPTH,
- STRM4_DEPTH,
- STRM5_DEPTH,
-
- //offsets for each stream
- STRM0_OFFSET,
- STRM1_OFFSET,
- STRM2_OFFSET,
- STRM3_OFFSET,
- STRM4_OFFSET,
- STRM5_OFFSET
-)
-dut
-(
- clk,
- ~rst,
-
- //optional AXI-Lite interface
- config_address,
- config_ce,
- config_we,
- config_d0,
- config_q0,
-
- //multiple output AXI Streams
- m_axis_0_afull,
- m_axis_0_tready,
- m_axis_0_tvalid,
- m_axis_0_tdata,
-
- m_axis_1_afull,
- m_axis_1_tready,
- m_axis_1_tvalid,
- m_axis_1_tdata,
-
- m_axis_2_afull,
- m_axis_2_tready,
- m_axis_2_tvalid,
- m_axis_2_tdata,
-
- m_axis_3_afull,
- m_axis_3_tready,
- m_axis_3_tvalid,
- m_axis_3_tdata,
-
- m_axis_4_afull,
- m_axis_4_tready,
- m_axis_4_tvalid,
- m_axis_4_tdata,
-
- m_axis_5_afull,
- m_axis_5_tready,
- m_axis_5_tvalid,
- m_axis_5_tdata
-
-
-);
-
-//stream checkers
-initial begin
- ptr0 = STRM0_OFFSET;
- ptr1 = STRM1_OFFSET;
- ptr2 = STRM2_OFFSET;
- ptr3 = STRM3_OFFSET;
- ptr4 = STRM4_OFFSET;
- ptr5 = STRM5_OFFSET;
- fork
- //check stream 0
- begin
- $display("Starting stream 0 checker");
- while(~done & (NSTREAMS > 0)) begin
- @(negedge clk);
- if(m_axis_0_tvalid) begin
- if(m_axis_0_tdata != golden[ptr0]) begin
- $display("Mismatch on stream 0");
- $stop();
- end
- //increment pointer
- ptr0 = ptr0 + 1;
- //rewind pointer if it's reached end
- if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH))
- ptr0 = STRM0_OFFSET;
- end
- end
- end
- //check stream 1
- begin
- $display("Starting stream 1 checker");
- while(~done & (NSTREAMS > 1)) begin
- @(negedge clk);
- if(m_axis_1_tvalid) begin
- if(m_axis_1_tdata != golden[ptr1]) begin
- $display("Mismatch on stream 1");
- $stop();
- end
- //increment pointer
- ptr1 = ptr1 + 1;
- //rewind pointer if it's reached end
- if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH))
- ptr1 = STRM1_OFFSET;
- end
- end
- end
-
- //check stream 2
- begin
- $display("Starting stream 2 checker");
- while(~done & (NSTREAMS > 2)) begin
- @(negedge clk);
- if(m_axis_2_tvalid) begin
- if(m_axis_2_tdata != golden[ptr2]) begin
- $display("Mismatch on stream 2");
- $stop();
- end
- //increment pointer
- ptr2 = ptr2 + 1;
- //rewind pointer if it's reached end
- if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH))
- ptr2 = STRM2_OFFSET;
- end
- end
- end
- //check stream 3
- begin
- $display("Starting stream 3 checker");
- while(~done & (NSTREAMS > 3)) begin
- @(negedge clk);
- if(m_axis_3_tvalid) begin
- if(m_axis_3_tdata != golden[ptr3]) begin
- $display("Mismatch on stream 3");
- $stop();
- end
- //increment pointer
- ptr3 = ptr3 + 1;
- //rewind pointer if it's reached end
- if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH))
- ptr3 = STRM3_OFFSET;
- end
- end
- end
- //check stream 4
- begin
- $display("Starting stream 4 checker");
- while(~done & (NSTREAMS > 4)) begin
- @(negedge clk);
- if(m_axis_4_tvalid) begin
- if(m_axis_4_tdata != golden[ptr4]) begin
- $display("Mismatch on stream 4");
- $stop();
- end
- //increment pointer
- ptr4 = ptr4 + 1;
- //rewind pointer if it's reached end
- if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH))
- ptr4 = STRM4_OFFSET;
- end
- end
- end
- //check stream 5
- begin
- $display("Starting stream 5 checker");
- while(~done & (NSTREAMS > 5)) begin
- @(negedge clk);
- if(m_axis_5_tvalid) begin
- if(m_axis_5_tdata != golden[ptr5]) begin
- $display("Mismatch on stream 5");
- $stop();
- end
- //increment pointer
- ptr5 = ptr5 + 1;
- //rewind pointer if it's reached end
- if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH))
- ptr5 = STRM5_OFFSET;
- end
- end
- end
- join
-end
-
-initial begin
- done = 0;
- $readmemh(MEM_CHECK,golden);
-// $dumpfile("wave.vcd");
-// $dumpvars(0,tb_memstream);
- @(negedge rst);
- #10000000
- $display("Test done!");
- done = 1;
- #1000
- $finish();
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/sim/tb_memstream_writes.v b/finn-rtllib/memstream/sim/tb_memstream_writes.v
deleted file mode 100644
index c66807454b9a7f8ff7ab7008a504938740fb03a0..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/tb_memstream_writes.v
+++ /dev/null
@@ -1,486 +0,0 @@
-/*
- Copyright (c) 2020, Xilinx
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- * Neither the name of FINN nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-`timescale 1ns/10ps
-
-module tb_memstream_writes;
-
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
-parameter CONFIG_EN = 1;
-parameter NSTREAMS = 2;//1 up to 6
-
-parameter MEM_DEPTH = 40;
-parameter MEM_WIDTH = 70;
-
-//widths per stream
-parameter STRM0_WIDTH = 70;
-parameter STRM1_WIDTH = 32;
-parameter STRM2_WIDTH = 32;
-parameter STRM3_WIDTH = 32;
-parameter STRM4_WIDTH = 1;
-parameter STRM5_WIDTH = 1;
-
-//depths per stream
-parameter STRM0_DEPTH = 20;
-parameter STRM1_DEPTH = 20;
-parameter STRM2_DEPTH = 2304;
-parameter STRM3_DEPTH = 2304;
-parameter STRM4_DEPTH = 1;
-parameter STRM5_DEPTH = 1;
-
-//offsets for each stream
-parameter STRM0_OFFSET = 0;
-parameter STRM1_OFFSET = 20;
-parameter STRM2_OFFSET = 4608;
-parameter STRM3_OFFSET = 6912;
-parameter STRM4_OFFSET = 0;
-parameter STRM5_OFFSET = 0;
-
-
-reg clk;
-reg rst;
-
-wire awready;
-reg awvalid;
-reg [31:0] awaddr;
-reg [2:0] awprot;
-//write data
-wire wready;
-reg wvalid;
-reg [31:0] wdata;
-reg [3:0] wstrb;
-//burst response
-reg bready;
-wire bvalid;
-wire [1:0] bresp;
-
-//Read channels
-//read address
-wire arready;
-reg arvalid;
-reg [31:0] araddr;
-reg [2:0] arprot;
-//read data
-reg rready;
-wire rvalid;
-wire [1:0] rresp;
-wire [31:0] rdata;
-
-//multiple wire AXI Streams
-reg m_axis_0_afull;
-reg m_axis_0_tready;
-wire m_axis_0_tvalid;
-wire [STRM0_WIDTH-1:0] m_axis_0_tdata;
-
-reg m_axis_1_afull;
-reg m_axis_1_tready;
-wire m_axis_1_tvalid;
-wire [STRM1_WIDTH-1:0] m_axis_1_tdata;
-
-reg m_axis_2_afull;
-reg m_axis_2_tready;
-wire m_axis_2_tvalid;
-wire [STRM2_WIDTH-1:0] m_axis_2_tdata;
-
-reg m_axis_3_afull;
-reg m_axis_3_tready;
-wire m_axis_3_tvalid;
-wire [STRM3_WIDTH-1:0] m_axis_3_tdata;
-
-reg m_axis_4_afull;
-reg m_axis_4_tready;
-wire m_axis_4_tvalid;
-wire [STRM4_WIDTH-1:0] m_axis_4_tdata;
-
-reg m_axis_5_afull;
-reg m_axis_5_tready;
-wire m_axis_5_tvalid;
-wire [STRM5_WIDTH-1:0] m_axis_5_tdata;
-
-reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0];
-reg [MEM_WIDTH-1:0] gword;
-integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5;
-integer done = 0;
-integer i, j;
-reg [5:0] rng;
-
-parameter NFOLDS_PER_WORD = (MEM_WIDTH+31)/32;
-
-task axi_write;
- input [MEM_WIDTH-1:0] data;
- input [31:0] adr;
- begin
- for(j=0; j<(1<<$clog2(NFOLDS_PER_WORD)); j=j+1) begin
- @(negedge clk);
- awvalid = 1;
- wvalid = 1;
- wdata = data>>(j*32);
- awaddr = (adr*(1<<$clog2(NFOLDS_PER_WORD))+j)*4;
- fork
- begin
- @(posedge awready);
- @(posedge clk) awvalid = 0;
- end
- begin
- @(posedge wready);
- @(posedge clk) wvalid = 0;
- end
- join
- @(posedge clk);
- end
- end
-endtask
-
-task axi_read;
- input [31:0] adr;
- output [MEM_WIDTH-1:0] data;
- begin
- data = 0;
- for(j=0; j<NFOLDS_PER_WORD; j=j+1) begin
- @(negedge clk);
- arvalid = 1;
- araddr = (adr*(1<<$clog2(NFOLDS_PER_WORD))+j)*4;
- rready = 1;
- fork
- begin
- @(posedge arready);
- @(posedge clk) arvalid = 0;
- end
- begin
- @(posedge rvalid);
- @(posedge clk) rready = 0;
- data = data | (rdata<<(32*j));
- end
- join
- @(posedge clk);
- end
- end
-endtask
-
-//clock
-initial begin
- clk = 0;
- forever #5 clk = ~clk;
-end
-
-initial begin
- rst = 1;
- awvalid = 0;
- arvalid = 0;
- wvalid = 0;
- rready = 1;
- bready = 1;
- m_axis_0_afull = 1;
- m_axis_1_afull = 1;
- m_axis_2_afull = 1;
- m_axis_3_afull = 1;
- m_axis_4_afull = 1;
- m_axis_5_afull = 1;
- m_axis_0_tready = 0;
- m_axis_1_tready = 0;
- m_axis_2_tready = 0;
- m_axis_3_tready = 0;
- m_axis_4_tready = 0;
- m_axis_5_tready = 0;
- repeat(100) @(negedge clk);
- rst = 0;
- #100
- //random initialization of golden data
- for(i=0; i<MEM_DEPTH; i=i+1) begin
- gword = 0;
- repeat(NFOLDS_PER_WORD)
- gword = (gword << 32) | $random;
- golden[i] = gword;
- axi_write(golden[i],i);
- axi_read(i,gword);
- end
- //re-reset
- repeat(100) @(negedge clk);
- rst = 1;
- #100
- repeat(100) @(negedge clk);
- rst = 0;
- #100
- @(negedge clk);
- //start reads
- m_axis_0_afull = 0;
- m_axis_1_afull = 0;
- m_axis_2_afull = 0;
- m_axis_3_afull = 0;
- m_axis_4_afull = 0;
- m_axis_5_afull = 0;
- m_axis_0_tready = 1;
- m_axis_1_tready = 1;
- m_axis_2_tready = 1;
- m_axis_3_tready = 1;
- m_axis_4_tready = 1;
- m_axis_5_tready = 1;
- fork
- begin
- $display("Starting to generate random AFULL");
- while(~done) begin
- rng = $random;
- m_axis_0_afull = rng[0];
- m_axis_1_afull = rng[1];
- m_axis_2_afull = rng[2];
- m_axis_3_afull = rng[3];
- m_axis_4_afull = rng[4];
- m_axis_5_afull = rng[5];
- @(negedge clk);
- end
- end
- join
-end
-
-
-//DUT
-memstream
-#(
- CONFIG_EN,
- NSTREAMS,
- MEM_DEPTH,
- MEM_WIDTH,
- ".",
- "auto",
- //widths per stream
- STRM0_WIDTH,
- STRM1_WIDTH,
- STRM2_WIDTH,
- STRM3_WIDTH,
- STRM4_WIDTH,
- STRM5_WIDTH,
- //depths per stream
- STRM0_DEPTH,
- STRM1_DEPTH,
- STRM2_DEPTH,
- STRM3_DEPTH,
- STRM4_DEPTH,
- STRM5_DEPTH,
- //offsets for each stream
- STRM0_OFFSET,
- STRM1_OFFSET,
- STRM2_OFFSET,
- STRM3_OFFSET,
- STRM4_OFFSET,
- STRM5_OFFSET
-)
-dut
-(
- clk,
- ~rst,
-
- //optional AXI-Lite interface
- awready,
- awvalid,
- awaddr,
- awprot,
- //write data
- wready,
- wvalid,
- wdata,
- wstrb,
- //burst response
- bready,
- bvalid,
- bresp,
-
- //Read channels
- //read address
- arready,
- arvalid,
- araddr,
- arprot,
- //read data
- rready,
- rvalid,
- rresp,
- rdata,
-
- //multiple output AXI Streams
- m_axis_0_afull,
- m_axis_0_tready,
- m_axis_0_tvalid,
- m_axis_0_tdata,
- m_axis_1_afull,
- m_axis_1_tready,
- m_axis_1_tvalid,
- m_axis_1_tdata,
- m_axis_2_afull,
- m_axis_2_tready,
- m_axis_2_tvalid,
- m_axis_2_tdata,
- m_axis_3_afull,
- m_axis_3_tready,
- m_axis_3_tvalid,
- m_axis_3_tdata,
- m_axis_4_afull,
- m_axis_4_tready,
- m_axis_4_tvalid,
- m_axis_4_tdata,
- m_axis_5_afull,
- m_axis_5_tready,
- m_axis_5_tvalid,
- m_axis_5_tdata
-
-);
-
-//stream checkers
-initial begin
- ptr0 = STRM0_OFFSET;
- ptr1 = STRM1_OFFSET;
- ptr2 = STRM2_OFFSET;
- ptr3 = STRM3_OFFSET;
- ptr4 = STRM4_OFFSET;
- ptr5 = STRM5_OFFSET;
- fork
- //check stream 0
- begin
- $display("Starting stream 0 checker");
- while(~done & (NSTREAMS > 0)) begin
- @(negedge clk);
- if(m_axis_0_tvalid & m_axis_0_tready) begin
- if(m_axis_0_tdata != golden[ptr0]) begin
- $display("Mismatch on stream 0");
- $stop();
- end
- //increment pointer
- ptr0 = ptr0 + 1;
- //rewind pointer if it's reached end
- if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH))
- ptr0 = STRM0_OFFSET;
- end
- end
- end
- //check stream 1
- begin
- $display("Starting stream 1 checker");
- while(~done & (NSTREAMS > 1)) begin
- @(negedge clk);
- if(m_axis_1_tvalid & m_axis_1_tready) begin
- if(m_axis_1_tdata != golden[ptr1]) begin
- $display("Mismatch on stream 1");
- $stop();
- end
- //increment pointer
- ptr1 = ptr1 + 1;
- //rewind pointer if it's reached end
- if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH))
- ptr1 = STRM1_OFFSET;
- end
- end
- end
- //check stream 2
- begin
- $display("Starting stream 2 checker");
- while(~done & (NSTREAMS > 2)) begin
- @(negedge clk);
- if(m_axis_2_tvalid & m_axis_2_tready) begin
- if(m_axis_2_tdata != golden[ptr2]) begin
- $display("Mismatch on stream 2");
- $stop();
- end
- //increment pointer
- ptr2 = ptr2 + 1;
- //rewind pointer if it's reached end
- if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH))
- ptr2 = STRM2_OFFSET;
- end
- end
- end
- //check stream 3
- begin
- $display("Starting stream 3 checker");
- while(~done & (NSTREAMS > 3)) begin
- @(negedge clk);
- if(m_axis_3_tvalid & m_axis_3_tready) begin
- if(m_axis_3_tdata != golden[ptr3]) begin
- $display("Mismatch on stream 3");
- $stop();
- end
- //increment pointer
- ptr3 = ptr3 + 1;
- //rewind pointer if it's reached end
- if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH))
- ptr3 = STRM3_OFFSET;
- end
- end
- end
- //check stream 4
- begin
- $display("Starting stream 4 checker");
- while(~done & (NSTREAMS > 4)) begin
- @(negedge clk);
- if(m_axis_4_tvalid & m_axis_4_tready) begin
- if(m_axis_4_tdata != golden[ptr4]) begin
- $display("Mismatch on stream 4");
- $stop();
- end
- //increment pointer
- ptr4 = ptr4 + 1;
- //rewind pointer if it's reached end
- if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH))
- ptr4 = STRM4_OFFSET;
- end
- end
- end
- //check stream 5
- begin
- $display("Starting stream 5 checker");
- while(~done & (NSTREAMS > 5)) begin
- @(negedge clk);
- if(m_axis_5_tvalid & m_axis_5_tready) begin
- if(m_axis_5_tdata != golden[ptr5]) begin
- $display("Mismatch on stream 5");
- $stop();
- end
- //increment pointer
- ptr5 = ptr5 + 1;
- //rewind pointer if it's reached end
- if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH))
- ptr5 = STRM5_OFFSET;
- end
- end
- end
- join
-end
-
-initial begin
- done = 0;
- @(negedge rst);
- $dumpfile("wave.vcd");
- $dumpvars(0,tb_memstream_writes);
- #50000
- $display("Test done!");
- done = 1;
- #1000
- $finish();
-end
-
-endmodule
diff --git a/finn-rtllib/memstream/sim/test.sh b/finn-rtllib/memstream/sim/test.sh
deleted file mode 100755
index 7cb0497d261ac41a763bad8e58afabb204887d39..0000000000000000000000000000000000000000
--- a/finn-rtllib/memstream/sim/test.sh
+++ /dev/null
@@ -1,32 +0,0 @@
-#!/bin/bash
-
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-iverilog ../hdl/*.v tb_memstream_writes.v -o sim
-./sim
diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
index 87565bc5613ce783d6a8067e8323d2358adb8061..e802d81c79d9483f3ce515cb69b96f424badd1d5 100644
--- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
+++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
@@ -8,42 +8,21 @@ proc init_gui { IPINST } {
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "AXILITE_ADDR_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "CONFIG_EN" -parent ${Page_0}
- ipgui::add_param $IPINST -name "MEM_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "MEM_INIT" -parent ${Page_0}
- ipgui::add_param $IPINST -name "MEM_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "NSTREAMS" -parent ${Page_0}
- ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} -widget comboBox
- ipgui::add_param $IPINST -name "STRM0_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM0_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM0_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM1_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM1_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM1_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM2_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM2_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM2_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM3_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM3_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM3_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM4_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM4_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM4_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM5_DEPTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM5_OFFSET" -parent ${Page_0}
- ipgui::add_param $IPINST -name "STRM5_WIDTH" -parent ${Page_0}
-
-
+ ipgui::add_param $IPINST -name "DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "INIT_FILE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0}
}
-proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_WIDTH } {
+proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.DEPTH PARAM_VALUE.WIDTH } {
# Procedure called to update AXILITE_ADDR_WIDTH when any of the dependent parameters in the arguments change
+
set AXILITE_ADDR_WIDTH ${PARAM_VALUE.AXILITE_ADDR_WIDTH}
- set MEM_DEPTH ${PARAM_VALUE.MEM_DEPTH}
- set MEM_WIDTH ${PARAM_VALUE.MEM_WIDTH}
- set values(MEM_DEPTH) [get_property value $MEM_DEPTH]
- set values(MEM_WIDTH) [get_property value $MEM_WIDTH]
- set_property value [gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE $values(MEM_DEPTH) $values(MEM_WIDTH)] $AXILITE_ADDR_WIDTH
+ set DEPTH ${PARAM_VALUE.DEPTH}
+ set WIDTH ${PARAM_VALUE.WIDTH}
+ set values(DEPTH) [get_property value $DEPTH]
+ set values(WIDTH) [get_property value $WIDTH]
+ set_property value [gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE $values(DEPTH) $values(WIDTH)] $AXILITE_ADDR_WIDTH
}
proc validate_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH } {
@@ -51,48 +30,21 @@ proc validate_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH }
return true
}
-proc update_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
- # Procedure called to update CONFIG_EN when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } {
+ # Procedure called to update DEPTH when any of the dependent parameters in the arguments change
}
-proc validate_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
- # Procedure called to validate CONFIG_EN
+proc validate_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } {
+ # Procedure called to validate DEPTH
return true
}
-proc update_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
- # Procedure called to update MEM_DEPTH when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } {
+ # Procedure called to update INIT_FILE when any of the dependent parameters in the arguments change
}
-proc validate_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
- # Procedure called to validate MEM_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
- # Procedure called to update MEM_INIT when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
- # Procedure called to validate MEM_INIT
- return true
-}
-
-proc update_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
- # Procedure called to update MEM_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
- # Procedure called to validate MEM_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
- # Procedure called to update NSTREAMS when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
- # Procedure called to validate NSTREAMS
+proc validate_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } {
+ # Procedure called to validate INIT_FILE
return true
}
@@ -105,192 +57,29 @@ proc validate_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } {
return true
}
-proc update_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
- # Procedure called to update STRM0_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
- # Procedure called to validate STRM0_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
- # Procedure called to update STRM0_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
- # Procedure called to validate STRM0_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
- # Procedure called to update STRM0_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
- # Procedure called to validate STRM0_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
- # Procedure called to update STRM1_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
- # Procedure called to validate STRM1_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
- # Procedure called to update STRM1_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
- # Procedure called to validate STRM1_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
- # Procedure called to update STRM1_WIDTH when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+ # Procedure called to update WIDTH when any of the dependent parameters in the arguments change
}
-proc validate_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
- # Procedure called to validate STRM1_WIDTH
+proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+ # Procedure called to validate WIDTH
return true
}
-proc update_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
- # Procedure called to update STRM2_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
- # Procedure called to validate STRM2_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
- # Procedure called to update STRM2_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
- # Procedure called to validate STRM2_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
- # Procedure called to update STRM2_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
- # Procedure called to validate STRM2_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
- # Procedure called to update STRM3_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
- # Procedure called to validate STRM3_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
- # Procedure called to update STRM3_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
- # Procedure called to validate STRM3_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
- # Procedure called to update STRM3_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
- # Procedure called to validate STRM3_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
- # Procedure called to update STRM4_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
- # Procedure called to validate STRM4_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
- # Procedure called to update STRM4_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
- # Procedure called to validate STRM4_OFFSET
- return true
-}
-proc update_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
- # Procedure called to update STRM4_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
- # Procedure called to validate STRM4_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
- # Procedure called to update STRM5_DEPTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
- # Procedure called to validate STRM5_DEPTH
- return true
-}
-
-proc update_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
- # Procedure called to update STRM5_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
- # Procedure called to validate STRM5_OFFSET
- return true
-}
-
-proc update_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
- # Procedure called to update STRM5_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
- # Procedure called to validate STRM5_WIDTH
- return true
-}
-
-
-proc update_MODELPARAM_VALUE.CONFIG_EN { MODELPARAM_VALUE.CONFIG_EN PARAM_VALUE.CONFIG_EN } {
+proc update_MODELPARAM_VALUE.DEPTH { MODELPARAM_VALUE.DEPTH PARAM_VALUE.DEPTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.CONFIG_EN}] ${MODELPARAM_VALUE.CONFIG_EN}
+ set_property value [get_property value ${PARAM_VALUE.DEPTH}] ${MODELPARAM_VALUE.DEPTH}
}
-proc update_MODELPARAM_VALUE.NSTREAMS { MODELPARAM_VALUE.NSTREAMS PARAM_VALUE.NSTREAMS } {
+proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.NSTREAMS}] ${MODELPARAM_VALUE.NSTREAMS}
+ set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH}
}
-proc update_MODELPARAM_VALUE.MEM_DEPTH { MODELPARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_DEPTH } {
+proc update_MODELPARAM_VALUE.INIT_FILE { MODELPARAM_VALUE.INIT_FILE PARAM_VALUE.INIT_FILE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.MEM_DEPTH}] ${MODELPARAM_VALUE.MEM_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.MEM_WIDTH { MODELPARAM_VALUE.MEM_WIDTH PARAM_VALUE.MEM_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.MEM_WIDTH}] ${MODELPARAM_VALUE.MEM_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.MEM_INIT { MODELPARAM_VALUE.MEM_INIT PARAM_VALUE.MEM_INIT } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.MEM_INIT}] ${MODELPARAM_VALUE.MEM_INIT}
+ set_property value [get_property value ${PARAM_VALUE.INIT_FILE}] ${MODELPARAM_VALUE.INIT_FILE}
}
proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE.RAM_STYLE } {
@@ -298,96 +87,6 @@ proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE.
set_property value [get_property value ${PARAM_VALUE.RAM_STYLE}] ${MODELPARAM_VALUE.RAM_STYLE}
}
-proc update_MODELPARAM_VALUE.STRM0_WIDTH { MODELPARAM_VALUE.STRM0_WIDTH PARAM_VALUE.STRM0_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM0_WIDTH}] ${MODELPARAM_VALUE.STRM0_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM1_WIDTH { MODELPARAM_VALUE.STRM1_WIDTH PARAM_VALUE.STRM1_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM1_WIDTH}] ${MODELPARAM_VALUE.STRM1_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM2_WIDTH { MODELPARAM_VALUE.STRM2_WIDTH PARAM_VALUE.STRM2_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM2_WIDTH}] ${MODELPARAM_VALUE.STRM2_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM3_WIDTH { MODELPARAM_VALUE.STRM3_WIDTH PARAM_VALUE.STRM3_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM3_WIDTH}] ${MODELPARAM_VALUE.STRM3_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM4_WIDTH { MODELPARAM_VALUE.STRM4_WIDTH PARAM_VALUE.STRM4_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM4_WIDTH}] ${MODELPARAM_VALUE.STRM4_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM5_WIDTH { MODELPARAM_VALUE.STRM5_WIDTH PARAM_VALUE.STRM5_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM5_WIDTH}] ${MODELPARAM_VALUE.STRM5_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM0_DEPTH { MODELPARAM_VALUE.STRM0_DEPTH PARAM_VALUE.STRM0_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM0_DEPTH}] ${MODELPARAM_VALUE.STRM0_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM1_DEPTH { MODELPARAM_VALUE.STRM1_DEPTH PARAM_VALUE.STRM1_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM1_DEPTH}] ${MODELPARAM_VALUE.STRM1_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM2_DEPTH { MODELPARAM_VALUE.STRM2_DEPTH PARAM_VALUE.STRM2_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM2_DEPTH}] ${MODELPARAM_VALUE.STRM2_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM3_DEPTH { MODELPARAM_VALUE.STRM3_DEPTH PARAM_VALUE.STRM3_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM3_DEPTH}] ${MODELPARAM_VALUE.STRM3_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM4_DEPTH { MODELPARAM_VALUE.STRM4_DEPTH PARAM_VALUE.STRM4_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM4_DEPTH}] ${MODELPARAM_VALUE.STRM4_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM5_DEPTH { MODELPARAM_VALUE.STRM5_DEPTH PARAM_VALUE.STRM5_DEPTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM5_DEPTH}] ${MODELPARAM_VALUE.STRM5_DEPTH}
-}
-
-proc update_MODELPARAM_VALUE.STRM0_OFFSET { MODELPARAM_VALUE.STRM0_OFFSET PARAM_VALUE.STRM0_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM0_OFFSET}] ${MODELPARAM_VALUE.STRM0_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM1_OFFSET { MODELPARAM_VALUE.STRM1_OFFSET PARAM_VALUE.STRM1_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM1_OFFSET}] ${MODELPARAM_VALUE.STRM1_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM2_OFFSET { MODELPARAM_VALUE.STRM2_OFFSET PARAM_VALUE.STRM2_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM2_OFFSET}] ${MODELPARAM_VALUE.STRM2_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM3_OFFSET { MODELPARAM_VALUE.STRM3_OFFSET PARAM_VALUE.STRM3_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM3_OFFSET}] ${MODELPARAM_VALUE.STRM3_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM4_OFFSET { MODELPARAM_VALUE.STRM4_OFFSET PARAM_VALUE.STRM4_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM4_OFFSET}] ${MODELPARAM_VALUE.STRM4_OFFSET}
-}
-
-proc update_MODELPARAM_VALUE.STRM5_OFFSET { MODELPARAM_VALUE.STRM5_OFFSET PARAM_VALUE.STRM5_OFFSET } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.STRM5_OFFSET}] ${MODELPARAM_VALUE.STRM5_OFFSET}
-}
-
proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.AXILITE_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXILITE_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH}
diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv
new file mode 100644
index 0000000000000000000000000000000000000000..f2cdc333cad0a546aa9cfb55c9ca1dd74a753dc2
--- /dev/null
+++ b/finn-rtllib/swg/swg_common.sv
@@ -0,0 +1,249 @@
+/******************************************************************************
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+
+// loop controller used for both, "default" and "parallel", implementation styles
+module swg_controller
+import swg::*; #(
+ int unsigned LOOP_H_ITERATIONS,
+ int unsigned LOOP_W_ITERATIONS,
+ int unsigned LOOP_KH_ITERATIONS,
+ int unsigned LOOP_KW_ITERATIONS,
+ int unsigned LOOP_SIMD_ITERATIONS,
+
+ int unsigned INCR_BITWIDTH,
+
+ bit IS_DEPTHWISE,
+
+ int HEAD_INCR_SIMD,
+ int HEAD_INCR_KW,
+ int HEAD_INCR_KH,
+ int HEAD_INCR_W,
+ int HEAD_INCR_H,
+ int TAIL_INCR_W,
+ int TAIL_INCR_H,
+ int TAIL_INCR_LAST,
+
+ state_e INNERMOST_STATE
+)(
+ input logic clk,
+ input logic rst_n,
+
+ input logic advance,
+ output logic [INCR_BITWIDTH-1:0] addr_incr,
+ output logic [INCR_BITWIDTH-1:0] tail_incr
+);
+
+ // state and counters
+ state_e State = INNERMOST_STATE;
+ state_e state_next;
+
+ logic signed [$clog2(LOOP_H_ITERATIONS +2)+1-1:0] Counter_loop_h = LOOP_H_ITERATIONS;
+ logic signed [$clog2(LOOP_W_ITERATIONS +2)+1-1:0] Counter_loop_w = LOOP_W_ITERATIONS;
+ logic signed [$clog2(LOOP_KH_ITERATIONS +2)+1-1:0] Counter_loop_kh = LOOP_KH_ITERATIONS;
+ logic signed [$clog2(LOOP_KW_ITERATIONS +2)+1-1:0] Counter_loop_kw = LOOP_KW_ITERATIONS;
+ logic signed [$clog2(LOOP_SIMD_ITERATIONS+2)+1-1:0] Counter_loop_simd = LOOP_SIMD_ITERATIONS;
+
+ // combinational logic for addr_incr generation
+ always_comb begin : blkHead
+ unique case (State)
+ STATE_START : addr_incr = 0;
+ STATE_LOOP_SIMD : addr_incr = HEAD_INCR_SIMD;
+ STATE_LOOP_KW : addr_incr = HEAD_INCR_KW;
+ STATE_LOOP_KH : addr_incr = HEAD_INCR_KH;
+ STATE_LOOP_W : addr_incr = HEAD_INCR_W;
+ STATE_LOOP_H : addr_incr = HEAD_INCR_H;
+ endcase
+ end
+
+ // combinational logic for tail_incr generation
+ uwire tail_incr_inner_condition = IS_DEPTHWISE? (Counter_loop_kh >= 0) : 0;
+ assign tail_incr =
+ tail_incr_inner_condition? 1 :
+ Counter_loop_w >= 0? TAIL_INCR_W :
+ Counter_loop_h >= 0? TAIL_INCR_H :
+ /* else */ TAIL_INCR_LAST;
+
+ // combinational next state logic
+ always_comb begin : blkState
+ state_next = State;
+ if(State != INNERMOST_STATE) state_next = INNERMOST_STATE;
+ else begin
+ if(Counter_loop_simd < 0) begin
+ state_next =
+ (Counter_loop_kw >= 0)? STATE_LOOP_KW :
+ (Counter_loop_kh >= 0)? STATE_LOOP_KH :
+ (Counter_loop_w >= 0)? STATE_LOOP_W :
+ (Counter_loop_h >= 0)? STATE_LOOP_H :
+ /* else */ STATE_START;
+ end
+ end
+ end : blkState
+
+ // sequential logic
+ always_ff @ (posedge clk) begin
+ if(!rst_n) begin
+ State <= INNERMOST_STATE;
+ Counter_loop_h <= LOOP_H_ITERATIONS;
+ Counter_loop_w <= LOOP_W_ITERATIONS;
+ Counter_loop_kh <= LOOP_KH_ITERATIONS;
+ Counter_loop_kw <= LOOP_KW_ITERATIONS;
+ Counter_loop_simd <= LOOP_SIMD_ITERATIONS;
+ end
+ else if(advance) begin
+ State <= state_next;
+ if (State == INNERMOST_STATE) begin
+ if(Counter_loop_simd >= 0) Counter_loop_simd <= Counter_loop_simd-1;
+ else begin
+ Counter_loop_simd <= LOOP_SIMD_ITERATIONS;
+ if(Counter_loop_kw >= 0) Counter_loop_kw <= Counter_loop_kw-1;
+ else begin
+ Counter_loop_kw <= LOOP_KW_ITERATIONS;
+ if(Counter_loop_kh >= 0) Counter_loop_kh <= Counter_loop_kh-1;
+ else begin
+ Counter_loop_kh <= LOOP_KH_ITERATIONS;
+ if(Counter_loop_w >= 0) Counter_loop_w <= Counter_loop_w-1;
+ else begin
+ Counter_loop_w <= LOOP_W_ITERATIONS;
+ if(Counter_loop_h >= 0) Counter_loop_h <= Counter_loop_h-1;
+ else Counter_loop_h <= LOOP_H_ITERATIONS;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+
+endmodule : swg_controller
+
+// buffer used in "default" implementation style
+module swg_cyclic_buffer_addressable #(
+ int unsigned WIDTH,
+ int unsigned DEPTH,
+ parameter RAM_STYLE = "auto"
+)(
+ input logic clk,
+
+ input logic write_enable,
+ input logic [$clog2(DEPTH)-1:0] write_addr,
+ input logic [WIDTH-1:0] data_in,
+
+ input logic read_enable,
+ input logic [$clog2(DEPTH)-1:0] read_addr, // absolute (!) read address of cyclic buffer
+ output logic [WIDTH-1:0] data_out
+);
+
+ (*ram_style=RAM_STYLE*) logic [WIDTH-1:0] Ram[DEPTH];
+ logic [WIDTH-1:0] Out = 'x;
+ always_ff @(posedge clk) begin
+ if (read_enable) Out <= Ram[read_addr];
+ if (write_enable) Ram[write_addr] <= data_in;
+ end
+ assign data_out = Out;
+
+endmodule : swg_cyclic_buffer_addressable
+
+// buffer used in "parallel" implementation style
+module swg_reg_buffer
+#(
+ int unsigned WIDTH = 1,
+ int unsigned DEPTH = 1
+)
+(
+ input logic clk,
+ input logic shift_enable,
+ input logic [WIDTH-1:0] shift_in,
+ output logic [WIDTH-1:0] shift_out,
+ output logic [WIDTH*DEPTH-1:0] data_out
+);
+
+logic [WIDTH-1:0] Data [DEPTH-1:0];
+
+assign shift_out = Data[DEPTH-1];
+
+for (genvar e=0; e<DEPTH; e++)
+ assign data_out[e*WIDTH +: WIDTH] = Data[e];
+
+always @ (posedge clk) begin
+ if (shift_enable) begin
+ for (int i=DEPTH-1; i>0; i--)
+ Data[i] <= Data[i-1];
+ Data[0] <= shift_in;
+ end
+end
+endmodule : swg_reg_buffer
+
+// buffer used in "parallel" implementation style
+module swg_ram_buffer
+#(
+ int unsigned WIDTH,
+ int unsigned DEPTH,
+ parameter RAM_STYLE = "auto"
+)
+(
+ input logic clk,
+ input logic rst_n,
+ input logic shift_enable,
+ input logic [WIDTH-1:0] shift_in,
+ output logic [WIDTH-1:0] shift_out
+);
+
+logic [WIDTH-1:0] Out_reg;
+assign shift_out = Out_reg;
+
+logic [$clog2(DEPTH)-1:0] Addr_w = 0;
+logic [$clog2(DEPTH)-1:0] Addr_r = 0;
+
+(*ram_style=RAM_STYLE*) logic [WIDTH-1:0] Ram [DEPTH-1:0];
+
+always_ff @(posedge clk) begin
+ if (rst_n == 1'b0) begin
+ Addr_w <= 0;
+ Addr_r <= 1;
+ end else begin
+ if (shift_enable) begin
+ Ram[Addr_w] <= shift_in;
+ Out_reg <= Ram[Addr_r];
+
+ if (Addr_w == DEPTH-1)
+ Addr_w <= 0;
+ else
+ Addr_w <= Addr_w + 1;
+
+ if (Addr_r == DEPTH-1)
+ Addr_r <= 0;
+ else
+ Addr_r <= Addr_r + 1;
+ end
+ end
+end
+endmodule : swg_ram_buffer
diff --git a/finn-rtllib/swg/swg_pkg.sv b/finn-rtllib/swg/swg_pkg.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1200310acad2931568235a82fd0277b8dd50a424
--- /dev/null
+++ b/finn-rtllib/swg/swg_pkg.sv
@@ -0,0 +1,41 @@
+/******************************************************************************
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+package swg;
+ typedef enum logic [2:0] {
+ STATE_START,
+ STATE_LOOP_SIMD,
+ STATE_LOOP_KW,
+ STATE_LOOP_KH,
+ STATE_LOOP_W,
+ STATE_LOOP_H
+ } state_e;
+endpackage : swg
diff --git a/finn-rtllib/swg/swg_template_axilite.v b/finn-rtllib/swg/swg_template_axilite.v
index 9479c7f80d7d82b27141dbe5abcce442049237bd..1f39e4440e47f752816907dc454d15b849c8fa85 100644
--- a/finn-rtllib/swg/swg_template_axilite.v
+++ b/finn-rtllib/swg/swg_template_axilite.v
@@ -1,8 +1,35 @@
+/******************************************************************************
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
-`timescale 1 ns / 1 ps
-
-module $TOP_MODULE_NAME$_axilite #
-(
+module $TOP_MODULE_NAME$_axilite #(
// Users to add parameters here
// User parameters ends
@@ -12,8 +39,7 @@ module $TOP_MODULE_NAME$_axilite #
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 6
-)
-(
+)(
// Users to add ports here
output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg0,
output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg1,
diff --git a/finn-rtllib/swg/swg_template_default.sv b/finn-rtllib/swg/swg_template_default.sv
index 06e65e911100dd7d3d8879b014a6d59713eb9bbd..78a8d0a3b984b987df6ca62f3789fbbedcbc6d8b 100644
--- a/finn-rtllib/swg/swg_template_default.sv
+++ b/finn-rtllib/swg/swg_template_default.sv
@@ -28,141 +28,6 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
-module $TOP_MODULE_NAME$_controller #(
- int unsigned LOOP_H_ITERATIONS = $LOOP_H_ITERATIONS$,
- int unsigned LOOP_W_ITERATIONS = $LOOP_W_ITERATIONS$,
- int unsigned LOOP_KH_ITERATIONS = $LOOP_KH_ITERATIONS$,
- int unsigned LOOP_KW_ITERATIONS = $LOOP_KW_ITERATIONS$,
- int unsigned LOOP_SIMD_ITERATIONS = $LOOP_SIMD_ITERATIONS$,
-
- int unsigned INCR_BITWIDTH = $INCR_BITWIDTH$,
-
- bit IS_DEPTHWISE = $IS_DEPTHWISE$
-)(
- input logic clk,
- input logic rst_n,
-
- input logic advance,
- output logic [INCR_BITWIDTH-1:0] addr_incr,
- output logic [INCR_BITWIDTH-1:0] tail_incr
-);
-
- // state and counters
- typedef enum logic [2:0] {
- STATE_START,
- STATE_LOOP_SIMD,
- STATE_LOOP_KW,
- STATE_LOOP_KH,
- STATE_LOOP_W,
- STATE_LOOP_H
- } state_e;
- state_e State = $INNERMOST_STATE$;
- state_e state_next;
-
- logic signed [$clog2(LOOP_H_ITERATIONS +2)+1-1:0] Counter_loop_h = LOOP_H_ITERATIONS;
- logic signed [$clog2(LOOP_W_ITERATIONS +2)+1-1:0] Counter_loop_w = LOOP_W_ITERATIONS;
- logic signed [$clog2(LOOP_KH_ITERATIONS +2)+1-1:0] Counter_loop_kh = LOOP_KH_ITERATIONS;
- logic signed [$clog2(LOOP_KW_ITERATIONS +2)+1-1:0] Counter_loop_kw = LOOP_KW_ITERATIONS;
- logic signed [$clog2(LOOP_SIMD_ITERATIONS+2)+1-1:0] Counter_loop_simd = LOOP_SIMD_ITERATIONS;
-
- // combinational logic for addr_incr generation
- always_comb begin : blkHead
- unique case (State)
- 0 : addr_incr = 0;
- 1 : addr_incr = $HEAD_INCR_SIMD$;
- 2 : addr_incr = $HEAD_INCR_KW$;
- 3 : addr_incr = $HEAD_INCR_KH$;
- 4 : addr_incr = $HEAD_INCR_W$;
- 5 : addr_incr = $HEAD_INCR_H$;
- endcase
- end
-
- // combinational logic for tail_incr generation
- uwire tail_incr_inner_condition = IS_DEPTHWISE? (Counter_loop_kh >= 0) : 0;
- assign tail_incr =
- tail_incr_inner_condition? 1 :
- Counter_loop_w >= 0? $TAIL_INCR_W$ :
- Counter_loop_h >= 0? $TAIL_INCR_H$ :
- /* else */ $TAIL_INCR_LAST$;
-
- // combinational next state logic
- always_comb begin : blkState
- state_next = State;
- if(State != $INNERMOST_STATE$) state_next = $INNERMOST_STATE$;
- else begin
- if(Counter_loop_simd < 0) begin
- state_next =
- (Counter_loop_kw >= 0)? STATE_LOOP_KW :
- (Counter_loop_kh >= 0)? STATE_LOOP_KH :
- (Counter_loop_w >= 0)? STATE_LOOP_W :
- (Counter_loop_h >= 0)? STATE_LOOP_H :
- /* else */ STATE_START;
- end
- end
- end : blkState
-
- // sequential logic
- always_ff @ (posedge clk) begin
- if(!rst_n) begin
- State <= $INNERMOST_STATE$;
- Counter_loop_h <= LOOP_H_ITERATIONS;
- Counter_loop_w <= LOOP_W_ITERATIONS;
- Counter_loop_kh <= LOOP_KH_ITERATIONS;
- Counter_loop_kw <= LOOP_KW_ITERATIONS;
- Counter_loop_simd <= LOOP_SIMD_ITERATIONS;
- end
- else if(advance) begin
- State <= state_next;
- if (State == $INNERMOST_STATE$) begin
- if(Counter_loop_simd >= 0) Counter_loop_simd <= Counter_loop_simd-1;
- else begin
- Counter_loop_simd <= LOOP_SIMD_ITERATIONS;
- if(Counter_loop_kw >= 0) Counter_loop_kw <= Counter_loop_kw-1;
- else begin
- Counter_loop_kw <= LOOP_KW_ITERATIONS;
- if(Counter_loop_kh >= 0) Counter_loop_kh <= Counter_loop_kh-1;
- else begin
- Counter_loop_kh <= LOOP_KH_ITERATIONS;
- if(Counter_loop_w >= 0) Counter_loop_w <= Counter_loop_w-1;
- else begin
- Counter_loop_w <= LOOP_W_ITERATIONS;
- if(Counter_loop_h >= 0) Counter_loop_h <= Counter_loop_h-1;
- else Counter_loop_h <= LOOP_H_ITERATIONS;
- end
- end
- end
- end
- end
- end
- end
-
-endmodule : $TOP_MODULE_NAME$_controller
-
-module $TOP_MODULE_NAME$_cyclic_buffer_addressable #(
- int unsigned WIDTH,
- int unsigned DEPTH
-)(
- input logic clk,
-
- input logic write_enable,
- input logic [$clog2(DEPTH)-1:0] write_addr,
- input logic [WIDTH-1:0] data_in,
-
- input logic read_enable,
- input logic [$clog2(DEPTH)-1:0] read_addr, // absolute (!) read address of cyclic buffer
- output logic [WIDTH-1:0] data_out
-);
-
- $RAM_STYLE$ logic [WIDTH-1:0] Ram[DEPTH];
- logic [WIDTH-1:0] Out = 'x;
- always_ff @(posedge clk) begin
- if (read_enable) Out <= Ram[read_addr];
- if (write_enable) Ram[write_addr] <= data_in;
- end
- assign data_out = Out;
-
-endmodule : $TOP_MODULE_NAME$_cyclic_buffer_addressable
-
module $TOP_MODULE_NAME$_impl #(
int BIT_WIDTH,
int SIMD,
@@ -197,9 +62,10 @@ module $TOP_MODULE_NAME$_impl #(
uwire window_buffer_read_enable;
uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_write_addr;
uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_read_addr;
- $TOP_MODULE_NAME$_cyclic_buffer_addressable #(
+ swg_cyclic_buffer_addressable #(
.WIDTH(BUF_IN_WIDTH),
- .DEPTH(BUF_ELEM_TOTAL)
+ .DEPTH(BUF_ELEM_TOTAL),
+ .RAM_STYLE($RAM_STYLE$)
) window_buffer_inst (
.clk(ap_clk),
@@ -216,7 +82,25 @@ module $TOP_MODULE_NAME$_impl #(
uwire advance_controller;
uwire signed [INCR_BITWIDTH-1:0] addr_incr;
uwire [INCR_BITWIDTH-1:0] tail_incr;
- $TOP_MODULE_NAME$_controller controller_inst (
+ swg_controller #(
+ .LOOP_H_ITERATIONS($LOOP_H_ITERATIONS$),
+ .LOOP_W_ITERATIONS($LOOP_W_ITERATIONS$),
+ .LOOP_KH_ITERATIONS($LOOP_KH_ITERATIONS$),
+ .LOOP_KW_ITERATIONS($LOOP_KW_ITERATIONS$),
+ .LOOP_SIMD_ITERATIONS($LOOP_SIMD_ITERATIONS$),
+ .HEAD_INCR_SIMD($HEAD_INCR_SIMD$),
+ .HEAD_INCR_KW($HEAD_INCR_KW$),
+ .HEAD_INCR_KH($HEAD_INCR_KH$),
+ .HEAD_INCR_W($HEAD_INCR_W$),
+ .HEAD_INCR_H($HEAD_INCR_H$),
+ .TAIL_INCR_W($TAIL_INCR_W$),
+ .TAIL_INCR_H($TAIL_INCR_H$),
+ .TAIL_INCR_LAST($TAIL_INCR_LAST$),
+ .INCR_BITWIDTH($INCR_BITWIDTH$),
+ .IS_DEPTHWISE($IS_DEPTHWISE$),
+ .INNERMOST_STATE(swg::$INNERMOST_STATE$)
+ )
+ controller_inst (
.clk(ap_clk),
.rst_n(ap_rst_n),
.advance(advance_controller),
diff --git a/finn-rtllib/swg/swg_template_default_dynamic.sv b/finn-rtllib/swg/swg_template_default_dynamic.sv
index eb53978b580a4753bbea6c8478f35912deb812b4..5a6fdda170242b804353cac186c1f920a4a71d7a 100644
--- a/finn-rtllib/swg/swg_template_default_dynamic.sv
+++ b/finn-rtllib/swg/swg_template_default_dynamic.sv
@@ -1,3 +1,34 @@
+/******************************************************************************
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
module $TOP_MODULE_NAME$_controller #(
int unsigned CNTR_BITWIDTH,
int unsigned INCR_BITWIDTH,
@@ -27,6 +58,8 @@ module $TOP_MODULE_NAME$_controller #(
input logic [INCR_BITWIDTH-1:0] cfg_incr_tail_last
);
+ import swg::*;
+
// (dynamic) configuration registers
logic [CNTR_BITWIDTH-1:0] Cfg_cntr_simd = $LOOP_SIMD_ITERATIONS$;
logic [CNTR_BITWIDTH-1:0] Cfg_cntr_kw = $LOOP_KW_ITERATIONS$;
@@ -62,14 +95,6 @@ module $TOP_MODULE_NAME$_controller #(
end
// state and counters
- typedef enum logic [2:0] {
- STATE_START,
- STATE_LOOP_SIMD,
- STATE_LOOP_KW,
- STATE_LOOP_KH,
- STATE_LOOP_W,
- STATE_LOOP_H
- } state_e;
state_e State = $INNERMOST_STATE$;
state_e state_next;
@@ -152,31 +177,6 @@ module $TOP_MODULE_NAME$_controller #(
endmodule : $TOP_MODULE_NAME$_controller
-module $TOP_MODULE_NAME$_cyclic_buffer_addressable #(
- int unsigned WIDTH,
- int unsigned DEPTH
-)(
- input logic clk,
-
- input logic write_enable,
- input logic [$clog2(DEPTH)-1:0] write_addr,
- input logic [WIDTH-1:0] data_in,
-
- input logic read_enable,
- input logic [$clog2(DEPTH)-1:0] read_addr, // absolute (!) read address of cyclic buffer
- output logic [WIDTH-1:0] data_out
-);
-
- $RAM_STYLE$ logic [WIDTH-1:0] Ram[DEPTH];
- logic [WIDTH-1:0] Out = 'x;
- always_ff @(posedge clk) begin
- if (read_enable) Out <= Ram[read_addr];
- if (write_enable) Ram[write_addr] <= data_in;
- end
- assign data_out = Out;
-
-endmodule : $TOP_MODULE_NAME$_cyclic_buffer_addressable
-
module $TOP_MODULE_NAME$_impl #(
int BIT_WIDTH,
int SIMD,
@@ -242,9 +242,10 @@ module $TOP_MODULE_NAME$_impl #(
uwire window_buffer_read_enable;
uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_write_addr;
uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_read_addr;
- $TOP_MODULE_NAME$_cyclic_buffer_addressable #(
+ swg_cyclic_buffer_addressable #(
.WIDTH(BUF_IN_WIDTH),
- .DEPTH(BUF_ELEM_TOTAL)
+ .DEPTH(BUF_ELEM_TOTAL),
+ .RAM_STYLE($RAM_STYLE$)
) window_buffer_inst (
.clk(ap_clk),
diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv
new file mode 100644
index 0000000000000000000000000000000000000000..83a525ff36b883122cd31a59675557a23085a872
--- /dev/null
+++ b/finn-rtllib/swg/swg_template_parallel.sv
@@ -0,0 +1,228 @@
+/******************************************************************************
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+module $TOP_MODULE_NAME$_wb
+#(
+ int unsigned IN_WIDTH = 1, // bit-width*C*MMV_in
+ int unsigned OUT_ELEM_WIDTH = 1, // bit-width*C
+ int unsigned OUT_WIDTH = 1, // bit-width*C*MMV_out
+ int unsigned BUFFER_ELEM_TOTAL = 1
+)
+(
+ input logic clk,
+ input logic rst_n,
+ input logic shift_enable,
+ input logic [IN_WIDTH-1:0] data_in,
+ output logic [OUT_WIDTH-1:0] data_out
+);
+
+$GENERATE_REG_FIFOS$
+
+$GENERATE_BRAM_FIFOS$
+
+// fixed interconnect between linear buffers
+$GENERATE_BUFFER_CONNECTION$
+
+// fixed REG FIFO -> output mapping
+$GENERATE_OUTPUT_MAPPING$
+
+endmodule : $TOP_MODULE_NAME$_wb
+
+module $TOP_MODULE_NAME$_impl #(
+ int unsigned BIT_WIDTH,
+ int unsigned SIMD,
+ int unsigned MMV_IN,
+ int unsigned MMV_OUT,
+ int unsigned LAST_READ_ELEM = $LAST_READ_ELEM$,
+ int unsigned FIRST_WRITE_ELEM = $FIRST_WRITE_ELEM$,
+ int unsigned LAST_WRITE_ELEM = $LAST_WRITE_ELEM$,
+ int unsigned BUF_ELEM_TOTAL = $BUF_ELEM_TOTAL$,
+ int unsigned INCR_BITWIDTH = $INCR_BITWIDTH$
+)(
+ input logic ap_clk,
+ input logic ap_rst_n,
+
+ input logic in0_V_V_TVALID,
+ output logic in0_V_V_TREADY,
+ input logic [BIT_WIDTH * SIMD * MMV_IN-1:0] in0_V_V_TDATA,
+
+ output logic out_V_V_TVALID,
+ input logic out_V_V_TREADY,
+ output logic [BIT_WIDTH * SIMD * MMV_OUT-1:0] out_V_V_TDATA
+);
+ // derived constants
+ localparam int unsigned BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN;
+ localparam int unsigned BUF_OUT_ELEM_WIDTH = BIT_WIDTH * SIMD;
+ localparam int unsigned BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT;
+
+ // main buffer instantiation
+ uwire [BUF_IN_WIDTH -1:0] window_buffer_in;
+ uwire [BUF_OUT_WIDTH-1:0] window_buffer_out;
+ uwire window_buffer_shift_enable;
+ $TOP_MODULE_NAME$_wb
+ #(
+ .IN_WIDTH(BUF_IN_WIDTH),
+ .OUT_ELEM_WIDTH(BUF_OUT_ELEM_WIDTH),
+ .OUT_WIDTH(BUF_OUT_WIDTH),
+ .BUFFER_ELEM_TOTAL(BUF_ELEM_TOTAL)
+ )
+ window_buffer_inst
+ (
+ .clk(ap_clk),
+ .rst_n(ap_rst_n),
+ .data_in(window_buffer_in),
+ .shift_enable(window_buffer_shift_enable),
+ .data_out(window_buffer_out)
+ );
+
+ // controller instantiation
+ uwire advance_controller;
+ uwire signed [INCR_BITWIDTH-1:0] addr_incr;
+ uwire [INCR_BITWIDTH-1:0] tail_incr;
+ swg_controller #(
+ .LOOP_H_ITERATIONS($LOOP_H_ITERATIONS$),
+ .LOOP_W_ITERATIONS($LOOP_W_ITERATIONS$),
+ .LOOP_KH_ITERATIONS($LOOP_KH_ITERATIONS$),
+ .LOOP_KW_ITERATIONS($LOOP_KW_ITERATIONS$),
+ .LOOP_SIMD_ITERATIONS($LOOP_SIMD_ITERATIONS$),
+ .HEAD_INCR_SIMD($HEAD_INCR_SIMD$),
+ .HEAD_INCR_KW($HEAD_INCR_KW$),
+ .HEAD_INCR_KH($HEAD_INCR_KH$),
+ .HEAD_INCR_W($HEAD_INCR_W$),
+ .HEAD_INCR_H($HEAD_INCR_H$),
+ .TAIL_INCR_W($TAIL_INCR_W$),
+ .TAIL_INCR_H($TAIL_INCR_H$),
+ .TAIL_INCR_LAST($TAIL_INCR_LAST$),
+ .INCR_BITWIDTH($INCR_BITWIDTH$),
+ .IS_DEPTHWISE($IS_DEPTHWISE$),
+ .INNERMOST_STATE(swg::$INNERMOST_STATE$)
+ )
+ controller_inst (
+ .clk(ap_clk),
+ .rst_n(ap_rst_n),
+ .advance(advance_controller),
+ .addr_incr(addr_incr),
+ .tail_incr(tail_incr)
+ );
+
+ // counters/address registers
+ logic signed [$clog2(LAST_READ_ELEM+1)+1-1:0] Newest_buffered_elem = -1;
+ logic [$clog2(LAST_READ_ELEM+1)+1-1:0] Current_elem = FIRST_WRITE_ELEM;
+ logic [$clog2(LAST_READ_ELEM+1)+1-1:0] First_elem_next_window = 0;
+
+ // control registers/signals
+ logic Writing_done = 0;
+ logic Write_done = 0;
+ uwire write_cmd = !($signed(Current_elem) > Newest_buffered_elem) && !Writing_done;;
+ uwire write_ok = write_cmd && (out_V_V_TREADY || Write_done);
+ uwire write_blocked = write_cmd && !out_V_V_TREADY && !Write_done;
+
+ uwire reading_done = Newest_buffered_elem == LAST_READ_ELEM;
+ uwire read_cmd =
+ !reading_done && ( // if there is still an input element left to read
+ Writing_done || ( // if writing is done (e.g. for skipped rows at FM end due to stride)
+ $signed(((Newest_buffered_elem - ($signed(BUF_ELEM_TOTAL) - 1)))) < $signed(First_elem_next_window) &&
+ $signed(((Newest_buffered_elem - ($signed(BUF_ELEM_TOTAL) - 1)))) < $signed(Current_elem)
+ ) // (over-)write to buffer if oldest buffered element will no longer be needed
+ );
+ uwire read_ok = read_cmd && in0_V_V_TVALID && !write_blocked;
+
+ // includes waiting on W if W-only cycle: wait only on W no R/W to wait for
+ uwire advance = read_ok || (!read_cmd && write_ok) || (!read_cmd && !write_cmd);
+
+ // assign buffer control
+ assign window_buffer_shift_enable = advance;
+ assign advance_controller = write_ok;
+
+ // assign I/O ports
+ assign window_buffer_in = in0_V_V_TDATA;
+ assign out_V_V_TDATA = window_buffer_out;
+ assign in0_V_V_TREADY = ap_rst_n && read_ok; //only asserted if data is available and we can store it (allowed)
+ assign out_V_V_TVALID = ap_rst_n && write_cmd && !Write_done; //only asserted if we have data available and it has not been read yet (don't wait for READY from sink)
+
+ // write done logic
+ always_ff @(posedge ap_clk) begin
+ if(!ap_rst_n) begin
+ Write_done <= 1'b0;
+ end
+ else begin
+ if (advance) begin
+ Write_done <= 1'b0; //reset flag
+ end else if (write_ok) //successful W in this cycle, but R still outstanding
+ Write_done <= 1'b1; //write can happen even if read is blocked, but only for the current cycle!
+ end
+ end
+
+ // main process for advancing counters
+ always_ff @(posedge ap_clk) begin
+ if(!ap_rst_n) begin
+ Newest_buffered_elem <= -1;
+ Current_elem <= FIRST_WRITE_ELEM;
+ First_elem_next_window <= 0;
+ Writing_done <= 0;
+ end
+ else begin
+ if (read_ok) begin
+ Newest_buffered_elem <= Newest_buffered_elem+1;
+
+ // check if this is the last read cycle (reading_done will be true afterwards)
+ if ((Newest_buffered_elem == LAST_READ_ELEM-1) && Writing_done) begin
+ // start processing of next FM if writing is done already (possible due to unused input elements at the tail end)
+ // todo: allow for read overlapping between feature maps (i.e., reading first elements from next FM while still writing last window of current FM)
+ Newest_buffered_elem <= -1;
+ Current_elem <= FIRST_WRITE_ELEM;
+ First_elem_next_window <= 0;
+ Writing_done <= 0;
+ end
+ end
+
+ if (write_ok) begin
+ First_elem_next_window <= First_elem_next_window + tail_incr;
+
+ // check if this is the last write cycle (Writing_done will be true afterwards)
+ if (Current_elem == LAST_WRITE_ELEM) begin
+ Writing_done <= 1;
+
+ if (reading_done || (read_ok && (Newest_buffered_elem == LAST_READ_ELEM - 1))) begin
+ // start processing of next FM if reading is done already, or completes in the same cycle
+ Newest_buffered_elem <= -1;
+ Current_elem <= FIRST_WRITE_ELEM;
+ First_elem_next_window <= 0;
+ Writing_done <= 0;
+ end
+ end
+ else
+ Current_elem <= $signed(Current_elem) + addr_incr;
+ end
+ end
+ end
+
+endmodule : $TOP_MODULE_NAME$_impl
diff --git a/finn-rtllib/swg/swg_template_wrapper.v b/finn-rtllib/swg/swg_template_wrapper.v
index 0cc3579a255fddaf1a470d440b9e8ac245abe486..11fa0a88cbd80f466148eef0102466690af5b9c8 100644
--- a/finn-rtllib/swg/swg_template_wrapper.v
+++ b/finn-rtllib/swg/swg_template_wrapper.v
@@ -28,19 +28,19 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
-`timescale 1 ns / 1 ps
module $TOP_MODULE_NAME$ (
-(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *)
-input ap_clk,
-(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *)
-input ap_rst_n,
-input [BUF_IN_WIDTH-1:0] in0_V_TDATA,
-input in0_V_TVALID,
-output in0_V_TREADY,
-output [BUF_OUT_WIDTH-1:0] out_V_TDATA,
-output out_V_TVALID,
-input out_V_TREADY
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *)
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
+ input ap_clk,
+ (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
+ input ap_rst_n,
+ input [BUF_IN_WIDTH-1:0] in0_V_TDATA,
+ input in0_V_TVALID,
+ output in0_V_TREADY,
+ output [BUF_OUT_WIDTH-1:0] out_V_TDATA,
+ output out_V_TVALID,
+ input out_V_TREADY
);
// top-level parameters (set via code-generation)
@@ -53,23 +53,20 @@ parameter MMV_OUT = $MMV_OUT$;
parameter BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN;
parameter BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT;
-$TOP_MODULE_NAME$_impl
-#(
- .BIT_WIDTH(BIT_WIDTH),
- .SIMD(SIMD),
- .MMV_IN(MMV_IN),
- .MMV_OUT(MMV_OUT)
-)
-impl
-(
- .ap_clk(ap_clk),
- .ap_rst_n(ap_rst_n),
- .in0_V_V_TDATA(in0_V_TDATA),
- .in0_V_V_TVALID(in0_V_TVALID),
- .in0_V_V_TREADY(in0_V_TREADY),
- .out_V_V_TDATA(out_V_TDATA),
- .out_V_V_TVALID(out_V_TVALID),
- .out_V_V_TREADY(out_V_TREADY)
+$TOP_MODULE_NAME$_impl #(
+ .BIT_WIDTH(BIT_WIDTH),
+ .SIMD(SIMD),
+ .MMV_IN(MMV_IN),
+ .MMV_OUT(MMV_OUT)
+) impl (
+ .ap_clk(ap_clk),
+ .ap_rst_n(ap_rst_n),
+ .in0_V_V_TDATA(in0_V_TDATA),
+ .in0_V_V_TVALID(in0_V_TVALID),
+ .in0_V_V_TREADY(in0_V_TREADY),
+ .out_V_V_TDATA(out_V_TDATA),
+ .out_V_V_TVALID(out_V_TVALID),
+ .out_V_V_TREADY(out_V_TREADY)
);
-endmodule //TOP_MODULE_NAME
+endmodule : $TOP_MODULE_NAME$
diff --git a/finn-rtllib/swg/swg_template_wrapper_dynamic.v b/finn-rtllib/swg/swg_template_wrapper_dynamic.v
index ca870ace11edcf097645bc12b0486ffbb83b0ea4..5c09e7c1b4b80aa6f7b9e632750f24cee52898b4 100644
--- a/finn-rtllib/swg/swg_template_wrapper_dynamic.v
+++ b/finn-rtllib/swg/swg_template_wrapper_dynamic.v
@@ -1,4 +1,33 @@
-`timescale 1 ns / 1 ps
+/******************************************************************************
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
module $TOP_MODULE_NAME$ #(
// top-level parameters (set via code-generation)
@@ -18,9 +47,10 @@ module $TOP_MODULE_NAME$ #(
parameter integer C_s_axilite_ADDR_WIDTH = 6
)
(
- (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
+ (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite, ASSOCIATED_RESET ap_rst_n" *)
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input ap_clk,
- (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
+ (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input ap_rst_n,
input [BUF_IN_WIDTH-1:0] in0_V_TDATA,
input in0_V_TVALID,
@@ -113,17 +143,14 @@ $TOP_MODULE_NAME$_axilite # (
.cfg_reg15(cfg_last_write)
);
-$TOP_MODULE_NAME$_impl
-#(
+$TOP_MODULE_NAME$_impl #(
.BIT_WIDTH(BIT_WIDTH),
.SIMD(SIMD),
.MMV_IN(MMV_IN),
.MMV_OUT(MMV_OUT),
.CNTR_BITWIDTH(CNTR_BITWIDTH),
.INCR_BITWIDTH(INCR_BITWIDTH)
-)
-impl
-(
+) impl (
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.in0_V_V_TDATA(in0_V_TDATA),
@@ -151,4 +178,4 @@ impl
.cfg_last_write(cfg_last_write)
);
-endmodule //TOP_MODULE_NAME
+endmodule : $TOP_MODULE_NAME$
diff --git a/notebooks/advanced/0_custom_analysis_pass.ipynb b/notebooks/advanced/0_custom_analysis_pass.ipynb
index f8444520c3ded795702420d7f86335d0048ef043..f915b11fa052e0f2c3b4c056a5147bec61c87fd8 100644
--- a/notebooks/advanced/0_custom_analysis_pass.ipynb
+++ b/notebooks/advanced/0_custom_analysis_pass.ipynb
@@ -52,7 +52,9 @@
"metadata": {},
"outputs": [],
"source": [
- "showInNetron(\"../LFCW1A1.onnx\")"
+ "import os\n",
+ "notebook_dir = os.environ['FINN_ROOT'] + \"/notebooks\"\n",
+ "showInNetron(notebook_dir + \"/LFCW1A1.onnx\")"
]
},
{
@@ -69,7 +71,7 @@
"outputs": [],
"source": [
"from qonnx.core.modelwrapper import ModelWrapper\n",
- "model = ModelWrapper('../LFCW1A1.onnx')"
+ "model = ModelWrapper(notebook_dir + \"/LFCW1A1.onnx\")"
]
},
{
diff --git a/notebooks/advanced/1_custom_transformation_pass.ipynb b/notebooks/advanced/1_custom_transformation_pass.ipynb
index 391e852a71e1109b376abd7bb5d5f9d264d06498..7e4989c902a65167c8ed7ed4a591fcb0dbad7011 100644
--- a/notebooks/advanced/1_custom_transformation_pass.ipynb
+++ b/notebooks/advanced/1_custom_transformation_pass.ipynb
@@ -110,8 +110,11 @@
"metadata": {},
"outputs": [],
"source": [
+ "import os\n",
+ "notebook_dir = os.environ['FINN_ROOT'] + \"/notebooks\"\n",
+ "\n",
"import onnx\n",
- "onnx_model = onnx.load('../LFCW1A1.onnx')\n",
+ "onnx_model = onnx.load(notebook_dir + \"/LFCW1A1.onnx\")\n",
"from qonnx.core.modelwrapper import ModelWrapper\n",
"onnx_model = ModelWrapper(onnx_model)"
]
@@ -122,7 +125,7 @@
"metadata": {},
"outputs": [],
"source": [
- "showInNetron('../LFCW1A1.onnx')"
+ "showInNetron(notebook_dir + \"/LFCW1A1.onnx\")"
]
},
{
diff --git a/notebooks/basics/1_brevitas_network_import.ipynb b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb
similarity index 93%
rename from notebooks/basics/1_brevitas_network_import.ipynb
rename to notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb
index a884e90d7572789fc64cf9b953b5730590d4e8f1..756faf149d125b7c779b89a413953b6205c21e3e 100644
--- a/notebooks/basics/1_brevitas_network_import.ipynb
+++ b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb
@@ -4,7 +4,9 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "# Importing Brevitas networks into FINN\n",
+ "# Importing Brevitas networks into FINN with the FINN-ONNX interchange format\n",
+ "\n",
+ "**Note: This notebook is very similar to the 1b notebook, in that it shows the same concepts for the FINN-ONNX ingestion as 1b does for QONNX. Section 1 is identical in both notebooks.**\n",
"\n",
"In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n",
"\n",
@@ -137,10 +139,10 @@
"metadata": {},
"outputs": [],
"source": [
- "import brevitas.onnx as bo\n",
- "export_onnx_path = \"/tmp/LFCW1A1.onnx\"\n",
+ "from brevitas.export import export_finn_onnx\n",
+ "export_onnx_path = \"/tmp/LFCW1A1_finn-onnx.onnx\"\n",
"input_shape = (1, 1, 28, 28)\n",
- "bo.export_finn_onnx(lfc, input_shape, export_onnx_path)"
+ "export_finn_onnx(lfc, torch.randn(input_shape), export_onnx_path);"
]
},
{
@@ -156,7 +158,7 @@
"metadata": {},
"outputs": [],
"source": [
- "showInNetron('/tmp/LFCW1A1.onnx')"
+ "showInNetron(export_onnx_path)"
]
},
{
@@ -244,7 +246,7 @@
"from qonnx.transformation.infer_shapes import InferShapes\n",
"model = model.transform(InferShapes())\n",
"model = model.transform(FoldConstants())\n",
- "export_onnx_path_transformed = \"/tmp/LFCW1A1-clean.onnx\"\n",
+ "export_onnx_path_transformed = \"/tmp/LFCW1A1-finn-onnx-clean.onnx\"\n",
"model.save(export_onnx_path_transformed)"
]
},
@@ -254,7 +256,7 @@
"metadata": {},
"outputs": [],
"source": [
- "showInNetron('/tmp/LFCW1A1-clean.onnx')"
+ "showInNetron(export_onnx_path_transformed)"
]
},
{
diff --git a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb
new file mode 100644
index 0000000000000000000000000000000000000000..58fa3fc7e185919b896f121f1a55c5e88ec26000
--- /dev/null
+++ b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb
@@ -0,0 +1,326 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Importing Brevitas networks into FINN with the QONNX interchange format\n",
+ "\n",
+ "**Note: This notebook is very similar to the 1a notebook, in that it shows the same concepts for the QONNX ingestion as 1a does for FINN-ONNX. Section 1 is identical in both notebooks.**\n",
+ "\n",
+ "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n",
+ "\n",
+ "1. Load up the trained PyTorch model\n",
+ "2. Call Brevitas QONNX export and visualize with Netron\n",
+ "3. Import into FINN and converting QONNX to FINN-ONNX\n",
+ "\n",
+ "We'll use the following utility functions to print the source code for function calls (`showSrc()`) and to visualize a network using netron (`showInNetron()`) in the Jupyter notebook:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import onnx\n",
+ "from finn.util.visualization import showSrc, showInNetron"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 1. Load up the trained PyTorch model\n",
+ "\n",
+ "The FINN Docker image comes with several [example Brevitas networks](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq), and we'll use the LFC-w1a1 model as the example network here. This is a binarized fully connected network trained on the MNIST dataset. Let's start by looking at what the PyTorch network definition looks like:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from brevitas_examples import bnn_pynq\n",
+ "showSrc(bnn_pynq.models.FC)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "We can see that the network topology is constructed using a few helper functions that generate the quantized linear layers and quantized activations. The bitwidth of the layers is actually parametrized in the constructor, so let's instantiate a 1-bit weights and activations version of this network. We also have pretrained weights for this network, which we will load into the model."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from finn.util.test import get_test_model\n",
+ "lfc = get_test_model(netname = \"LFC\", wbits = 1, abits = 1, pretrained = True)\n",
+ "lfc"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "We have now instantiated our trained PyTorch network. Let's try to run an example MNIST image through the network using PyTorch."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import torch\n",
+ "import matplotlib.pyplot as plt\n",
+ "from pkgutil import get_data\n",
+ "import onnx\n",
+ "import onnx.numpy_helper as nph\n",
+ "raw_i = get_data(\"qonnx.data\", \"onnx/mnist-conv/test_data_set_0/input_0.pb\")\n",
+ "input_tensor = onnx.load_tensor_from_string(raw_i)\n",
+ "input_tensor_npy = nph.to_array(input_tensor)\n",
+ "input_tensor_pyt = torch.from_numpy(input_tensor_npy).float()\n",
+ "imgplot = plt.imshow(input_tensor_npy.reshape(28,28), cmap='gray')"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from torch.nn.functional import softmax\n",
+ "# do forward pass in PyTorch/Brevitas\n",
+ "produced = lfc.forward(input_tensor_pyt).detach()\n",
+ "probabilities = softmax(produced, dim=-1).flatten()\n",
+ "probabilities"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import numpy as np\n",
+ "objects = [str(x) for x in range(10)]\n",
+ "y_pos = np.arange(len(objects))\n",
+ "plt.bar(y_pos, probabilities, align='center', alpha=0.5)\n",
+ "plt.xticks(y_pos, objects)\n",
+ "plt.ylabel('Predicted Probability')\n",
+ "plt.title('LFC-w1a1 Predictions for Image')\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Call Brevitas QONNX export and visualize with Netron\n",
+ "\n",
+ "Brevitas comes with built-in QONNX export functionality. This is similar to the regular ONNX export capabilities of PyTorch, with a few differences:\n",
+ "\n",
+ "1. Weight and activation quantization is represented as a 'fake-quantization' with Quant and BipolarQuant nodes.\n",
+ "2. Truncation operations as required by average pooling are represented with a Trunc node.\n",
+ "\n",
+ "One can read more about how QONNX works and why it was developed here: https://xilinx.github.io/finn//2021/11/03/qonnx-and-finn.html\n",
+ "\n",
+ "Additionally QONNX comes with a set of tools for working with the format. These are maintained together with the Fast Machinelearning collaboration as an open-source projet here: https://github.com/fastmachinelearning/qonnx\n",
+ "\n",
+ "It's actually quite straightforward to export QONNX from our Brevitas model as follows:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from brevitas.export import export_qonnx\n",
+ "export_onnx_path = \"/tmp/LFCW1A1_qonnx.onnx\"\n",
+ "input_shape = (1, 1, 28, 28)\n",
+ "export_qonnx(lfc, torch.randn(input_shape), export_onnx_path);"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Let's examine what the exported ONNX model looks like. For this, we will use the Netron visualizer:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "showInNetron(export_onnx_path)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "When running this notebook in the FINN Docker container, you should be able to see an interactive visualization of the imported network above, and click on individual nodes to inspect their parameters. If you look at any of the MatMul nodes, you should be able to see that the weights are all {-1, +1} values."
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Import into FINN and converting QONNX to FINN-ONNX\n",
+ "\n",
+ "Similarily to the 1a notebook we will first run a cleanup transformation on the exported QONNX model."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from qonnx.util.cleanup import cleanup\n",
+ "\n",
+ "export_onnx_path_cleaned = \"/tmp/LFCW1A1-qonnx-clean.onnx\"\n",
+ "cleanup(export_onnx_path, out_file=export_onnx_path_cleaned)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "showInNetron(export_onnx_path_cleaned)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "We will now import this QONNX model into FINN using the ModelWrapper. Here we can immediatley execute the model to verify correctness."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from qonnx.core.modelwrapper import ModelWrapper\n",
+ "import qonnx.core.onnx_exec as oxe\n",
+ "model = ModelWrapper(export_onnx_path_cleaned)\n",
+ "input_dict = {\"global_in\": nph.to_array(input_tensor)}\n",
+ "output_dict = oxe.execute_onnx(model, input_dict)\n",
+ "produced_qonnx = output_dict[list(output_dict.keys())[0]]\n",
+ "\n",
+ "produced_qonnx"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "np.isclose(produced, produced_qonnx).all()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Using the `QONNXtoFINN` transformation we can convert the model to the FINN internal FINN-ONNX representation. Notably all Quant and BipolarQuant nodes will have disappeared and are converted into MultiThreshold nodes."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN\n",
+ "model = ModelWrapper(export_onnx_path_cleaned)\n",
+ "\n",
+ "model = model.transform(ConvertQONNXtoFINN())\n",
+ "\n",
+ "export_onnx_path_converted = \"/tmp/LFCW1A1-qonnx-converted.onnx\"\n",
+ "model.save(export_onnx_path_converted)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "showInNetron(export_onnx_path_converted)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "And once again we can execute the model with the FINN/QONNX execution engine."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "model = ModelWrapper(export_onnx_path_cleaned)\n",
+ "input_dict = {\"global_in\": nph.to_array(input_tensor)}\n",
+ "output_dict = oxe.execute_onnx(model, input_dict)\n",
+ "produced_finn = output_dict[list(output_dict.keys())[0]]\n",
+ "\n",
+ "produced_finn"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "np.isclose(produced_qonnx, produced_finn).all()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "We have succesfully verified that the transformed and cleaned-up FINN graph still produces the same output, and can now use this model for further processing in FINN."
+ ]
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3 (ipykernel)",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.8.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}
diff --git a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb
index 388accad3aa2bb2633fb691241d234442d59bb11..73e9f4e6e1f6f01f6d3dc0e934615cb25c70278f 100644
--- a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb
+++ b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb
@@ -81,16 +81,17 @@
"metadata": {},
"outputs": [],
"source": [
+ "import torch\n",
"import onnx\n",
"from finn.util.test import get_test_model_trained\n",
- "import brevitas.onnx as bo\n",
+ "from brevitas.export import export_finn_onnx\n",
"from qonnx.core.modelwrapper import ModelWrapper\n",
"from qonnx.transformation.infer_shapes import InferShapes\n",
"from qonnx.transformation.fold_constants import FoldConstants\n",
"from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, RemoveStaticGraphInputs\n",
"\n",
"cnv = get_test_model_trained(\"CNV\", 1, 1)\n",
- "bo.export_finn_onnx(cnv, (1, 3, 32, 32), build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n",
+ "export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n",
"model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n",
"model = model.transform(InferShapes())\n",
"model = model.transform(FoldConstants())\n",
@@ -148,7 +149,7 @@
"# preprocessing: torchvision's ToTensor divides uint8 inputs by 255\n",
"totensor_pyt = ToTensor()\n",
"chkpt_preproc_name = build_dir+\"/end2end_cnv_w1a1_preproc.onnx\"\n",
- "bo.export_finn_onnx(totensor_pyt, ishape, chkpt_preproc_name)\n",
+ "export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n",
"\n",
"# join preprocessing and core model\n",
"pre_model = ModelWrapper(chkpt_preproc_name)\n",
@@ -240,7 +241,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "We won't go into too much detail about what happens in each transformation and why they are called in the particular order they are (feel free to visualize the intermediate steps using Netron yourself if you are curious) but here is a brief summmmary:\n",
+ "We won't go into too much detail about what happens in each transformation and why they are called in the particular order they are (feel free to visualize the intermediate steps using Netron yourself if you are curious) but here is a brief summary:\n",
"\n",
"* `Streamline` moves floating point scaling and addition operations closer to the input of the nearest thresholding activation and absorbs them into thresholds\n",
"* `LowerConvsToMatMul` converts ONNX `Conv` nodes into sequences of `Im2Col, MatMul` nodes as discussed above. `Im2Col` is a custom FINN ONNX high-level node type that implements the sliding window operator.\n",
diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb
index eec17b2fa7e8226cafe48f095aa38eb704b2812e..f99944e31f3e45f08b53bfd53b373fa726e09a49 100644
--- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb
+++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb
@@ -81,12 +81,13 @@
"metadata": {},
"outputs": [],
"source": [
+ "import torch\n",
"import onnx\n",
"from finn.util.test import get_test_model_trained\n",
- "import brevitas.onnx as bo\n",
+ "from brevitas.export import export_finn_onnx\n",
"\n",
"tfc = get_test_model_trained(\"TFC\", 1, 1)\n",
- "bo.export_finn_onnx(tfc, (1, 1, 28, 28), build_dir+\"/tfc_w1_a1.onnx\"); # semicolon added to suppress log"
+ "export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), build_dir+\"/tfc_w1_a1.onnx\"); # semicolon added to suppress log"
]
},
{
@@ -267,7 +268,7 @@
"# preprocessing: torchvision's ToTensor divides uint8 inputs by 255\n",
"totensor_pyt = ToTensor()\n",
"chkpt_preproc_name = build_dir+\"/tfc_w1_a1_preproc.onnx\"\n",
- "bo.export_finn_onnx(totensor_pyt, ishape, chkpt_preproc_name)\n",
+ "export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n",
"\n",
"# join preprocessing and core model\n",
"pre_model = ModelWrapper(chkpt_preproc_name)\n",
diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb
index 6c3b7965098e013fa35ac5f5b2b481e678d68f5d..2f6cde6e5b895cfa9a4146bd11fca3e0d791c2f9 100644
--- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb
+++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb
@@ -121,12 +121,11 @@
"output_dict = oxe.execute_onnx(model_for_sim, input_dict, return_full_exec_context=False)\n",
"output_pysim = output_dict[list(output_dict.keys())[0]]\n",
"\n",
- "\n",
- "\n",
- "if np.isclose(output_pysim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n",
+ "try:\n",
+ " assert np.isclose(output_pysim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n",
" print(\"Results are the same!\")\n",
- "else:\n",
- " print(\"The results are not the same!\")"
+ "except AssertionError:\n",
+ " assert False, \"The results are not the same!\""
]
},
{
@@ -268,10 +267,11 @@
"output_dict = oxe.execute_onnx(parent_model, input_dict)\n",
"output_cppsim = output_dict[list(output_dict.keys())[0]]\n",
"\n",
- "if np.isclose(output_cppsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n",
+ "try:\n",
+ " assert np.isclose(output_cppsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n",
" print(\"Results are the same!\")\n",
- "else:\n",
- " print(\"The results are not the same!\")"
+ "except AssertionError:\n",
+ " assert False, \"The results are not the same!\""
]
},
{
@@ -356,10 +356,11 @@
"output_dict = oxe.execute_onnx(model_for_rtlsim, input_dict)\n",
"output_rtlsim = output_dict[list(output_dict.keys())[0]]\n",
"\n",
- "if np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n",
+ "try:\n",
+ " assert np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n",
" print(\"Results are the same!\")\n",
- "else:\n",
- " print(\"The results are not the same!\")"
+ "except AssertionError:\n",
+ " assert False, \"The results are not the same!\""
]
},
{
@@ -430,10 +431,11 @@
"metadata": {},
"outputs": [],
"source": [
- "if np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n",
+ "try:\n",
+ " assert np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n",
" print(\"Results are the same!\")\n",
- "else:\n",
- " print(\"The results are not the same!\")"
+ "except AssertionError:\n",
+ " assert False, \"The results are not the same!\""
]
}
],
diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb
index 3d77586258b9ddb64985e7f7b7a2215565839c50..0f90b8ee78f3113ce4f0a2fa5738771be60ed19e 100644
--- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb
+++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb
@@ -62,8 +62,11 @@
"metadata": {},
"outputs": [],
"source": [
+ "import os\n",
"import onnx\n",
- "import torch"
+ "import torch\n",
+ "\n",
+ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity\""
]
},
{
@@ -483,13 +486,14 @@
"metadata": {},
"outputs": [],
"source": [
+ "import os\n",
"import torch\n",
"\n",
"# Make sure the model is on CPU before loading a pretrained state_dict\n",
"model = model.cpu()\n",
"\n",
"# Load pretrained weights\n",
- "trained_state_dict = torch.load(\"state_dict.pth\")[\"models_state_dict\"][0]\n",
+ "trained_state_dict = torch.load(model_dir + \"/state_dict.pth\")[\"models_state_dict\"][0]\n",
"\n",
"model.load_state_dict(trained_state_dict, strict=False)"
]
@@ -677,10 +681,10 @@
"metadata": {},
"outputs": [],
"source": [
- "import brevitas.onnx as bo\n",
+ "from brevitas.export import export_finn_onnx\n",
"from brevitas.quant_tensor import QuantTensor\n",
"\n",
- "ready_model_filename = \"cybsec-mlp-ready.onnx\"\n",
+ "ready_model_filename = model_dir + \"/cybsec-mlp-ready.onnx\"\n",
"input_shape = (1, 600)\n",
"\n",
"# create a QuantTensor instance to mark input as bipolar during export\n",
@@ -696,7 +700,7 @@
"model_for_export.cpu()\n",
"\n",
"# Export to ONNX\n",
- "bo.export_finn_onnx(\n",
+ "export_finn_onnx(\n",
" model_for_export, export_path=ready_model_filename, input_t=input_qt\n",
")\n",
"\n",
diff --git a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb
index e4848a1f40bed5865eccc1d831a634ac5f54e965..5f4924b30989eb7089bc32117cb1e1a0d82f2e09 100644
--- a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb
+++ b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb
@@ -62,9 +62,11 @@
"metadata": {},
"outputs": [],
"source": [
+ "import os\n",
"from qonnx.core.modelwrapper import ModelWrapper\n",
"\n",
- "ready_model_filename = \"cybsec-mlp-ready.onnx\"\n",
+ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity\"\n",
+ "ready_model_filename = model_dir + \"/cybsec-mlp-ready.onnx\"\n",
"model_for_sim = ModelWrapper(ready_model_filename)"
]
},
@@ -151,7 +153,7 @@
"model_for_sim = model_for_sim.transform(InferDataTypes())\n",
"model_for_sim = model_for_sim.transform(RemoveStaticGraphInputs())\n",
"\n",
- "verif_model_filename = \"cybsec-mlp-verification.onnx\"\n",
+ "verif_model_filename = model_dir + \"/cybsec-mlp-verification.onnx\"\n",
"model_for_sim.save(verif_model_filename)"
]
},
@@ -258,7 +260,8 @@
"\n",
"# replace this with your trained network checkpoint if you're not\n",
"# using the pretrained weights\n",
- "trained_state_dict = torch.load(\"state_dict.pth\")[\"models_state_dict\"][0]\n",
+ "trained_state_dict = torch.load(model_dir + \"/state_dict.pth\")[\"models_state_dict\"][0]\n",
+ "\n",
"# Uncomment the following line if you previously chose to train the network yourself\n",
"#trained_state_dict = torch.load(\"state_dict_self-trained.pth\")\n",
"\n",
@@ -365,10 +368,11 @@
"metadata": {},
"outputs": [],
"source": [
- "if ok == n_verification_inputs:\n",
+ "try:\n",
+ " assert ok == n_verification_inputs\n",
" print(\"Verification succeeded. Brevitas and FINN-ONNX execution outputs are identical\")\n",
- "else:\n",
- " print(\"Verification failed. Brevitas and FINN-ONNX execution outputs are NOT identical\")"
+ "except AssertionError:\n",
+ " assert False, \"Verification failed. Brevitas and FINN-ONNX execution outputs are NOT identical\""
]
},
{
diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
index a18cafd6044328d53139acafb2be2cf73a4ec9b6..80f3cd3819a76b5ad538f28f48e85fd22c660f20 100644
--- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
+++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb
@@ -115,7 +115,8 @@
"import os\n",
"import shutil\n",
"\n",
- "model_file = \"cybsec-mlp-ready.onnx\"\n",
+ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity\"\n",
+ "model_file = model_dir + \"/cybsec-mlp-ready.onnx\"\n",
"\n",
"estimates_output_dir = \"output_estimates_only\"\n",
"\n",
@@ -148,6 +149,15 @@
"build.build_dataflow_cfg(model_file, cfg_estimates)"
]
},
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "assert os.path.exists(estimates_output_dir + \"/report/estimate_network_performance.json\")"
+ ]
+ },
{
"cell_type": "markdown",
"metadata": {},
@@ -272,7 +282,7 @@
"import os\n",
"import shutil\n",
"\n",
- "model_file = \"cybsec-mlp-ready.onnx\"\n",
+ "model_file = model_dir + \"/cybsec-mlp-ready.onnx\"\n",
"\n",
"rtlsim_output_dir = \"output_ipstitch_ooc_rtlsim\"\n",
"\n",
@@ -305,6 +315,17 @@
"build.build_dataflow_cfg(model_file, cfg_stitched_ip)"
]
},
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "assert os.path.exists(rtlsim_output_dir + \"/report/ooc_synth_and_timing.json\")\n",
+ "assert os.path.exists(rtlsim_output_dir + \"/report/rtlsim_performance.json\")\n",
+ "assert os.path.exists(rtlsim_output_dir + \"/final_hw_config.json\")"
+ ]
+ },
{
"cell_type": "markdown",
"metadata": {},
@@ -412,7 +433,7 @@
"import os\n",
"import shutil\n",
"\n",
- "model_file = \"cybsec-mlp-ready.onnx\"\n",
+ "model_file = model_dir + \"/cybsec-mlp-ready.onnx\"\n",
"\n",
"final_output_dir = \"output_final\"\n",
"\n",
diff --git a/requirements.txt b/requirements.txt
index 83aad07d729e30cbbbaf565b4332fb1f7ae6f014..223138932e4dbae3f67a70ee3bcb10ba905bf83f 100644
--- a/requirements.txt
+++ b/requirements.txt
@@ -1,8 +1,8 @@
bitstring==3.1.7
clize==4.1.1
dataclasses-json==0.5.7
-docrep==0.2.7
gspread==3.6.0
+ipython==8.12.2
numpy==1.22.0
onnx==1.13.0
onnxoptimizer
@@ -14,6 +14,8 @@ pyscaffold==3.2.1
scipy==1.5.2
setupext-janitor>=1.1.2
sigtools==2.0.3
+sphinx==5.0.2
+sphinx_rtd_theme==0.5.0
toposort==1.5
vcdvcd==1.0.5
wget==3.2
diff --git a/setup.cfg b/setup.cfg
index 1893aa42316dad341fcedbd527f5abcf482e5cfb..50a91498ce994ba3672cd2e2bbc2aa73f7fa0406 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -81,6 +81,8 @@ docs =
pytest
netron
vcdvcd
+ sphinx==5.0.2
+ sphinx_rtd_theme==0.5.0
torchvision
torch
qonnx@git+https://github.com/fastmachinelearning/qonnx@main#egg=qonnx
@@ -127,6 +129,7 @@ markers =
transform: mark tests that test transformations (before hls layers)
fpgadataflow: mark tests related to hls layers
end2end: mark tests that run the end2end flow
+ notebooks: mark tests that execute all Jupyter notebooks
norecursedirs =
dist
build
diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py
index a38cb6e572d683871a924330742a1859b6fbe75d..4c3e4ff899513bf9939612e04621140d84be1bd1 100644
--- a/src/finn/builder/build_dataflow_config.py
+++ b/src/finn/builder/build_dataflow_config.py
@@ -119,6 +119,7 @@ default_build_dataflow_steps = [
"step_create_dataflow_partition",
"step_target_fps_parallelization",
"step_apply_folding_config",
+ "step_minimize_bit_width",
"step_generate_estimate_reports",
"step_hls_codegen",
"step_hls_ipgen",
@@ -140,6 +141,7 @@ estimate_only_dataflow_steps = [
"step_create_dataflow_partition",
"step_target_fps_parallelization",
"step_apply_folding_config",
+ "step_minimize_bit_width",
"step_generate_estimate_reports",
]
@@ -233,6 +235,12 @@ class DataflowBuildConfig:
#: flexibility, and makes it possible to have runtime-writable thresholds.
standalone_thresholds: Optional[bool] = False
+ #: (Optional) Whether optimizations that minimize the bit width of the
+ #: weights and accumulator will be applied. Because this optimization relies
+ #: on the the values of the weights, it will only be applied if runtime-
+ #: writeable weights is not enabled.
+ minimize_bit_width: Optional[bool] = True
+
#: Target board, only needed for generating full bitfiles where the FINN
#: design is integrated into a shell.
#: e.g. "Pynq-Z1" or "U250"
diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py
index 2ee898bc7d50822f962b6a70cf86b2893e0937b7..a22b5adc9846af22833568065a0c31e6e9a4d111 100644
--- a/src/finn/builder/build_dataflow_steps.py
+++ b/src/finn/builder/build_dataflow_steps.py
@@ -89,6 +89,12 @@ from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
from finn.transformation.fpgadataflow.make_zynq_proj import ZynqBuild
+from finn.transformation.fpgadataflow.minimize_accumulator_width import (
+ MinimizeAccumulatorWidth,
+)
+from finn.transformation.fpgadataflow.minimize_weight_bit_width import (
+ MinimizeWeightBitWidth,
+)
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
@@ -410,6 +416,7 @@ def step_target_fps_parallelization(model: ModelWrapper, cfg: DataflowBuildConfi
hw_attrs = [
"PE",
"SIMD",
+ "parallel_window",
"ram_style",
"resType",
"mem_mode",
@@ -477,6 +484,16 @@ def step_generate_estimate_reports(model: ModelWrapper, cfg: DataflowBuildConfig
return model
+def step_minimize_bit_width(model: ModelWrapper, cfg: DataflowBuildConfig):
+ """Tighten the weight and accumulator bit widths for each layer."""
+ if cfg.minimize_bit_width:
+ model = model.transform(MinimizeWeightBitWidth())
+ model = model.transform(MinimizeAccumulatorWidth())
+ # make sure the changed datatypes are propagated through the network
+ model = model.transform(InferDataTypes())
+ return model
+
+
def step_hls_codegen(model: ModelWrapper, cfg: DataflowBuildConfig):
"Generate Vivado HLS code to prepare HLSCustomOp nodes for IP generation."
@@ -572,6 +589,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig):
hw_attrs = [
"PE",
"SIMD",
+ "parallel_window",
"ram_style",
"depth",
"impl_style",
@@ -668,7 +686,6 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi
rtlsim_bs = int(cfg.rtlsim_batch_size)
orig_rtlsim_trace_depth = get_rtlsim_trace_depth()
if force_python_rtlsim:
- # run with single input to get latency
assert rtlsim_bs > 0, "rtlsim batch size must be >0"
if cfg.verify_save_rtlsim_waveforms:
# set depth to 3 for layer-by-layer visibility
@@ -680,9 +697,11 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi
rtlsim_model.set_metadata_prop(
"extra_verilator_args", str(["-CFLAGS", "-O3"])
)
+ # run with single input to get latency
+ rtlsim_latency_dict = throughput_test_rtlsim(rtlsim_model, 1)
+ # run with batch to get stable-state throughput
rtlsim_perf_dict = throughput_test_rtlsim(rtlsim_model, rtlsim_bs)
- rtlsim_latency = rtlsim_perf_dict["cycles"]
- rtlsim_perf_dict["latency_cycles"] = rtlsim_latency
+ rtlsim_perf_dict["latency_cycles"] = rtlsim_latency_dict["cycles"]
else:
rtlsim_perf_dict = verilator_fifosim(model, rtlsim_bs)
# keep keys consistent between the Python and C++-styles
@@ -696,6 +715,19 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi
for (key, val) in rtlsim_perf_dict.items():
if "max_count" in key:
del rtlsim_perf_dict[key]
+ # estimate stable-state throughput based on latency+throughput
+ if rtlsim_bs == 1:
+ rtlsim_perf_dict["stable_throughput[images/s]"] = rtlsim_perf_dict[
+ "throughput[images/s]"
+ ]
+ else:
+ total_cycles = rtlsim_perf_dict["cycles"]
+ latency_cycles = rtlsim_perf_dict["latency_cycles"]
+ stablestate_cycles = total_cycles - latency_cycles
+ clk_ns = float(model.get_metadata_prop("clk_ns"))
+ fclk_mhz = 1 / (clk_ns * 0.001)
+ runtime_s = (stablestate_cycles * clk_ns) * (10**-9)
+ rtlsim_perf_dict["stable_throughput[images/s]"] = rtlsim_bs / runtime_s
with open(report_dir + "/rtlsim_performance.json", "w") as f:
json.dump(rtlsim_perf_dict, f, indent=2)
@@ -823,6 +855,7 @@ build_dataflow_step_lookup = {
"step_create_dataflow_partition": step_create_dataflow_partition,
"step_target_fps_parallelization": step_target_fps_parallelization,
"step_apply_folding_config": step_apply_folding_config,
+ "step_minimize_bit_width": step_minimize_bit_width,
"step_generate_estimate_reports": step_generate_estimate_reports,
"step_hls_codegen": step_hls_codegen,
"step_hls_ipgen": step_hls_ipgen,
diff --git a/src/finn/core/onnx_exec.py b/src/finn/core/onnx_exec.py
index 2695113661ed286c94ae9cb5f20ca99cc1fced7f..daecb59743d1b843e9d7fd40fdbf5bf10fac2fe1 100644
--- a/src/finn/core/onnx_exec.py
+++ b/src/finn/core/onnx_exec.py
@@ -31,7 +31,6 @@ import numpy as np
import qonnx.analysis.topology as ta
from qonnx.core.onnx_exec import execute_onnx as execute_onnx_base
-from finn.core.remote_exec import remote_exec
from finn.core.rtlsim_exec import rtlsim_exec
@@ -51,7 +50,6 @@ def execute_onnx(
# check if model has an execution mode set
# if None, execute model node using the QONNX-provided execute_onnx impl
- # if set to "remote_pynq" execute model on PYNQ board
# if set to "rtlsim" execute model using pyverilator
model_exec_mode = model.get_metadata_prop("exec_mode")
if (model_exec_mode is None) or (model_exec_mode == ""):
@@ -91,22 +89,17 @@ def execute_onnx(
# check if model has an execution mode set
# if None, execute model node by node using execute_node()
- # if set to "remote_pynq" execute model on PYNQ board
# if set to "rtlsim" execute model using pyverilator
model_exec_mode = model.get_metadata_prop("exec_mode")
if (model_exec_mode is None) or (model_exec_mode == ""):
return execute_onnx_base()
- elif model_exec_mode == "remote_pynq":
- # use remote exec metadata built into model to execute on a remote PYNQ
- remote_exec(model, execution_context)
elif model_exec_mode == "rtlsim":
# use stitched IP for rtlsim
rtlsim_exec(model, execution_context)
else:
raise Exception(
- """Metadata property "exec_mode" is set to an unknown value.
- Can be left unset or has to be set to "remote_pynq" for remote execution
- on PYNQ board or "rtlsim" for execution using pyverilator!"""
+ """Metadata property "exec_mode" is set to an unknown value. Can be left
+ unset or has to be set to "rtlsim" for execution using pyverilator!"""
)
if return_full_exec_context:
diff --git a/src/finn/core/remote_exec.py b/src/finn/core/remote_exec.py
deleted file mode 100644
index f487b48f86f1ef0440ed4a8bf371083369dd096c..0000000000000000000000000000000000000000
--- a/src/finn/core/remote_exec.py
+++ /dev/null
@@ -1,119 +0,0 @@
-# Copyright (c) 2020 Xilinx, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of Xilinx nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import numpy as np
-import os
-import subprocess
-import warnings
-
-
-def remote_exec(model, execution_context):
- """Executes the given model remotely on the pynq board. The metadata properties
- related to the pynq board have to be set. The execution context contains the
- input values."""
- # TODO fix for multi input-output
- pynq_ip = model.get_metadata_prop("pynq_ip")
- pynq_port = int(model.get_metadata_prop("pynq_port"))
- pynq_username = model.get_metadata_prop("pynq_username")
- pynq_password = model.get_metadata_prop("pynq_password")
- pynq_target_dir = model.get_metadata_prop("pynq_target_dir")
- deployment_dir = model.get_metadata_prop("pynq_deploy_dir")
- platform = model.get_metadata_prop("platform")
- assert platform in ["alveo", "zynq-iodma"]
- bitfile = model.get_metadata_prop("bitfile")
- bitfile = os.path.basename(bitfile)
- if pynq_password == "":
- if "zynq" in platform:
- raise Exception("PYNQ board remote exec needs password for sudo")
- else:
- local_prefix = "" # assume we are using an ssh key
- warnings.warn("Empty password, make sure you've set up an ssh key")
- else:
- local_prefix = "sshpass -p %s " % pynq_password
-
- if platform == "alveo":
- # Alveo can run without sudo
- remote_prefix = ""
- elif "zynq" in platform:
- # PYNQ Zynq boards need to execute with sudo
- remote_prefix = "echo %s | sudo -S " % pynq_password
-
- inp = execution_context[model.graph.input[0].name]
- # make copy of array before saving it
- inp = inp.copy()
- batchsize = inp.shape[0]
- np.save(os.path.join(deployment_dir, "input.npy"), inp)
- # extracting last folder of absolute path (deployment_dir)
- deployment_folder = os.path.basename(os.path.normpath(deployment_dir))
- # copy input to PYNQ board
- cmd = local_prefix + "scp -P{} -r {}/input.npy {}@{}:{}/{}".format(
- pynq_port,
- deployment_dir,
- pynq_username,
- pynq_ip,
- pynq_target_dir,
- deployment_folder,
- )
- bash_command = ["/bin/bash", "-c", cmd]
- process_scp_in = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
- process_scp_in.communicate()
-
- # use platform attribute for correct remote execution
- if platform == "alveo":
- remote_cmd = "bash -ic 'bash alveo_run.sh execute %d' \"" % batchsize
- else:
- remote_cmd = (
- "python3.6 driver.py --exec_mode=execute --batchsize={} "
- "--bitfile={} --inputfile=input.npy --outputfile=output.npy "
- '--platform={} "'
- ).format(batchsize, bitfile, platform)
- cmd = (
- local_prefix + 'ssh {}@{} -p {} "cd {}/{}; ' + remote_prefix + remote_cmd
- ).format(pynq_username, pynq_ip, pynq_port, pynq_target_dir, deployment_folder)
- bash_command = ["/bin/bash", "-c", cmd]
- process_exec_accel = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
- process_exec_accel.communicate()
- # remove stale output file from local dir, if any
- try:
- os.remove("{}/output.npy".format(deployment_dir))
- except FileNotFoundError:
- pass
- # copy generated output to local
- cmd = local_prefix + "scp -P{} {}@{}:{}/{}/output.npy {}".format(
- pynq_port,
- pynq_username,
- pynq_ip,
- pynq_target_dir,
- deployment_folder,
- deployment_dir,
- )
- bash_command = ["/bin/bash", "-c", cmd]
- process_scp_out = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
- process_scp_out.communicate()
- outp = np.load("{}/output.npy".format(deployment_dir))
- execution_context[model.graph.output[0].name] = outp
diff --git a/src/finn/core/throughput_test.py b/src/finn/core/throughput_test.py
index 3533fd13399a4ba4392d66af785979afc32cab29..08633be33b8ab6d096275aca2c362a8bac43d704 100644
--- a/src/finn/core/throughput_test.py
+++ b/src/finn/core/throughput_test.py
@@ -28,90 +28,11 @@
import numpy as np
import os
-import subprocess
-import warnings
from qonnx.util.basic import gen_finn_dt_tensor
from finn.core.rtlsim_exec import rtlsim_exec
-def throughput_test_remote(model, batchsize=1000, timeout=None):
- """Runs the throughput test for the given model remotely on the pynq board.
- The metadata properties related to the pynq board have to be set.
- Additionally a timeout for the SSH communication can be set.
- Returns a dictionary with results of the throughput test. Returns None
- if the test fails."""
-
- pynq_ip = model.get_metadata_prop("pynq_ip")
- pynq_port = int(model.get_metadata_prop("pynq_port"))
- pynq_username = model.get_metadata_prop("pynq_username")
- pynq_password = model.get_metadata_prop("pynq_password")
- pynq_target_dir = model.get_metadata_prop("pynq_target_dir")
- deployment_dir = model.get_metadata_prop("pynq_deploy_dir")
- # extracting last folder of absolute path (deployment_dir)
- deployment_folder = os.path.basename(os.path.normpath(deployment_dir))
- platform = model.get_metadata_prop("platform")
- assert platform in ["alveo", "zynq-iodma"]
- bitfile = model.get_metadata_prop("bitfile")
- bitfile = os.path.basename(bitfile)
- if pynq_password == "":
- if "zynq" in platform:
- raise Exception("PYNQ board remote exec needs password for sudo")
- else:
- local_prefix = "" # assume we are using an ssh key
- warnings.warn("Empty password, make sure you've set up an ssh key")
- else:
- local_prefix = "sshpass -p %s " % pynq_password
-
- if platform == "alveo":
- # Alveo can run without sudo but needs correct environment
- remote_prefix = "conda activate finn-pynq-alveo; "
- elif "zynq" in platform:
- # PYNQ Zynq boards need to execute with sudo
- remote_prefix = "echo %s | sudo -S " % pynq_password
-
- # use platform attribute for correct remote execution
- if platform == "alveo":
- remote_cmd = "bash -ic 'bash alveo_run.sh throughput_test %d' \"" % batchsize
- else:
- remote_cmd = (
- "python3.6 driver.py --exec_mode=throughput_test --batchsize={} "
- "--bitfile={} --inputfile=input.npy --outputfile=output.npy "
- '--platform={} "'
- ).format(batchsize, bitfile, platform)
- cmd = (
- local_prefix + 'ssh {}@{} -p {} "cd {}/{}; ' + remote_prefix + remote_cmd
- ).format(pynq_username, pynq_ip, pynq_port, pynq_target_dir, deployment_folder)
- bash_command = ["/bin/bash", "-c", cmd]
- process_throughput_test = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
- process_throughput_test.communicate(timeout=timeout)
-
- # remove any pre-existing metrics file
- try:
- os.remove("{}/nw_metrics.txt".format(deployment_dir))
- except FileNotFoundError:
- pass
-
- cmd = local_prefix + "scp -P{} {}@{}:{}/{}/nw_metrics.txt {}".format(
- pynq_port,
- pynq_username,
- pynq_ip,
- pynq_target_dir,
- deployment_folder,
- deployment_dir,
- )
- bash_command = ["/bin/bash", "-c", cmd]
- process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
- process_compile.communicate(timeout=timeout)
-
- try:
- with open("{}/nw_metrics.txt".format(deployment_dir), "r") as file:
- res = eval(file.read())
- return res
- except FileNotFoundError:
- return None
-
-
def throughput_test_rtlsim(model, batchsize=100):
"""Runs a throughput test for the given IP-stitched model. When combined
with tracing, useful to determine bottlenecks and required FIFO sizes."""
diff --git a/src/finn/custom_op/fpgadataflow/addstreams_batch.py b/src/finn/custom_op/fpgadataflow/addstreams_batch.py
index cd0af6b3ab3d8250abbf7d48e004622e55f09f04..af106d9c0698d2d49bbd8f8998f57cad0b2e781e 100644
--- a/src/finn/custom_op/fpgadataflow/addstreams_batch.py
+++ b/src/finn/custom_op/fpgadataflow/addstreams_batch.py
@@ -38,8 +38,8 @@ from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
class AddStreams_Batch(HLSCustomOp):
"""Class that corresponds to finn-hlslib AddStreams_Batch function."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = super().get_nodeattr_types()
diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
index 46adca680d3c96695eeb5a91be53ea158fc78f1f..7791647abf1c5a51c0425ae835471ec9ceb7c21c 100644
--- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
+++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py
@@ -39,8 +39,6 @@ from finn.util.data_packing import (
rtlsim_output_to_npy,
)
-from . import templates
-
# ONNX i/o tensor shape assumptions for channelwise ops:
# input 0 is the input tensor, shape (..., NumChannels)
# input 1 is the channelwise parameter tensor, shape (NumChannels, params_per_channel)
@@ -85,9 +83,8 @@ class ChannelwiseOp_Batch(HLSCustomOp):
including Add, Mul and multi-thresholding.
"""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
- self.decoupled_wrapper = templates.decoupled_wrapper
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/checksum.py b/src/finn/custom_op/fpgadataflow/checksum.py
index c927c07df21faf40ccbf9ddbe47e3f2f2ca61c89..99646274fa1bc5b710b23ea42a25d0fed0da529c 100644
--- a/src/finn/custom_op/fpgadataflow/checksum.py
+++ b/src/finn/custom_op/fpgadataflow/checksum.py
@@ -38,8 +38,8 @@ from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
class CheckSum(HLSCustomOp):
"""Class that corresponds to custom_hls checksum function."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/concat.py b/src/finn/custom_op/fpgadataflow/concat.py
index 4437bcd1984c5194b0a19b43d692babb7e3cd158..8b655b570d0396e253a1c98231702f816072da20 100644
--- a/src/finn/custom_op/fpgadataflow/concat.py
+++ b/src/finn/custom_op/fpgadataflow/concat.py
@@ -39,8 +39,8 @@ class StreamingConcat(HLSCustomOp):
"""Streaming concatenation node with dynamically generated HLS.
Only supports concatenating along the last axis."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
index 1566445999a2c568b5c5a112d436bf05fd89aca5..6cc9208bb81ff68fe941c8d8d006c65b635eb437 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
@@ -54,8 +54,8 @@ class ConvolutionInputGenerator(HLSCustomOp):
attributes (e.g. depthwise or not, whether k % stride is 0) a different
variant will be picked for the actual HLS implementation."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
index f1c84662cc06e89df5bd7c0762ac47b8c5723502..6e792ca585718ff9690b0a2430fc09ba46e0a2ba 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py
@@ -59,8 +59,8 @@ class ConvolutionInputGenerator1D(HLSCustomOp):
attributes (e.g. depthwise or not, whether dilation is 0) a different
variant will be picked for the actual HLS implementation."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
index 1afd23d3a1709a8929a03c21a6eba0a5a8cd6ba6..c54c4ac1c90ed72331c61b0a28cf6040b8d66881 100755
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
@@ -29,6 +29,7 @@
import math
import numpy as np
import os
+import shutil
from qonnx.core.datatype import DataType
from qonnx.custom_op.general import im2col
from qonnx.custom_op.general.im2col import compute_conv_output_dim
@@ -60,8 +61,8 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
(sliding window) function variants. Generates an RTL ConvolutionInputGenerator
implementation based on (System-)Verilog templates, defined in finn-rtllib/swg."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
@@ -72,8 +73,8 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
"SIMD": ("i", True, 0),
# additional parallelization parameter - not yet implemented
"M": ("i", False, 1),
- # alternative implementation style - not yet implemented
- "parallel_window": ("i", False, 0, {0}),
+ # Enable parallel window output (requires full SIMD unfolding)
+ "parallel_window": ("i", False, 0, {0, 1}),
"Stride": ("ints", True, []), # [H, W] = [Y, X]
"Dilation": ("ints", True, []), # [H, W] = [Y, X]
# FINN DataTypes for inputs, weights, outputs
@@ -81,7 +82,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
"outputDataType": ("s", True, ""),
"depthwise": ("i", False, 0, {0, 1}),
# Enable reprogrammable implementation to change FM dimensions,
- # stride, or dilation during runtime
+ # stride, or dilation during runtime (requires parallel_window = 0)
"dynamic_mode": ("i", False, 0, {0, 1}),
# FPGA resource type for ConvolutionInputGenerator input buffer
# auto -- let Vivado decide
@@ -188,6 +189,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
return self.get_instream_width()
def get_number_input_values(self):
+ """Function to get the number of expected input values."""
folded_ishape = self.get_folded_input_shape()
num_input_elems = np.prod(folded_ishape[:-1])
return num_input_elems
@@ -198,6 +200,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
return num_output_elems
def get_1d_conv_attrs_normalized(self):
+ """Returns normalized spatial attributes, where H=1 for the 1D case."""
# normalize FM dimensions so that:
# [H, W] = [Y, X] = [1, D] or [D, 1] are always mapped to [1, D].
# The dummy ('1') dimension is the Y-dimension.
@@ -218,6 +221,8 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
return (ifm_ch, ifm_dim, ofm_dim, k, stride, dilation)
def get_buffer_depth(self):
+ """Returns total depth of the internal buffer, depending on
+ implementation style."""
ifm_ch = self.get_nodeattr("IFMChannels")
k = self.get_nodeattr("ConvKernelDim")
ifm_dim = self.get_nodeattr("IFMDim")
@@ -233,13 +238,13 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
mmv_out = 1
channel_factor = int(ifm_ch / simd)
+ # compute minimal buffer length (assuming it holds 1 complete window)
+ buffer_min_size = (
+ (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1
+ ) * channel_factor
+
impl_style = self.select_impl_style()
if impl_style == "default":
- # compute minimal buffer length (assuming it holds 1 complete window)
- buffer_min_size = (
- (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1
- ) * channel_factor
-
# add additional buffer space in case of stride > 1
# this minimizes cycle count as it allows an earlier pre-load of inputs
buffer_depth = (
@@ -255,73 +260,89 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
* channel_factor,
)
)
- else:
- buffer_depth = 0
- raise Exception("Requested impl. style not implemented")
+ elif impl_style == "parallel":
+ buffer_depth = buffer_min_size + 1
return buffer_depth
def get_exp_cycles(self):
- simd = self.get_nodeattr("SIMD")
- ifm_ch = self.get_nodeattr("IFMChannels")
- k = self.get_nodeattr("ConvKernelDim")
- ifm_dim = self.get_nodeattr("IFMDim")
- ofm_dim = self.get_nodeattr("OFMDim")
- stride = self.get_nodeattr("Stride")
- dilation = self.get_nodeattr("Dilation")
- depthwise = self.get_nodeattr("depthwise")
- ifm_dim_h, ifm_dim_w = ifm_dim
- ofm_dim_h, ofm_dim_w = ofm_dim
- k_h, k_w = k
- stride_h, stride_w = stride
- dilation_h, dilation_w = dilation
-
- channel_factor = int(ifm_ch / simd)
+ impl_style = self.select_impl_style()
- if ifm_dim_h == 1 or ifm_dim_w == 1:
- # 1D case
- (
- ifm_ch,
- [ifm_dim_h, ifm_dim_w],
- [ofm_dim_h, ofm_dim_w],
- [k_h, k_w],
- [stride_h, stride_w],
- [dilation_h, dilation_w],
- ) = self.get_1d_conv_attrs_normalized()
-
- if depthwise:
- exp_cycles = (
- +ofm_dim_w * k_w * channel_factor
- + channel_factor * (k_w - 1) * (stride_w - 1)
- - (k_w - 1)
- + 2
- )
+ if impl_style == "parallel":
+ exp_cycles = self.get_number_input_values() + 2
+ elif impl_style == "default":
+ simd = self.get_nodeattr("SIMD")
+ ifm_ch = self.get_nodeattr("IFMChannels")
+ k = self.get_nodeattr("ConvKernelDim")
+ ifm_dim = self.get_nodeattr("IFMDim")
+ ofm_dim = self.get_nodeattr("OFMDim")
+ stride = self.get_nodeattr("Stride")
+ dilation = self.get_nodeattr("Dilation")
+ depthwise = self.get_nodeattr("depthwise")
+ ifm_dim_h, ifm_dim_w = ifm_dim
+ ofm_dim_h, ofm_dim_w = ofm_dim
+ k_h, k_w = k
+ stride_h, stride_w = stride
+ dilation_h, dilation_w = dilation
+
+ channel_factor = int(ifm_ch / simd)
+ if ifm_dim_h == 1 or ifm_dim_w == 1:
+ # 1D case
+ (
+ ifm_ch,
+ [ifm_dim_h, ifm_dim_w],
+ [ofm_dim_h, ofm_dim_w],
+ [k_h, k_w],
+ [stride_h, stride_w],
+ [dilation_h, dilation_w],
+ ) = self.get_1d_conv_attrs_normalized()
+
+ if depthwise:
+ exp_cycles = (
+ +ofm_dim_w * k_w * channel_factor
+ + channel_factor * (k_w - 1) * (stride_w - 1)
+ - (k_w - 1)
+ + 2
+ )
+ else:
+ exp_cycles = ofm_dim_w * k_w * channel_factor + 2
else:
- exp_cycles = ofm_dim_w * k_w * channel_factor + 2
- else:
- # 2D case
- buffer_min_size = (
- (k_h - 1) * dilation_h * ifm_dim_w + (k_w - 1) * dilation_w + 1
- ) * channel_factor
- cycles_write_block = ofm_dim_w * k_w * k_h * channel_factor
- cycles_read_block = stride_w * ifm_dim_w * channel_factor
- max_cycles = max(cycles_write_block, cycles_read_block)
- if depthwise:
- max_cycles += ofm_dim_w * (stride_w - 1) * (channel_factor - 1)
- exp_cycles = buffer_min_size + ofm_dim_h * max_cycles # initial buffering
- if depthwise:
- exp_cycles += (stride_h - 1) * ifm_dim_w * channel_factor
+ # 2D case
+ buffer_min_size = (
+ (k_h - 1) * dilation_h * ifm_dim_w + (k_w - 1) * dilation_w + 1
+ ) * channel_factor
+ cycles_write_block = ofm_dim_w * k_w * k_h * channel_factor
+ cycles_read_block = stride_w * ifm_dim_w * channel_factor
+ max_cycles = max(cycles_write_block, cycles_read_block)
+ if depthwise:
+ max_cycles += ofm_dim_w * (stride_w - 1) * (channel_factor - 1)
+ exp_cycles = buffer_min_size + ofm_dim_h * max_cycles
+ if depthwise:
+ exp_cycles += (stride_h - 1) * ifm_dim_w * channel_factor
return int(exp_cycles)
def bram_estimation(self):
simd = self.get_nodeattr("SIMD")
ram_style = self.get_nodeattr("ram_style")
+ impl_style = self.select_impl_style()
+ [k_h, k_w] = self.get_nodeattr("ConvKernelDim")
+ [ifm_dim_h, ifm_dim_w] = self.get_nodeattr("IFMDim")
+ [dilation_h, dilation_w] = self.get_nodeattr("Dilation")
- # NOTE: Actual BRAM usage might be lower in some cases.
- # This does not account for the exact Vivado behavior yet.
- buffer_width = simd * self.get_input_datatype().bitwidth()
- buffer_depth = self.get_buffer_depth()
if ram_style == "block" or ram_style == "auto":
+ buffer_width = simd * self.get_input_datatype().bitwidth()
+ if impl_style == "default":
+ buffer_depth = self.get_buffer_depth()
+ buffer_count = 1
+ elif impl_style == "parallel":
+ if ifm_dim_h == 1 or ifm_dim_w == 1:
+ return 0 # 1D case (no line buffers needed)
+ kernel_width = (k_w - 1) * dilation_w + 1
+ buffer_depth = (ifm_dim_w - kernel_width) + ifm_dim_w * (dilation_h - 1)
+ buffer_count = k_h - 1
+
+ # NOTE: Actual BRAM usage might be lower in some cases
+ # due to imperfect modeling of Vivado behavior
if buffer_depth <= 512:
ram_width = 36
elif buffer_depth <= 1024:
@@ -356,7 +377,9 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
remainder_cascade_width = math.ceil(buffer_width / remainder_width)
cascade_savings = ram_cascade_width - remainder_cascade_width
- return int(ram_cascade_depth * ram_cascade_width - cascade_savings)
+ return int(
+ (ram_cascade_depth * ram_cascade_width - cascade_savings) * buffer_count
+ )
else:
return 0
@@ -374,15 +397,28 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
def uram_estimation(self):
simd = self.get_nodeattr("SIMD")
ram_style = self.get_nodeattr("ram_style")
- buffer_width = simd * self.get_input_datatype().bitwidth()
- buffer_depth = self.get_buffer_depth()
+ impl_style = self.select_impl_style()
+ [k_h, k_w] = self.get_nodeattr("ConvKernelDim")
+ [ifm_dim_h, ifm_dim_w] = self.get_nodeattr("IFMDim")
+ [dilation_h, dilation_w] = self.get_nodeattr("Dilation")
if ram_style == "ultra":
+ buffer_width = simd * self.get_input_datatype().bitwidth()
+ if impl_style == "default":
+ buffer_depth = self.get_buffer_depth()
+ buffer_count = 1
+ elif impl_style == "parallel":
+ if ifm_dim_h == 1 or ifm_dim_w == 1:
+ return 0 # 1D case (no line buffers needed)
+ kernel_width = (k_w - 1) * dilation_w + 1
+ buffer_depth = (ifm_dim_w - kernel_width) + ifm_dim_w * (dilation_h - 1)
+ buffer_count = k_h - 1
+
ram_depth = 4096
ram_width = 72
ram_cascade_depth = math.ceil(buffer_depth / ram_depth)
ram_cascade_width = math.ceil(buffer_width / ram_width)
- return int(ram_cascade_depth * ram_cascade_width)
+ return int(ram_cascade_depth * ram_cascade_width * buffer_count)
else:
return 0
@@ -457,8 +493,8 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
shape doesn't match expected shape (1, ofm_dim_h, ofm_dim_w, k_h*k_w*ifm_ch)."""
def prepare_codegen_default(self):
- # Default implementation style for MMV_out = 1: addressable cyclic buffer
- # Computing incremental addressing scheme directly..
+ """Fills code generation dict for the default implementation style by computing
+ the incremental addressing scheme for the circular buffer."""
if self.get_nodeattr("dynamic_mode"):
template_select = "/finn-rtllib/swg/swg_template_default_dynamic.sv"
else:
@@ -528,13 +564,13 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
)
addr_incr_end_simd = -buffer_min_size + (channel_factor + 1)
- # sanity check
+ # sanity check for wrap logic
assert not (
abs(addr_incr_end_window) > buffer_actual_size
- ), "ERROR: W increment > buffer size, wrap logic doesn't account for this"
+ ), "ERROR: W increment > buffer size, try setting parallel_window=1"
assert not (
abs(addr_incr_end_row) > buffer_actual_size
- ), "ERROR: H increment > buffer size, wrap logic doesn't account for this"
+ ), "ERROR: H increment > buffer size, try setting parallel_window=1"
# set certain threshold indices to detect when reading/writing finishes
code_gen_dict["$LAST_READ_ELEM$"] = [str(h * w * channel_factor - 1)]
@@ -639,7 +675,275 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
return template_path, code_gen_dict
+ def prepare_codegen_parallel(self):
+ """Fills code generation dict for the parallel implementation style by computing
+ the loop controller configuration and partitioning the fixed buffer into
+ shift-registers (for parallel read access) and line buffers (for efficient
+ LUTRAM/BRAM/URAM implementation)."""
+ template_path = (
+ os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_parallel.sv"
+ )
+ code_gen_dict = {}
+
+ ifm_ch = self.get_nodeattr("IFMChannels")
+ k = self.get_nodeattr("ConvKernelDim")
+ ifm_dim = self.get_nodeattr("IFMDim")
+ stride = self.get_nodeattr("Stride")
+ dilation = self.get_nodeattr("Dilation")
+ simd = self.get_nodeattr("SIMD")
+ M = self.get_nodeattr("M")
+
+ k_h, k_w = k
+ h, w = ifm_dim
+ pad = [0, 0, 0, 0] # padding happens in separate padding node for now
+ stride_h, stride_w = stride
+ dilation_h, dilation_w = dilation
+ pad_h = pad[0] + pad[2]
+ pad_w = pad[1] + pad[3]
+ out_dim_h = im2col.compute_conv_output_dim(h, k_h, stride_h, pad_h, dilation_h)
+ out_dim_w = im2col.compute_conv_output_dim(w, k_w, stride_w, pad_w, dilation_w)
+ mmv_in = M * 1
+ mmv_out = M * k_h * k_w
+ channel_factor = int(ifm_ch / simd)
+
+ # compute minimal buffer length (assuming it holds 1 complete window)
+ buffer_min_size = (
+ (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1
+ ) * channel_factor
+
+ buffer_actual_size = self.get_buffer_depth()
+ code_gen_dict["$BUF_ELEM_TOTAL$"] = [str(buffer_actual_size)]
+
+ # compute some intermediate values, e.g., kernel "width" = k_w incl. dilation
+ # or cols/rows that are skipped due to imperfect stride<->dim combination
+ kernel_width = (k_w - 1) * dilation_w + 1
+ kernel_height = (k_h - 1) * dilation_h + 1
+ skip_columns = w % (kernel_width + (out_dim_w - 1) * stride_w)
+ skip_rows = h % (kernel_height + (out_dim_h - 1) * stride_h)
+
+ # set certain threshold indices to detect when reading/writing finishes
+ code_gen_dict["$LAST_READ_ELEM$"] = [str(h * w * channel_factor - 1)]
+ code_gen_dict["$LAST_WRITE_ELEM$"] = [
+ str(((h - skip_rows - 1) * w + (w - skip_columns)) * channel_factor - 1)
+ ]
+
+ # re-use default controller loop structure
+ code_gen_dict["$IS_DEPTHWISE$"] = ["0"]
+ loop_h_iterations = out_dim_h
+ loop_w_iterations = out_dim_w # now the innermost loop
+ loop_kh_iterations = 1
+ loop_kw_iterations = 1
+ loop_simd_iterations = 1
+
+ if loop_w_iterations == 1:
+ code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_H"]
+ loop_h_iterations -= 1 # -1 because state is initial state
+ else:
+ code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_W"]
+ loop_w_iterations -= 1 # -1 because state is initial state
+
+ # set head and tail address increment values
+ addr_incr_end_window = -buffer_min_size + stride_w * channel_factor + 1
+ addr_incr_end_row = (
+ -buffer_min_size
+ + ((skip_columns + kernel_width) * channel_factor) # remaining line
+ + ((stride_h - 1) * w * channel_factor) # skip lines
+ + 1
+ )
+
+ tail_incr_w = addr_incr_end_window + buffer_min_size - 1
+ tail_incr_h = addr_incr_end_row + buffer_min_size - 1
+ tail_incr_last_window = stride_w
+
+ addr_incr_end_simd = 1
+ addr_incr_end_window_elem = 1
+ addr_incr_end_window_row = 1
+ addr_incr_end_window = tail_incr_w
+ addr_incr_end_row = tail_incr_h
+
+ # add init value for CURRENT_ELEM counter = last elem of first window
+ code_gen_dict["$FIRST_WRITE_ELEM$"] = [str(buffer_min_size - 1)]
+
+ cntr_bitwidth = math.ceil(
+ math.log2(
+ max(
+ loop_h_iterations - 2 + 1,
+ loop_w_iterations - 2 + 1,
+ loop_kh_iterations - 2 + 1,
+ loop_kw_iterations - 2 + 1,
+ loop_simd_iterations - 2 + 1,
+ )
+ )
+ )
+ code_gen_dict["$CNTR_BITWIDTH$"] = [str(cntr_bitwidth)]
+ code_gen_dict["$LOOP_H_ITERATIONS$"] = [str(loop_h_iterations - 2)]
+ code_gen_dict["$LOOP_W_ITERATIONS$"] = [str(loop_w_iterations - 2)]
+ code_gen_dict["$LOOP_KH_ITERATIONS$"] = [str(loop_kh_iterations - 2)]
+ code_gen_dict["$LOOP_KW_ITERATIONS$"] = [str(loop_kw_iterations - 2)]
+ code_gen_dict["$LOOP_SIMD_ITERATIONS$"] = [str(loop_simd_iterations - 2)]
+
+ incr_bitwidth = 1 + math.ceil(
+ math.log2(
+ max(
+ abs(addr_incr_end_simd) + 1,
+ abs(addr_incr_end_window_elem) + 1,
+ abs(addr_incr_end_window_row) + 1,
+ abs(addr_incr_end_window) + 1,
+ abs(addr_incr_end_row) + 1,
+ abs(tail_incr_w) + 1,
+ abs(tail_incr_h) + 1,
+ abs(tail_incr_last_window) + 1,
+ )
+ )
+ )
+ code_gen_dict["$INCR_BITWIDTH$"] = [str(incr_bitwidth)]
+ code_gen_dict["$HEAD_INCR_SIMD$"] = [str(addr_incr_end_simd)]
+ code_gen_dict["$HEAD_INCR_KW$"] = [str(addr_incr_end_window_elem)]
+ code_gen_dict["$HEAD_INCR_KH$"] = [str(addr_incr_end_window_row)]
+ code_gen_dict["$HEAD_INCR_W$"] = [str(addr_incr_end_window)]
+ code_gen_dict["$HEAD_INCR_H$"] = [str(addr_incr_end_row)]
+ code_gen_dict["$TAIL_INCR_W$"] = [str(tail_incr_w)]
+ code_gen_dict["$TAIL_INCR_H$"] = [str(tail_incr_h)]
+ code_gen_dict["$TAIL_INCR_LAST$"] = [str(tail_incr_last_window)]
+
+ code_gen_dict["$SIMD$"] = [str(simd)]
+ code_gen_dict["$MMV_IN$"] = [str(mmv_in)]
+ code_gen_dict["$MMV_OUT$"] = [str(mmv_out)]
+
+ # prepare buffer partitioning into "reg_fifos" and "bram_fifos"
+ # use normalized ([H,W]=[1,W]) dimensions for 1D case
+ (
+ ifm_ch,
+ [ifm_dim_h, ifm_dim_w],
+ [ofm_dim_h, ofm_dim_w],
+ [k_h, k_w],
+ [stride_h, stride_w],
+ [dilation_h, dilation_w],
+ ) = self.get_1d_conv_attrs_normalized()
+
+ reg_fifos = []
+ bram_fifos_depth = []
+
+ px_idx = 0
+ for ky in range(k_h):
+ reg_fifo = []
+ for kx in range(k_w):
+ reg_fifo.append(px_idx)
+ px_idx += 1
+ if kx < (k_w - 1):
+ reg_fifo.extend([-1] * (dilation_w - 1))
+ px_idx += dilation_w - 1
+ reg_fifos.append(reg_fifo)
+
+ if ky < (k_h - 1):
+ line_buffer_len = (w - kernel_width) + w * (dilation_h - 1)
+ bram_fifos_depth.append(line_buffer_len)
+ px_idx += line_buffer_len
+
+ code_gen_dict["$GENERATE_REG_FIFOS$"] = []
+ for i, reg_fifo in enumerate(reg_fifos):
+ code_gen_dict["$GENERATE_REG_FIFOS$"].append(
+ """
+ wire [IN_WIDTH-1:0] reg_fifo_{id}_in;
+ wire [IN_WIDTH-1:0] reg_fifo_{id}_out;
+ wire [IN_WIDTH*{len}-1:0] reg_fifo_{id};
+ swg_reg_buffer
+ #(
+ .WIDTH(IN_WIDTH),
+ .DEPTH({len})
+ )
+ reg_buffer_inst_{id}
+ (
+ .clk(clk),
+ .shift_enable(shift_enable),
+ .shift_in(reg_fifo_{id}_in),
+ .shift_out(reg_fifo_{id}_out),
+ .data_out(reg_fifo_{id})
+ );""".format(
+ id=i,
+ len=len(reg_fifo),
+ )
+ )
+
+ code_gen_dict["$GENERATE_BRAM_FIFOS$"] = []
+ for i, bram_fifo_depth in enumerate(bram_fifos_depth):
+ code_gen_dict["$GENERATE_BRAM_FIFOS$"].append(
+ """
+ wire [IN_WIDTH-1:0] bram_fifo_{id}_in;
+ wire [IN_WIDTH-1:0] bram_fifo_{id}_out;
+ swg_ram_buffer
+ #(
+ .WIDTH(IN_WIDTH),
+ .DEPTH({len}),
+ .RAM_STYLE("{ram_style}")
+ )
+ ram_buffer_inst_{id}
+ (
+ .clk(clk),
+ .rst_n(rst_n),
+ .shift_enable(shift_enable),
+ .shift_in(bram_fifo_{id}_in),
+ .shift_out(bram_fifo_{id}_out)
+ );""".format(
+ id=i,
+ len=bram_fifo_depth,
+ ram_style=self.get_nodeattr("ram_style"),
+ )
+ )
+
+ code_gen_dict["$GENERATE_OUTPUT_MAPPING$"] = []
+ out_idx = mmv_out - 1
+ for fifo_id, reg_fifo in enumerate(reg_fifos):
+ for fifo_idx, access_idx in enumerate(reg_fifo):
+ if access_idx != -1:
+ code_gen_dict["$GENERATE_OUTPUT_MAPPING$"].append(
+ """assign data_out[OUT_ELEM_WIDTH*{out_idx}+:OUT_ELEM_WIDTH]
+ = reg_fifo_{fifo_id}[{access_idx}*{mmv}*OUT_ELEM_WIDTH+
+ OUT_ELEM_WIDTH*{mmv_idx}+:OUT_ELEM_WIDTH];""".format(
+ out_idx=out_idx,
+ fifo_id=fifo_id,
+ access_idx=len(reg_fifo)
+ - 1
+ - int((max(reg_fifo) - access_idx) / M),
+ mmv_idx=(max(reg_fifo) - access_idx) % M,
+ mmv=M,
+ )
+ )
+ # reversal: out_idx=0 -> oldest buffer element -> highest access_idx
+ out_idx = out_idx - 1
+ assert out_idx == -1, "ERROR: Not all output vector elements connected"
+
+ code_gen_dict["$GENERATE_BUFFER_CONNECTION$"] = []
+ for i in range(len(reg_fifos)):
+ if i == 0:
+ # first FIFO containing newest elements -> input comes from input reg
+ code_gen_dict["$GENERATE_BUFFER_CONNECTION$"].append(
+ """assign reg_fifo_{fifo_id}_in = data_in;""".format(
+ fifo_id=i,
+ )
+ )
+ else:
+ # other REG FIFOs -> input comes from connected BRAM FIFO (line buffer)
+ input_fifo_id = i - 1
+ code_gen_dict["$GENERATE_BUFFER_CONNECTION$"].append(
+ """assign reg_fifo_{fifo_id}_in = bram_fifo_{input_fifo_id}_out;
+ """.format(
+ fifo_id=i, input_fifo_id=input_fifo_id
+ )
+ )
+ for i in range(len(bram_fifos_depth)):
+ input_fifo_id = i
+ code_gen_dict["$GENERATE_BUFFER_CONNECTION$"].append(
+ """assign bram_fifo_{fifo_id}_in = reg_fifo_{input_fifo_id}_out;
+ """.format(
+ fifo_id=i, input_fifo_id=input_fifo_id
+ )
+ )
+
+ return template_path, code_gen_dict
+
def select_impl_style(self):
+ """Selects implementation style based on folding configuration."""
simd = self.get_nodeattr("SIMD")
M = self.get_nodeattr("M")
ifm_ch = self.get_nodeattr("IFMChannels")
@@ -685,17 +989,20 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
else:
impl_style = "default"
- assert (
- impl_style == "default"
- ), "ERROR: Parallel window mode not yet implemented"
return impl_style
def generate_hdl(self):
+ """Generates HDL code and wrapper for the IP, depending on required
+ implementation style."""
impl_style = self.select_impl_style()
# prepare code generation by filling out dictionaries
if impl_style == "default":
template_path, code_gen_dict = self.prepare_codegen_default()
+ elif impl_style == "parallel":
+ template_path, code_gen_dict = self.prepare_codegen_parallel()
+ if self.get_nodeattr("dynamic_mode"):
+ raise Exception("Dynamic mode is not compatible with parallel_window")
else:
raise Exception("Requested impl. style not implemented")
@@ -706,10 +1013,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name())
code_gen_dict["$BIT_WIDTH$"] = [str(self.get_input_datatype().bitwidth())]
ram_style = self.get_nodeattr("ram_style")
- if ram_style == "auto":
- code_gen_dict["$RAM_STYLE$"] = [""]
- else:
- code_gen_dict["$RAM_STYLE$"] = ['(* ram_style = "{}" *)'.format(ram_style)]
+ code_gen_dict["$RAM_STYLE$"] = ['"{}"'.format(ram_style)]
# apply code generation to templates
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
@@ -756,6 +1060,14 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
) as f:
f.write(template_axilite)
+ # Copy static source file for common core components
+ shutil.copy2(
+ os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir
+ )
+ shutil.copy2(
+ os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv", code_gen_dir
+ )
+
# set ipgen_path and ip_path so that HLS-Synth transformation
# and stich_ip transformation do not complain
self.set_nodeattr("ipgen_path", code_gen_dir)
@@ -773,8 +1085,10 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
verilog_paths = [code_gen_dir]
verilog_files = [
+ "swg_pkg.sv",
self.get_nodeattr("gen_top_module") + "_wrapper.v",
self.get_nodeattr("gen_top_module") + "_impl.sv",
+ "swg_common.sv",
]
if self.get_nodeattr("dynamic_mode"):
verilog_files.append(self.get_nodeattr("gen_top_module") + "_axilite.v")
@@ -796,8 +1110,10 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
sourcefiles = [
+ "swg_pkg.sv",
self.get_nodeattr("gen_top_module") + "_wrapper.v",
self.get_nodeattr("gen_top_module") + "_impl.sv",
+ "swg_common.sv",
]
if self.get_nodeattr("dynamic_mode"):
@@ -835,6 +1151,8 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
apply (e.g. component must be synthesized for largest buffer size)."""
# NOTE: For better driver integration, this functionality could be packaged
# as a standalone function in the future
+ if self.select_impl_style() != "default":
+ raise Exception("Impl. style is incompatible with dynamic mode")
if ifm_dim is None:
ifm_dim = self.get_nodeattr("IFMDim")
@@ -887,44 +1205,53 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
return config
def code_generation_ipgen(self, model, fpgapart, clk):
- """Normally: Generates C++ code and tcl script for IP generation.
- Here: Generates (System-)Verilog code for IP generation."""
+ """Generates (System-)Verilog code for IP generation (instead of HLS code)."""
self.generate_hdl()
def ipgen_singlenode_code(self):
- """Normally: Builds the bash script for IP generation."""
+ """Not implemented (RTL component)."""
pass
def code_generation_cppsim(self, model):
- """Normally: Generates C++ code for simulation (cppsim)."""
+ """Not implemented (RTL component)."""
pass
def compile_singlenode_code(self):
+ """Not implemented (RTL component)."""
pass
def global_includes(self):
+ """Not implemented (RTL component)."""
pass
def defines(self, var):
+ """Not implemented (RTL component)."""
pass
def read_npy_data(self):
+ """Not implemented (RTL component)."""
pass
def strm_decl(self):
+ """Not implemented (RTL component)."""
pass
def docompute(self):
+ """Not implemented (RTL component)."""
pass
def dataoutstrm(self):
+ """Not implemented (RTL component)."""
pass
def save_as_npy(self):
+ """Not implemented (RTL component)."""
pass
def blackboxfunction(self):
+ """Not implemented (RTL component)."""
pass
def pragmas(self):
+ """Not implemented (RTL component)."""
pass
diff --git a/src/finn/custom_op/fpgadataflow/downsampler.py b/src/finn/custom_op/fpgadataflow/downsampler.py
index b7efaff440dd5cc2160fbfb8050b30924460ffe6..255606ee7f1998586c2b357904bd32b9a5590c96 100644
--- a/src/finn/custom_op/fpgadataflow/downsampler.py
+++ b/src/finn/custom_op/fpgadataflow/downsampler.py
@@ -39,8 +39,8 @@ class DownSampler(HLSCustomOp):
"""Corresponds to finn-hlslib ConvolutionInputGenerator_*_kernel1 function.
Basically performs a down sampling of the image removing rows and columns."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
index 93cde15ca7d42dbed12417837916359fdcc71b67..312f5e7e4a799d75aa0b9b7cd82b83c1b0e51dd9 100644
--- a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
+++ b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py
@@ -38,8 +38,8 @@ from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
class DuplicateStreams_Batch(HLSCustomOp):
"""Class that corresponds to finn-hlslib function of the same name."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/eltwise.py b/src/finn/custom_op/fpgadataflow/eltwise.py
index 68ed6546c741277bd8e962b6e80eda083cedba9c..c96f12f06bb1104152cecc6f5c6cdf5c0cc215f1 100644
--- a/src/finn/custom_op/fpgadataflow/eltwise.py
+++ b/src/finn/custom_op/fpgadataflow/eltwise.py
@@ -38,8 +38,8 @@ from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
class StreamingEltwise(HLSCustomOp):
"""Class that corresponds to finn-hlslib StreamingEltwise function."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
index dfc55d283fa664e3b60fc7c4d5a056f53a119292..bdb5775c3eea84b09297025501f0116438b09ae7 100644
--- a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
+++ b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py
@@ -39,8 +39,8 @@ class FMPadding_Batch(HLSCustomOp):
"""Corresponds to finn-hlslib FMPadding_Batch function.
Pads input image by given amount."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py
index 5650d218857a7c7ff86c15ac057c4ebbc18df5ca..9c2750322433627678d098c399b7a932eeac398d 100644
--- a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py
+++ b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py
@@ -49,8 +49,8 @@ class FMPadding_rtl(HLSCustomOp):
Supports adjusting the padding amount and spatial feature sizes at
runtime."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
index e7fa5bc0048b54a32ebc61482b96009fa019809e..220856922c1ed805ccfa60213dc0cf32f45573a1 100644
--- a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py
@@ -38,8 +38,8 @@ from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
class GlobalAccPool_Batch(HLSCustomOp):
"""Class that corresponds to finn-hlslib AccPool_Batch function."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/hlscustomop.py b/src/finn/custom_op/fpgadataflow/hlscustomop.py
index d1326607aa0dc5c34eef105b2ceb8ed86c1a0458..d5d0c9ea6e77395d95b2f1a3b2b6ff0412d2a553 100644
--- a/src/finn/custom_op/fpgadataflow/hlscustomop.py
+++ b/src/finn/custom_op/fpgadataflow/hlscustomop.py
@@ -59,8 +59,8 @@ class HLSCustomOp(CustomOp):
custom node should have. Some as abstract methods, these have to be filled
when writing a new fpgadataflow custom op node."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
self.code_gen_dict = {}
diff --git a/src/finn/custom_op/fpgadataflow/iodma.py b/src/finn/custom_op/fpgadataflow/iodma.py
index 65683079fc6a648de31148e398ea498f38b8d3d9..8a756b630ddbd25d5740f0e46297a4ae6f686d2b 100644
--- a/src/finn/custom_op/fpgadataflow/iodma.py
+++ b/src/finn/custom_op/fpgadataflow/iodma.py
@@ -75,8 +75,8 @@ from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp
class IODMA(HLSCustomOp):
"""Class that corresponds to finn-hlslib DMA function(s)."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/labelselect_batch.py b/src/finn/custom_op/fpgadataflow/labelselect_batch.py
index 03f89bd7ecac69a9097f4f35c42bd528be709515..492cd0107321f3abbfe02d5e456ee3732da982d0 100644
--- a/src/finn/custom_op/fpgadataflow/labelselect_batch.py
+++ b/src/finn/custom_op/fpgadataflow/labelselect_batch.py
@@ -39,8 +39,8 @@ from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
class LabelSelect_Batch(HLSCustomOp):
"""Class that corresponds to finn-hlslib LabelSelect_Batch function."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
odt_name = self.get_nodeattr("outputDataType")
if odt_name == "":
# If not provided compute min size
diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py
index fd3e2b5b1cfa74eb4f957df4b568e6c46da47617..ed560ac962477965bae39d296287c09eb077eca0 100644
--- a/src/finn/custom_op/fpgadataflow/lookup.py
+++ b/src/finn/custom_op/fpgadataflow/lookup.py
@@ -44,8 +44,8 @@ from finn.util.data_packing import (
class Lookup(HLSCustomOp):
"Streaming elementwise HLS lookup, mapping indices to values."
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
index 72128fda4cfe23db4858fe3ffe80a755733954cc..899bce98d2dd9572d1adf2f20910a0463f9d5994 100644
--- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
+++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py
@@ -46,8 +46,6 @@ from finn.util.data_packing import (
rtlsim_output_to_npy,
)
-from . import templates
-
# ONNX i/o tensor shape assumptions for MatrixVectorActivation:
# input 0 is the input tensor, shape (.., i_size) = (..., MW)
# input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH)
@@ -60,9 +58,8 @@ class MatrixVectorActivation(HLSCustomOp):
"""Class that corresponds to finn-hls Matrix_Vector_Activate(_Stream)_Batch
function."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
- self.decoupled_wrapper = templates.decoupled_wrapper
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
@@ -350,13 +347,23 @@ class MatrixVectorActivation(HLSCustomOp):
# adder tree
addertree_luts = (W + A) * (2 * Q - 1)
# accumulator
- acc_bits = W + A + np.ceil(math.log(MW, 2))
+ acc_datatype = self.get_accumulator_datatype()
+ # if accDataType is not set, then it will default to INT32, which would
+ # be a large overestimate in most (if not all) cases. In this scenario,
+ # we would use the minimum accumulator as determined by the data types
+ # bound, derived in https://arxiv.org/abs/2301.13376
+ alpha = math.log(MW, 2) + W + A - 1 - int(idt.signed())
+ acc_bits = min(
+ acc_datatype.bitwidth(),
+ np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1),
+ )
acc_luts = acc_bits
# thresholds and threshold comparators
thr_luts = 0
comp_luts = 0
noact = self.get_nodeattr("noActivation")
- if noact == 0:
+ tmem_style = self.get_nodeattr("ram_style_thresholds")
+ if (noact == 0) and (tmem_style == "distributed"):
odt = self.get_output_datatype()
B = odt.bitwidth()
thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64)
@@ -405,6 +412,10 @@ class MatrixVectorActivation(HLSCustomOp):
else:
raise Exception("Undefined input ind for this layer type")
+ def get_accumulator_datatype(self):
+ """Returns FINN DataType of accumulator"""
+ return DataType[self.get_nodeattr("accDataType")]
+
def get_weight_datatype(self):
"""Returns FINN DataType of weights."""
return DataType[self.get_nodeattr("weightDataType")]
@@ -575,6 +586,8 @@ class MatrixVectorActivation(HLSCustomOp):
return ret
def minimize_accumulator_width(self, model):
+ """Minimize the accumulator bit width according to the weight values,
+ input data types, and size of dot product"""
weights = model.get_initializer(self.onnx_node.input[1])
# since in the calculation the values of the weight matrix are used,
# for the bipolar case they need to be converted to bipolar
@@ -585,8 +598,23 @@ class MatrixVectorActivation(HLSCustomOp):
else:
thresholds = None
idt = self.get_input_datatype()
- # calculate minimum and maximum values of accumulator
- (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt)
+ # if runtime-writeable weights, then the values of the weights can
+ # change and we need to use the worst-case values from the datatypes
+ if self.get_nodeattr("runtime_writeable_weights"):
+ wdt = self.get_weight_datatype()
+ lower_worst = wdt.min() * np.ones_like(weights)
+ lower_range = calculate_matvec_accumulator_range(lower_worst, idt)
+ upper_worst = wdt.max() * np.ones_like(weights)
+ upper_range = calculate_matvec_accumulator_range(upper_worst, idt)
+ acc_min = min(min(lower_range), min(upper_range))
+ acc_max = max(max(upper_range), max(upper_range))
+ # if not runtime-writeable weights, then we can calculate the min
+ # and max values of the accumulation range using knowledge of the
+ # weights and input data types since they are fixed
+ else:
+ (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt)
+ # if the thresholds can be used to determine range, then adjust the range
+ # according to the known values of the thresholds
if thresholds is not None:
threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)
# set threshold datatype (and accumulator datatype implicitly)
@@ -622,7 +650,7 @@ class MatrixVectorActivation(HLSCustomOp):
self.onnx_node.name,
str(tdt),
)
- self.set_nodeattr("accDataType", tdt.name)
+ adt = tdt # Set activation datatype to the threshold datatype
else:
if acc_min < 0:
if abs(acc_min) > acc_max:
@@ -631,15 +659,33 @@ class MatrixVectorActivation(HLSCustomOp):
adt = DataType.get_smallest_possible(-acc_max - 1)
else:
adt = DataType.get_smallest_possible(acc_max)
- # ensure a datatype divisible by 8-bits in case this is the last node
+ # if this is the last node in the graph, then ensure the datatype is
+ # divisibly by 8 bits
+ if model.find_direct_successors(self.onnx_node) is None:
bw = roundup_to_integer_multiple(adt.bitwidth(), 8)
new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw))
adt = DataType[new_adt_name]
- self.set_nodeattr("accDataType", adt.name)
# for no-activation nodes, output dt = acc dt
self.set_nodeattr("outputDataType", adt.name)
+ self.set_nodeattr("accDataType", adt.name)
return DataType[self.get_nodeattr("accDataType")]
+ def minimize_weight_bit_width(self, model):
+ """Minimize the bit width based on the values of the weights"""
+ if not self.get_nodeattr("runtime_writeable_weights"):
+ weights = model.get_initializer(self.onnx_node.input[1])
+ w_min = weights.min()
+ w_max = weights.max()
+ if w_min < 0:
+ if abs(w_min) > w_max:
+ wdt = DataType.get_smallest_possible(w_min)
+ else:
+ wdt = DataType.get_smallest_possible(-w_max - 1)
+ else:
+ wdt = DataType.get_smallest_possible(w_max)
+ self.set_nodeattr("weightDataType", wdt.name)
+ return DataType[self.get_nodeattr("weightDataType")]
+
def get_hls_compatible_threshold_tensor(self, orig_thres_matrix):
"""Convert the original numpy weight matrix orig_weight_matrix into
a form suitable for passing to the hlslib call:
@@ -671,13 +717,6 @@ class MatrixVectorActivation(HLSCustomOp):
# ensure all thresholds are integer
assert (orig_thres_matrix.astype(np.int32) == orig_thres_matrix).all()
ret = orig_thres_matrix
- # workaround for vivado_hls threshold bug
- if ret[0][0] == 0 and n_thres_steps == 1:
- ret = np.copy(ret)
- ret[0][0] = 1
- warnings.warn(
- "Setting 0-valued first threshold to 1 to avoid vivado_hls bug"
- )
# ensure channels = mh , duplicating if necessary
if ret.shape[0] == 1:
ret = np.tile(ret, (mh, 1))
@@ -825,28 +864,10 @@ class MatrixVectorActivation(HLSCustomOp):
self.make_weight_file(weights, "decoupled_npy", weight_filename_sim)
if mem_mode == "decoupled":
# also save weights as Verilog .dat file
- # note that we provide two different .dat files, one for synth
- # and one for synthesis. this is because URAM-based weights always
- # need zero weights for synthesis, otherwise they get inferred
- # as BRAM
- weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(
- code_gen_dir
- )
- weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir)
- # sim weights are always the true weights
- self.make_weight_file(
- weights, "decoupled_verilog_dat", weight_filename_rtl_sim
- )
- ram_style = self.get_nodeattr("ram_style")
- if ram_style == "ultra":
- # UltraRAM must have no memory initializer, or only zeroes
- # otherwise BRAM will be inferred instead of URAM
- # as a workaround we provide a zero-weight init here
- synth_weights = np.zeros_like(weights, dtype=np.float32)
- else:
- synth_weights = weights
+ # This file will be ignored when synthesizing UltraScale memory.
+ weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir)
self.make_weight_file(
- synth_weights, "decoupled_verilog_dat", weight_filename_rtl_synth
+ weights, "decoupled_verilog_dat", weight_filename_rtl
)
else:
raise Exception(
@@ -1337,7 +1358,7 @@ class MatrixVectorActivation(HLSCustomOp):
% (self.get_nodeattr("ip_vlnv"), node_name, node_name)
)
# instantiate a streamer and connect it to the HLS IP
- strm_vlnv = "xilinx.com:user:memstream:1.0"
+ strm_vlnv = "amd.com:finn:memstream:1.0"
strm_inst = node_name + "_wstrm"
cmd.append(
"create_bd_cell -type ip -vlnv %s /%s/%s"
@@ -1345,22 +1366,16 @@ class MatrixVectorActivation(HLSCustomOp):
)
cmd.append(
"set_property -dict [list "
- "CONFIG.NSTREAMS {1} "
- "CONFIG.MEM_DEPTH {%d} "
- "CONFIG.MEM_WIDTH {%d} "
- "CONFIG.MEM_INIT {%s} "
+ "CONFIG.DEPTH {%d} "
+ "CONFIG.WIDTH {%d} "
+ "CONFIG.INIT_FILE {%s} "
"CONFIG.RAM_STYLE {%s} "
- "CONFIG.STRM0_DEPTH {%d} "
- "CONFIG.STRM0_WIDTH {%d} "
- "CONFIG.STRM0_OFFSET {0} "
"] [get_bd_cells /%s/%s]"
% (
self.calc_wmem(),
self.get_weightstream_width_padded(),
- self.get_nodeattr("code_gen_dir_ipgen") + "/",
+ self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat",
self.get_nodeattr("ram_style"),
- self.calc_wmem(),
- self.get_weightstream_width_padded(),
node_name,
strm_inst,
)
@@ -1371,11 +1386,11 @@ class MatrixVectorActivation(HLSCustomOp):
% (node_name, strm_inst, node_name, node_name, sname)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]"
% (node_name, rst_name, node_name, strm_inst)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]"
% (node_name, clk_name, node_name, strm_inst)
)
cmd.append(
diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py
index 522305327ff7c5f1356aad4fdf6b9e0a942eca72..34b1940fa1aa8e6c94d1a24cb069eb3d1a432274 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfifo.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py
@@ -41,8 +41,8 @@ from . import templates
class StreamingFIFO(HLSCustomOp):
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
self.strm_fifo_wrapper = templates.strm_fifo_wrapper
def get_nodeattr_types(self):
diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py
index c7bbc3f139b64f57943b2b099083a9611951e9c4..4e03e6daf9aee9aee2318ac1bc840b6387a40ccd 100644
--- a/src/finn/custom_op/fpgadataflow/templates.py
+++ b/src/finn/custom_op/fpgadataflow/templates.py
@@ -109,107 +109,6 @@ export_design -format ip_catalog
exit 0
"""
-# verilog wrapper for decoupled mem mode
-decoupled_wrapper = """
-module $TOPNAME$(
-ap_clk,
-ap_rst_n,
-in0_$HLS_SNAME$_TDATA,
-in0_$HLS_SNAME$_TVALID,
-in0_$HLS_SNAME$_TREADY,
-out_$HLS_SNAME$_TDATA,
-out_$HLS_SNAME$_TVALID,
-out_$HLS_SNAME$_TREADY
-);
-
-input ap_clk;
-input ap_rst_n;
-input $IN_RANGE$ in0_$HLS_SNAME$_TDATA;
-input in0_$HLS_SNAME$_TVALID;
-output in0_$HLS_SNAME$_TREADY;
-output $OUT_RANGE$ out_$HLS_SNAME$_TDATA;
-output out_$HLS_SNAME$_TVALID;
-input out_$HLS_SNAME$_TREADY;
-
-reg [31:0] config_address = 0;
-reg config_ce = 0;
-reg config_we = 0;
-reg [31:0] config_d0 = 0;
-wire [31:0] config_q0;
-
-//multiple wire AXI Streams
-wire m_axis_0_afull;
-// FIFO count to generate programmable full
-wire [5:0] fifo_0_count;
-wire m_axis_0_tready;
-wire m_axis_0_tvalid;
-wire $WEIGHT_RANGE$ m_axis_0_tdata;
-
-//memstream component
-
-memstream
-#(
-//parameters to enable/disable axi-mm, set number of streams, set readmemh for
-// memory, set per-stream offsets in memory, set per-stream widths
-.CONFIG_EN(1),
-.NSTREAMS(1),
-.MEM_DEPTH($MEM_DEPTH$),
-.MEM_WIDTH($WEIGHT_WIDTH$),
-.MEM_INIT("./"),
-.RAM_STYLE("$RAM_STYLE$"),
-
-//widths per stream
-.STRM0_WIDTH($WEIGHT_WIDTH$),
-
-//depths per stream
-.STRM0_DEPTH($WSTREAM_DEPTH$),
-
-//offsets for each stream
-.STRM0_OFFSET(0)
-)
-mem
-(
-.aclk(ap_clk),
-.aresetn(ap_rst_n),
-
-//optional configuration interface compatible with ap_memory
-.config_address(config_address),
-.config_ce(config_ce),
-.config_we(config_we),
-.config_d0(config_d0),
-.config_q0(config_q0),
-
-//multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
-.m_axis_0_afull(m_axis_0_afull),
-.m_axis_0_tready(m_axis_0_tready),
-.m_axis_0_tvalid(m_axis_0_tvalid),
-.m_axis_0_tdata(m_axis_0_tdata)
-
-
-);
-
-
-//MVA_Stream_Unit
-
-$LAYER_NAME$
-MVA_Stream_U
-(
-.ap_clk(ap_clk), //input
-.ap_rst_n(ap_rst_n), //input
-.in0_$HLS_SNAME$_TDATA(in0_$HLS_SNAME$_TDATA), //$IN_RANGE$ input
-.in0_$HLS_SNAME$_TVALID(in0_$HLS_SNAME$_TVALID), //input
-.in0_$HLS_SNAME$_TREADY(in0_$HLS_SNAME$_TREADY), //output
-.weights_$HLS_SNAME$_TDATA(m_axis_0_tdata), //$WEIGHT_RANGE$ input
-.weights_$HLS_SNAME$_TVALID(m_axis_0_tvalid), //input
-.weights_$HLS_SNAME$_TREADY(m_axis_0_tready), //output
-.out_$HLS_SNAME$_TDATA(out_$HLS_SNAME$_TDATA), //$OUT_RANGE$ output
-.out_$HLS_SNAME$_TVALID(out_$HLS_SNAME$_TVALID), //output
-.out_$HLS_SNAME$_TREADY(out_$HLS_SNAME$_TREADY) //input
-);
-
-endmodule
-"""
-
ip_package_tcl = """
## IP Info
set Vendor "xilinx.com"
diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py
index d9745acf63c4685b3369ac379abde0a6c5a3f157..12e635b3d612235f6b464e6f54d0f24011c7c907 100644
--- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py
+++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py
@@ -45,8 +45,6 @@ from finn.util.data_packing import (
rtlsim_output_to_npy,
)
-from . import templates
-
# ONNX i/o tensor shape assumptions for Thresholding:
# input 0 is the input tensor, shape (..., NumChannels)
# input 1 is the threshold tensor, shape (NumChannels, n_thres)
@@ -57,9 +55,8 @@ from . import templates
class Thresholding_Batch(HLSCustomOp):
"""Class that corresponds to finn-hls Thresholding_Batch function."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
- self.decoupled_wrapper = templates.decoupled_wrapper
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
@@ -319,13 +316,6 @@ class Thresholding_Batch(HLSCustomOp):
np.mod(orig_thres_matrix, 1), 0
).all(), "Need int threshold tensor"
ret = orig_thres_matrix
- # workaround for vivado_hls threshold bug
- if ret[0][0] == 0 and n_thres_steps == 1:
- ret = np.copy(ret)
- ret[0][0] = 1
- warnings.warn(
- "Setting 0-valued first threshold to 1 to avoid vivado_hls bug"
- )
# ensure channels = mh , duplicating if necessary
if ret.shape[0] == 1:
ret = np.tile(ret, (mh, 1))
@@ -464,26 +454,10 @@ class Thresholding_Batch(HLSCustomOp):
weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir)
self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim)
# also save weights as Verilog .dat file
- # note that we provide two different .dat files, one for synth
- # and one for synthesis. this is because URAM-based weights always
- # need zero weights for synthesis, otherwise they get inferred
- # as BRAM
- weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(code_gen_dir)
- weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir)
- # sim weights are always the true weights
- self.make_weight_file(
- thresholds, "decoupled_verilog_dat", weight_filename_rtl_sim
- )
- ram_style = self.get_nodeattr("ram_style")
- if ram_style == "ultra":
- # UltraRAM must have no memory initializer, or only zeroes
- # otherwise BRAM will be inferred instead of URAM
- # as a workaround we provide a zero-weight init here
- synth_thresholds = np.zeros_like(thresholds, dtype=np.float32)
- else:
- synth_thresholds = thresholds
+ # This file will be ignored when synthesizing UltraScale memory.
+ weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir)
self.make_weight_file(
- synth_thresholds, "decoupled_verilog_dat", weight_filename_rtl_synth
+ thresholds, "decoupled_verilog_dat", weight_filename_rtl
)
else:
raise Exception("Unrecognized mem_mode")
@@ -850,7 +824,7 @@ class Thresholding_Batch(HLSCustomOp):
% (self.get_nodeattr("ip_vlnv"), node_name, node_name)
)
# instantiate a streamer and connect it to the HLS IP
- strm_vlnv = "xilinx.com:user:memstream:1.0"
+ strm_vlnv = "amd.com:finn:memstream:1.0"
strm_inst = node_name + "_wstrm"
cmd.append(
"create_bd_cell -type ip -vlnv %s /%s/%s"
@@ -858,22 +832,16 @@ class Thresholding_Batch(HLSCustomOp):
)
cmd.append(
"set_property -dict [list "
- "CONFIG.NSTREAMS {1} "
- "CONFIG.MEM_DEPTH {%d} "
- "CONFIG.MEM_WIDTH {%d} "
- "CONFIG.MEM_INIT {%s} "
+ "CONFIG.DEPTH {%d} "
+ "CONFIG.WIDTH {%d} "
+ "CONFIG.INIT_FILE {%s} "
"CONFIG.RAM_STYLE {%s} "
- "CONFIG.STRM0_DEPTH {%d} "
- "CONFIG.STRM0_WIDTH {%d} "
- "CONFIG.STRM0_OFFSET {0} "
"] [get_bd_cells /%s/%s]"
% (
self.calc_tmem(),
self.get_weightstream_width_padded(),
- self.get_nodeattr("code_gen_dir_ipgen") + "/",
+ self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat",
self.get_nodeattr("ram_style"),
- self.calc_tmem(),
- self.get_weightstream_width_padded(),
node_name,
strm_inst,
)
@@ -884,11 +852,11 @@ class Thresholding_Batch(HLSCustomOp):
% (node_name, strm_inst, node_name, node_name, sname)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]"
% (node_name, rst_name, node_name, strm_inst)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]"
% (node_name, clk_name, node_name, strm_inst)
)
cmd.append(
diff --git a/src/finn/custom_op/fpgadataflow/tlastmarker.py b/src/finn/custom_op/fpgadataflow/tlastmarker.py
index 1bd32442a1986d6a86571e85a09322d6c15d8a78..895a2eedab51cee6322c7307ea1944d49a0dade5 100644
--- a/src/finn/custom_op/fpgadataflow/tlastmarker.py
+++ b/src/finn/custom_op/fpgadataflow/tlastmarker.py
@@ -37,8 +37,8 @@ class TLastMarker(HLSCustomOp):
(needed by the FINN PYNQ shell) or at the beginning to remove the end-of-burst
from DMA read."""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/upsampler.py b/src/finn/custom_op/fpgadataflow/upsampler.py
index a018fd35aac4d63b365e97464dab0fd4a5fa13f2..b653b9386e940dd2220fa1fb0d198e63b81a356d 100644
--- a/src/finn/custom_op/fpgadataflow/upsampler.py
+++ b/src/finn/custom_op/fpgadataflow/upsampler.py
@@ -41,8 +41,8 @@ class UpsampleNearestNeighbour_Batch(HLSCustomOp):
The layer expects square feature maps for the in and output.
"""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
index d5e29ca22acf89440c3c3a66101bec89d4a66d46..ede572f1a4c5fcf60476aa84beba8244eb9ec5a8 100644
--- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
+++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py
@@ -50,12 +50,13 @@ from finn.util.data_packing import (
class VectorVectorActivation(HLSCustomOp):
"""Class that corresponds to finn-hlslib Vector_Vector_Activate_Batch function"""
- def __init__(self, onnx_node):
- super().__init__(onnx_node)
+ def __init__(self, onnx_node, **kwargs):
+ super().__init__(onnx_node, **kwargs)
def get_nodeattr_types(self):
my_attrs = {
"PE": ("i", True, 0),
+ "SIMD": ("i", False, 1),
"Dim": ("ints", True, []), # [H, W]
"Channels": ("i", True, 0),
"Kernel": ("ints", True, []), # [H, W]
@@ -104,18 +105,39 @@ class VectorVectorActivation(HLSCustomOp):
return my_attrs
def minimize_accumulator_width(self, model):
+ """Minimize the accumulator bit width according to the weight values,
+ input data types, and size of dot product"""
weights = model.get_initializer(self.onnx_node.input[1])
k_h, k_w = self.get_nodeattr("Kernel")
fm = self.get_nodeattr("Channels")
# put weights into the shape expected by calculate_matvec_accumulator_range
weights = weights.reshape(fm, k_h * k_w).transpose()
+ # since in the calculation the values of the weight matrix are used,
+ # for the bipolar case they need to be converted to bipolar
+ if self.get_nodeattr("binaryXnorMode"):
+ weights = 2 * weights - 1
if len(self.onnx_node.input) > 2:
thresholds = model.get_initializer(self.onnx_node.input[2])
else:
thresholds = None
idt = self.get_input_datatype()
- # calculate minimum and maximum values of accumulator
- (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt)
+ # if runtime-writeable weights, then the values of the weights can
+ # change and we need to use the worst-case values from the datatypes
+ if self.get_nodeattr("runtime_writeable_weights"):
+ wdt = self.get_weight_datatype()
+ lower_worst = wdt.min() * np.ones_like(weights)
+ lower_range = calculate_matvec_accumulator_range(lower_worst, idt)
+ upper_worst = wdt.max() * np.ones_like(weights)
+ upper_range = calculate_matvec_accumulator_range(upper_worst, idt)
+ acc_min = min(min(lower_range), min(upper_range))
+ acc_max = max(max(upper_range), max(upper_range))
+ # if not runtime-writeable weights, then we can calculate the min
+ # and max values of the accumulation range using knowledge of the
+ # weights and input data types since they are fixed
+ else:
+ (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt)
+ # if the thresholds can be used to determine range, then adjust the range
+ # according to the known values of the thresholds
if thresholds is not None:
threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)
# set threshold datatype (and accumulator datatype implicitly)
@@ -151,7 +173,7 @@ class VectorVectorActivation(HLSCustomOp):
self.onnx_node.name,
str(tdt),
)
- self.set_nodeattr("accDataType", tdt.name)
+ adt = tdt # Set activation datatype to the threshold datatype
else:
if acc_min < 0:
if abs(acc_min) > acc_max:
@@ -160,21 +182,40 @@ class VectorVectorActivation(HLSCustomOp):
adt = DataType.get_smallest_possible(-acc_max - 1)
else:
adt = DataType.get_smallest_possible(acc_max)
- # ensure a datatype divisible by 8-bits in case this is the last node
+ # if this is the last node in the graph, then ensure the datatype is
+ # divisibly by 8 bits
+ if model.find_direct_successors(self.onnx_node) is None:
bw = roundup_to_integer_multiple(adt.bitwidth(), 8)
new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw))
adt = DataType[new_adt_name]
- self.set_nodeattr("accDataType", adt.name)
# for no-activation nodes, output dt = acc dt
self.set_nodeattr("outputDataType", adt.name)
+ self.set_nodeattr("accDataType", adt.name)
return DataType[self.get_nodeattr("accDataType")]
+ def minimize_weight_bit_width(self, model):
+ """Minimize the bit width based on the values of the weights"""
+ if not self.get_nodeattr("runtime_writeable_weights"):
+ weights = model.get_initializer(self.onnx_node.input[1])
+ w_min = weights.min()
+ w_max = weights.max()
+ if w_min < 0:
+ if abs(w_min) > w_max:
+ wdt = DataType.get_smallest_possible(w_min)
+ else:
+ wdt = DataType.get_smallest_possible(-w_max - 1)
+ else:
+ wdt = DataType.get_smallest_possible(w_max)
+ self.set_nodeattr("weightDataType", wdt.name)
+ return DataType[self.get_nodeattr("weightDataType")]
+
def calc_wmem(self):
"""Calculates and returns WMEM."""
ch = self.get_nodeattr("Channels")
k_h, k_w = self.get_nodeattr("Kernel")
pe = self.get_nodeattr("PE")
- wmem = k_h * k_w * ch // pe
+ simd = self.get_nodeattr("SIMD")
+ wmem = (k_h * k_w * ch // pe) // simd
return wmem
def calc_tmem(self):
@@ -216,13 +257,19 @@ class VectorVectorActivation(HLSCustomOp):
"""Returns FINN DataType of weights."""
return DataType[self.get_nodeattr("weightDataType")]
+ def get_accumulator_datatype(self):
+ """Returns FINN DataType of accumulator"""
+ return DataType[self.get_nodeattr("accDataType")]
+
def get_output_datatype(self, ind=0):
"""Returns FINN DataType of output."""
return DataType[self.get_nodeattr("outputDataType")]
def get_instream_width(self, ind=0):
i_bits = self.get_input_datatype().bitwidth()
- in_width = i_bits * self.get_nodeattr("PE")
+ simd = self.get_nodeattr("SIMD")
+ pe = self.get_nodeattr("PE")
+ in_width = i_bits * simd * pe
return in_width
def get_outstream_width(self, ind=0):
@@ -232,15 +279,21 @@ class VectorVectorActivation(HLSCustomOp):
def get_folded_input_shape(self, ind=0):
k_h, k_w = self.get_nodeattr("Kernel")
- sf = k_h * k_w
dim_h, dim_w = self.get_nodeattr("Dim")
ch = self.get_nodeattr("Channels")
+ simd = self.get_nodeattr("SIMD")
pe = self.get_nodeattr("PE")
+ kernel_2 = k_h * k_w
+ assert (
+ kernel_2 % simd == 0
+ ), "Requirement kernel (k_h * k_w) divisable by SIMD is violated."
+ sf = kernel_2 // simd
+ assert ch % pe == 0, "Requirement Channels divisable by PE is violated."
nf = ch // pe
if ind == 0:
# calculate shape of input 0
- folded_input_shape = tuple([1, dim_h, dim_w, sf * nf, pe])
+ folded_input_shape = tuple([1, dim_h, dim_w, sf * nf, simd * pe])
elif ind == 1 and self.get_nodeattr("mem_mode") == "external":
# calculate shape of input 1 (weights)
folded_input_shape = tuple([1, sf * nf, pe])
@@ -276,6 +329,7 @@ class VectorVectorActivation(HLSCustomOp):
def get_exp_cycles(self):
pe = self.get_nodeattr("PE")
+ simd = self.get_nodeattr("SIMD")
ch = self.get_nodeattr("Channels")
dim_h, dim_w = self.get_nodeattr("Dim")
k_h, k_w = self.get_nodeattr("Kernel")
@@ -283,7 +337,7 @@ class VectorVectorActivation(HLSCustomOp):
batch_size = 1
# since mmv != 1 is not supported yet, we set mmv for now to 1
mmv = 1
- exp_cycles = ((ch * k_h * k_w) / pe) * batch_size * (dim_h * dim_w) / mmv
+ exp_cycles = ((ch * k_h * k_w) / pe / simd) * batch_size * (dim_h * dim_w) / mmv
return int(exp_cycles)
def get_template_param_values(self):
@@ -327,6 +381,7 @@ class VectorVectorActivation(HLSCustomOp):
def get_hls_compatible_weight_tensor(self, orig_weight_matrix):
pe = self.get_nodeattr("PE")
+ simd = self.get_nodeattr("SIMD")
ch = self.get_nodeattr("Channels")
k_h, k_w = self.get_nodeattr("Kernel")
wmem = self.calc_wmem()
@@ -338,10 +393,13 @@ class VectorVectorActivation(HLSCustomOp):
), """Weights matrix doesn't
have expected shape (channels, 1, kernel_size, kernel_size)"""
ret = orig_weight_matrix
+ if self.get_weight_datatype() == DataType["BIPOLAR"]:
+ # convert bipolar to binary
+ ret = (ret + 1) / 2
ret = ret.reshape(ch, k_h * k_w)
# distribute rows between PEs
ret = interleave_matrix_outer_dim_from_partitions(ret, pe)
- ret = ret.reshape(1, pe, wmem, 1)
+ ret = ret.reshape(1, pe, wmem, simd)
return ret
def get_hls_compatible_threshold_tensor(self, orig_thres_matrix):
@@ -375,13 +433,6 @@ class VectorVectorActivation(HLSCustomOp):
# ensure all thresholds are integer
assert (orig_thres_matrix.astype(np.int32) == orig_thres_matrix).all()
ret = orig_thres_matrix
- # workaround for vivado_hls threshold bug
- if ret[0][0] == 0 and n_thres_steps == 1:
- ret = np.copy(ret)
- ret[0][0] = 1
- warnings.warn(
- "Setting 0-valued first threshold to 1 to avoid vivado_hls bug"
- )
# ensure channels = mh , duplicating if necessary
if ret.shape[0] == 1:
ret = np.tile(ret, (ch, 1))
@@ -432,7 +483,8 @@ class VectorVectorActivation(HLSCustomOp):
f_weights = open(weight_file_name, "w")
if export_wdt.bitwidth() != 1:
f_weights.write(
- "const FixedPointWeights<1,{},{},{}> weights = ".format(
+ "const FixedPointWeights<{},{},{},{}> weights = ".format(
+ self.get_nodeattr("SIMD"),
export_wdt.get_hls_datatype_str(),
self.get_nodeattr("PE"),
self.calc_wmem(),
@@ -440,7 +492,8 @@ class VectorVectorActivation(HLSCustomOp):
)
else:
f_weights.write(
- "const BinaryWeights<1,{},{}> weights = ".format(
+ "const BinaryWeights<{},{},{}> weights = ".format(
+ self.get_nodeattr("SIMD"),
self.get_nodeattr("PE"),
self.calc_wmem(),
)
@@ -457,7 +510,7 @@ class VectorVectorActivation(HLSCustomOp):
weight_tensor_pe_flipped = np.flip(weight_tensor_unflipped, axis=-2)
# reshape weight tensor (simd_flipped and pe_flipped) to desired shape
pe = self.get_nodeattr("PE")
- simd = 1
+ simd = self.get_nodeattr("SIMD")
# simd_flipped
weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape(
1, -1, pe * simd
@@ -527,28 +580,10 @@ class VectorVectorActivation(HLSCustomOp):
self.make_weight_file(weights, "decoupled_npy", weight_filename_sim)
if mem_mode == "decoupled":
# also save weights as Verilog .dat file
- # note that we provide two different .dat files, one for synth
- # and one for synthesis. this is because URAM-based weights always
- # need zero weights for synthesis, otherwise they get inferred
- # as BRAM
- weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(
- code_gen_dir
- )
- weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir)
- # sim weights are always the true weights
- self.make_weight_file(
- weights, "decoupled_verilog_dat", weight_filename_rtl_sim
- )
- ram_style = self.get_nodeattr("ram_style")
- if ram_style == "ultra":
- # UltraRAM must have no memory initializer, or only zeroes
- # otherwise BRAM will be inferred instead of URAM
- # as a workaround we provide a zero-weight init here
- synth_weights = np.zeros_like(weights, dtype=np.float32)
- else:
- synth_weights = weights
+ # This file will be ignored when synthesizing UltraScale memory.
+ weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir)
self.make_weight_file(
- synth_weights, "decoupled_verilog_dat", weight_filename_rtl_synth
+ weights, "decoupled_verilog_dat", weight_filename_rtl
)
else:
raise Exception(
@@ -636,6 +671,12 @@ class VectorVectorActivation(HLSCustomOp):
not float32 as expected."""
expected_inp_shape = self.get_folded_input_shape()
reshaped_input = context[inputs].reshape(expected_inp_shape)
+ if self.get_input_datatype() == DataType["BIPOLAR"]:
+ # store bipolar activations as binary
+ reshaped_input = (reshaped_input + 1) / 2
+ export_idt = DataType["BINARY"]
+ else:
+ export_idt = self.get_input_datatype()
# make copy before saving the array
reshaped_input = reshaped_input.copy()
np.save(
@@ -651,14 +692,20 @@ class VectorVectorActivation(HLSCustomOp):
super().exec_precompiled_singlenode_model()
# load output npy file
super().npy_to_dynamic_output(context)
+ # reinterpret binary output as bipolar where needed
+ if self.get_output_datatype() == DataType["BIPOLAR"]:
+ out = context[node.output[0]]
+ out = 2 * out - 1
+ context[node.output[0]] = out
assert (
context[node.output[0]].shape == self.get_normal_output_shape()
), "cppsim did not produce expected output shape"
elif mode == "rtlsim":
sim = self.get_rtlsim()
nbits = self.get_instream_width()
- idt = self.get_input_datatype()
- inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), idt, nbits)
+ inp = npy_to_rtlsim_input(
+ "{}/input_0.npy".format(code_gen_dir), export_idt, nbits
+ )
super().reset_rtlsim(sim)
super().toggle_clk(sim)
@@ -726,9 +773,10 @@ class VectorVectorActivation(HLSCustomOp):
self.code_gen_dict["$DEFINES$"] = [
"""#define Channels1 {}\n #define InnerProdDim {}\n
- #define SIMD1 1\n #define PE1 {}\n #define numReps {}""".format(
+ #define SIMD1 {}\n #define PE1 {}\n #define numReps {}""".format(
self.get_nodeattr("Channels"),
innerProdDim,
+ self.get_nodeattr("SIMD"),
self.get_nodeattr("PE"),
numReps,
)
@@ -742,6 +790,9 @@ class VectorVectorActivation(HLSCustomOp):
def read_npy_data(self):
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
dtype = self.get_input_datatype()
+ if dtype == DataType["BIPOLAR"]:
+ # use binary for bipolar storage
+ dtype = DataType["BINARY"]
elem_bits = dtype.bitwidth()
packed_bits = self.get_instream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
@@ -839,6 +890,9 @@ class VectorVectorActivation(HLSCustomOp):
def dataoutstrm(self):
code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim")
dtype = self.get_output_datatype()
+ if dtype == DataType["BIPOLAR"]:
+ # use binary for bipolar storage
+ dtype = DataType["BINARY"]
elem_bits = dtype.bitwidth()
packed_bits = self.get_outstream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
@@ -996,7 +1050,7 @@ class VectorVectorActivation(HLSCustomOp):
% (self.get_nodeattr("ip_vlnv"), node_name, node_name)
)
# instantiate a streamer and connect it to the HLS IP
- strm_vlnv = "xilinx.com:user:memstream:1.0"
+ strm_vlnv = "amd.com:finn:memstream:1.0"
strm_inst = node_name + "_wstrm"
cmd.append(
"create_bd_cell -type ip -vlnv %s /%s/%s"
@@ -1004,22 +1058,16 @@ class VectorVectorActivation(HLSCustomOp):
)
cmd.append(
"set_property -dict [list "
- "CONFIG.NSTREAMS {1} "
- "CONFIG.MEM_DEPTH {%d} "
- "CONFIG.MEM_WIDTH {%d} "
- "CONFIG.MEM_INIT {%s} "
+ "CONFIG.DEPTH {%d} "
+ "CONFIG.WIDTH {%d} "
+ "CONFIG.INIT_FILE {%s} "
"CONFIG.RAM_STYLE {%s} "
- "CONFIG.STRM0_DEPTH {%d} "
- "CONFIG.STRM0_WIDTH {%d} "
- "CONFIG.STRM0_OFFSET {0} "
"] [get_bd_cells /%s/%s]"
% (
self.calc_wmem(),
self.get_weightstream_width_padded(),
- self.get_nodeattr("code_gen_dir_ipgen") + "/",
+ self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat",
self.get_nodeattr("ram_style"),
- self.calc_wmem(),
- self.get_weightstream_width_padded(),
node_name,
strm_inst,
)
@@ -1030,11 +1078,11 @@ class VectorVectorActivation(HLSCustomOp):
% (node_name, strm_inst, node_name, node_name, sname)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]"
% (node_name, rst_name, node_name, strm_inst)
)
cmd.append(
- "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]"
+ "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]"
% (node_name, clk_name, node_name, strm_inst)
)
cmd.append(
@@ -1080,7 +1128,7 @@ class VectorVectorActivation(HLSCustomOp):
def uram_estimation(self):
P = self.get_nodeattr("PE")
- Q = 1
+ Q = self.get_nodeattr("SIMD")
wdt = self.get_weight_datatype()
W = wdt.bitwidth()
omega = self.calc_wmem()
@@ -1089,7 +1137,7 @@ class VectorVectorActivation(HLSCustomOp):
mstyle = self.get_nodeattr("ram_style")
if (
(mmode == "decoupled" and mstyle != "ultra")
- or (mmode == "const" and self.calc_wmem() <= 128)
+ or (mmode == "const")
or (mmode == "external")
):
return 0
@@ -1101,9 +1149,11 @@ class VectorVectorActivation(HLSCustomOp):
"""Calculates resource estimation for BRAM"""
# TODO add in/out FIFO contributions
P = self.get_nodeattr("PE")
+ Q = self.get_nodeattr("SIMD")
wdt = self.get_weight_datatype()
W = wdt.bitwidth()
omega = self.calc_wmem()
+ mem_width = Q * W * P
# assuming SDP mode RAMB18s (see UG573 Table 1-10)
# since this is HLS memory, not using the full width of a BRAM
# assuming memories up to 128 deep get implemented in LUTs
@@ -1111,23 +1161,24 @@ class VectorVectorActivation(HLSCustomOp):
mstyle = self.get_nodeattr("ram_style")
if (
(mmode == "decoupled" and mstyle in ["distributed", "ultra"])
+ or (mstyle == "auto" and self.calc_wmem() <= 128)
or (mmode == "const" and self.calc_wmem() <= 128)
or (mmode == "external")
):
return 0
- if W == 1:
- return math.ceil(omega / 16384) * P
- elif W == 2:
- return math.ceil(omega / 8192) * P
- elif W <= 4:
- return (math.ceil(omega / 4096)) * (math.ceil(W / 4)) * P
- elif W <= 9:
- return (math.ceil(omega / 2048)) * (math.ceil(W / 8)) * P
- elif W <= 18 or omega > 512:
- return (math.ceil(omega / 1024)) * (math.ceil(W / 16)) * P
+ if mem_width == 1:
+ return math.ceil(omega / 16384)
+ elif mem_width == 2:
+ return math.ceil(omega / 8192)
+ elif mem_width <= 4:
+ return (math.ceil(omega / 4096)) * (math.ceil(mem_width / 4))
+ elif mem_width <= 9:
+ return (math.ceil(omega / 2048)) * (math.ceil(mem_width / 8))
+ elif mem_width <= 18 or omega > 512:
+ return (math.ceil(omega / 1024)) * (math.ceil(mem_width / 16))
else:
- return (math.ceil(omega / 512)) * (math.ceil(W / 32)) * P
+ return (math.ceil(omega / 512)) * (math.ceil(mem_width / 32))
def bram_efficiency_estimation(self):
P = self.get_nodeattr("PE")
@@ -1151,6 +1202,7 @@ class VectorVectorActivation(HLSCustomOp):
"""
# TODO add in/out FIFO contributions
P = self.get_nodeattr("PE")
+ Q = self.get_nodeattr("SIMD")
wdt = self.get_weight_datatype()
W = wdt.bitwidth()
# determine tdt with input and weight data types
@@ -1165,29 +1217,46 @@ class VectorVectorActivation(HLSCustomOp):
if (mmode == "decoupled" and mstyle == "distributed") or (
mmode == "const" and self.calc_wmem() <= 128
):
- c2 = (P * W) * math.ceil(self.calc_wmem() / 64)
+ c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64)
# multiplication
res_type = self.get_nodeattr("resType")
if res_type == "dsp":
mult_luts = 0
else:
- mult_luts = (2 * math.ceil((W + A) / 6) - 1) * (W + A)
+ mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A)
+ # adder tree
+ addertree_luts = (W + A) * (2 * Q - 1)
# accumulator
+ acc_datatype = self.get_accumulator_datatype()
+ acc_bits = acc_datatype.bitwidth()
k_h, k_w = self.get_nodeattr("Kernel")
- acc_bits = W + A + math.ceil(math.log(k_h * k_w, 2))
+ # if accDataType is not set, then it will default to INT32, which would
+ # be a large overestimate in most (if not all) cases. In this scenario,
+ # we would use the minimum accumulator as determined by the data types
+ # bound, derived in https://arxiv.org/abs/2301.13376
+ alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed())
+ acc_bits = min(
+ acc_datatype.bitwidth(),
+ np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1),
+ )
acc_luts = acc_bits
# thresholds and threshold comparators
thr_luts = 0
comp_luts = 0
noact = self.get_nodeattr("noActivation")
+ # TODO - add 'ram_style_threshold' node attribute
if noact == 0:
odt = self.get_output_datatype()
B = odt.bitwidth()
- thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64)
+ thr_luts = (2**B - 1) * acc_bits * self.calc_tmem() / 64
comp_luts = (2**B - 1) * acc_bits
- return int(c0 + c1 * (P * (mult_luts + acc_luts + thr_luts + comp_luts)) + c2)
+ return int(
+ c0
+ + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts))
+ + c2
+ )
def dsp_estimation(self):
# multiplication
@@ -1209,9 +1278,10 @@ class VectorVectorActivation(HLSCustomOp):
self.get_nodeattr("mem_mode") == "decoupled"
or self.get_nodeattr("mem_mode") == "external"
):
+ simd = self.get_nodeattr("SIMD")
pe = self.get_nodeattr("PE")
wp = self.get_weight_datatype().bitwidth()
- w_width = pe * wp
+ w_width = simd * pe * wp
return w_width
else:
return 0
diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py
index 2096760580b4f33ba1ab09564ebba1601c4dc23c..5f6f00da13de551a3e3cd234ad28458ca3cc6287 100644
--- a/src/finn/qnn-data/templates/driver/driver_base.py
+++ b/src/finn/qnn-data/templates/driver/driver_base.py
@@ -189,14 +189,10 @@ class FINNExampleOverlay(Overlay):
layer_ind = int(w_filename.split("_")[1])
rt_weight_dict[(sdp_ind, layer_ind)] = layer_w
for sdp_ind, layer_ind in rt_weight_dict.keys():
- cand_if_name = "StreamingDataflowPartition_%d/s_axilite_%d" % (
- sdp_ind,
- layer_ind,
- )
+ cand_if_name = "StreamingDataflowPartition_%d" % sdp_ind
if cand_if_name in self.ip_dict.keys():
layer_mmio = getattr(
- getattr(self, "StreamingDataflowPartition_%d" % sdp_ind),
- "s_axilite_%d" % layer_ind,
+ self, "StreamingDataflowPartition_%d" % sdp_ind
).mmio
layer_w = rt_weight_dict[(sdp_ind, layer_ind)]
layer_mmio.write_mm(0, layer_w.tobytes())
diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py
index 7b8a1bf6b83175cfda041cfc49a22273fd696d8e..fcfe9e7727b60bd33fea7a56d312cf4789c0189a 100644
--- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py
+++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py
@@ -40,10 +40,6 @@ from qonnx.transformation.infer_shapes import InferShapes
from qonnx.util.basic import get_by_name
from qonnx.util.onnx import nchw_to_nhwc
-from finn.transformation.fpgadataflow.minimize_accumulator_width import (
- MinimizeAccumulatorWidth,
-)
-
class InferConvInpGen(Transformation):
"""Convert Im2Col layers to ConvolutionInputGenerator layers."""
@@ -144,19 +140,7 @@ class InferConvInpGen(Transformation):
k_h > 1 and k_w == 1 and ifm_dim_w == 1
)
- # Ensure that RTL variant is not inserted for unsupported configuration
- is_rtl_variant_compatible = True
- if is_kernel_pointwise:
- is_rtl_variant_compatible = False
- if self.use_rtl_variant:
- warnings.warn(
- """%s : RTL ConvInpGen requested for unsupported
- configuration. Falling back to HLS implementation."""
- % n.name
- )
-
- if self.use_rtl_variant and is_rtl_variant_compatible:
-
+ if self.use_rtl_variant:
ConvInpGen_node = helper.make_node(
"ConvolutionInputGenerator_rtl",
[ConvInpGen_input],
@@ -761,7 +745,6 @@ class InferBinaryMatrixVectorActivation(Transformation):
graph.node.remove(n)
graph_modified = True
if graph_modified:
- model = model.transform(MinimizeAccumulatorWidth())
model = model.transform(InferShapes())
model = model.transform(InferDataTypes())
return (model, graph_modified)
@@ -904,7 +887,6 @@ class InferQuantizedMatrixVectorActivation(Transformation):
graph.node.remove(n)
graph_modified = True
if graph_modified:
- model = model.transform(MinimizeAccumulatorWidth())
model = model.transform(InferShapes())
model = model.transform(InferDataTypes())
return (model, graph_modified)
@@ -1057,7 +1039,6 @@ class InferVectorVectorActivation(Transformation):
graph.node.remove(n)
graph_modified = True
if graph_modified:
- model = model.transform(MinimizeAccumulatorWidth())
model = model.transform(InferShapes())
model = model.transform(InferDataTypes())
return (model, graph_modified)
@@ -1135,7 +1116,8 @@ class InferThresholdingLayer(Transformation):
PE=pe,
numSteps=thl_thres_shape[1],
inputDataType=idt.name,
- weightDataType=idt.name, # will be set by MinimizeAccumulatorWidth
+ # weightDataType can be tightened by MinimizeAccumulatorWidth
+ weightDataType=idt.name,
outputDataType=odt.name,
numInputVectors=list(thl_in_shape[:-1]),
ActVal=actval,
@@ -1148,7 +1130,6 @@ class InferThresholdingLayer(Transformation):
graph_modified = True
if graph_modified:
- model = model.transform(MinimizeAccumulatorWidth())
model = model.transform(InferShapes())
model = model.transform(InferDataTypes())
return (model, graph_modified)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 8e2c69bad4b0a6749c605bea9ee21d6408c904c0..ef1afb95ca5fb97add4092d75d40b65c81349195 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -385,6 +385,8 @@ class CreateStitchedIP(Transformation):
"create_project %s %s -part %s"
% (prjname, vivado_stitch_proj_dir, self.fpgapart)
)
+ # no warnings on long module names
+ tcl.append("set_msg_config -id {[BD 41-1753]} -suppress")
# add all the generated IP dirs to ip_repo_paths
ip_dirs_str = " ".join(ip_dirs)
tcl.append("set_property ip_repo_paths [%s] [current_project]" % ip_dirs_str)
@@ -397,8 +399,9 @@ class CreateStitchedIP(Transformation):
fclk_mhz = 1 / (self.clk_ns * 0.001)
fclk_hz = fclk_mhz * 1000000
model.set_metadata_prop("clk_ns", str(self.clk_ns))
- tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk]" % fclk_hz)
- tcl.append("regenerate_bd_layout")
+ tcl.append(
+ "set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz)
+ )
tcl.append("validate_bd_design")
tcl.append("save_bd_design")
# create wrapper hdl (for rtlsim later on)
@@ -412,7 +415,7 @@ class CreateStitchedIP(Transformation):
wrapper_filename = "%s/hdl/%s_wrapper.v" % (bd_base, block_name)
tcl.append("add_files -norecurse %s" % wrapper_filename)
model.set_metadata_prop("wrapper_filename", wrapper_filename)
- tcl.append("set_property top finn_design_wrapper [current_fileset]")
+ tcl.append("set_property top %s_wrapper [current_fileset]" % block_name)
# synthesize to DCP and export stub, DCP and constraints
if self.vitis:
tcl.append(
@@ -450,6 +453,8 @@ class CreateStitchedIP(Transformation):
)
% (vivado_stitch_proj_dir, block_vendor, block_library, block_name)
)
+ # Allow user to customize clock in deployment of stitched IP
+ tcl.append("set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]")
# in some cases, the IP packager seems to infer an aperture of 64K or 4G,
# preventing address assignment of the DDR_LOW and/or DDR_HIGH segments
# the following is a hotfix to remove this aperture during IODMA packaging
@@ -544,20 +549,83 @@ class CreateStitchedIP(Transformation):
# add a rudimentary driver mdd to get correct ranges in xparameters.h later on
example_data_dir = pk.resource_filename("finn.qnn-data", "mdd-data/")
copytree(example_data_dir, vivado_stitch_proj_dir + "/data")
- tcl.append("file copy -force data ip/")
- tcl.append("ipx::add_file_group -type software_driver {} [ipx::current_core]")
- tcl.append(
- "set_property type mdd [ipx::add_file data/finn_design.mdd "
- "[ipx::get_file_groups xilinx_softwaredriver -of_objects "
- "[ipx::current_core]]]"
- )
+
+ #####
+ # Core Cleanup Operations
tcl.append(
- "set_property type tclSource [ipx::add_file data/finn_design.tcl "
- "[ipx::get_file_groups xilinx_softwaredriver -of_objects "
- "[ipx::current_core]]]"
+ """
+set core [ipx::current_core]
+
+# Add rudimentary driver
+file copy -force data ip/
+set file_group [ipx::add_file_group -type software_driver {} $core]
+set_property type mdd [ipx::add_file data/finn_design.mdd $file_group]
+set_property type tclSource [ipx::add_file data/finn_design.tcl $file_group]
+
+# Remove all XCI references to subcores
+set impl_files [ipx::get_file_groups xilinx_implementation -of $core]
+foreach xci [ipx::get_files -of $impl_files {*.xci}] {
+ ipx::remove_file [get_property NAME $xci] $impl_files
+}
+
+# Construct a single flat memory map for each AXI-lite interface port
+foreach port [get_bd_intf_ports -filter {CONFIG.PROTOCOL==AXI4LITE}] {
+ set pin $port
+ set awidth ""
+ while { $awidth == "" } {
+ set pins [get_bd_intf_pins -of [get_bd_intf_nets -boundary_type lower -of $pin]]
+ set kill [lsearch $pins $pin]
+ if { $kill >= 0 } { set pins [lreplace $pins $kill $kill] }
+ if { [llength $pins] != 1 } { break }
+ set pin [lindex $pins 0]
+ set awidth [get_property CONFIG.ADDR_WIDTH $pin]
+ }
+ if { $awidth == "" } {
+ puts "CRITICAL WARNING: Unable to construct address map for $port."
+ } {
+ set range [expr 2**$awidth]
+ puts "INFO: Building address map for $port: 0+:$range"
+ set name [get_property NAME $port]
+ set addr_block [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]]
+ set_property range $range $addr_block
+ set_property slave_memory_map_ref $name [ipx::get_bus_interfaces $name -of $core]
+ }
+}
+
+# Finalize and Save
+ipx::update_checksums $core
+ipx::save_core $core
+
+# Remove stale subcore references from component.xml
+file rename -force ip/component.xml ip/component.bak
+set ifile [open ip/component.bak r]
+set ofile [open ip/component.xml w]
+set buf [list]
+set kill 0
+while { [eof $ifile] != 1 } {
+ gets $ifile line
+ if { [string match {*<spirit:fileSet>*} $line] == 1 } {
+ foreach l $buf { puts $ofile $l }
+ set buf [list $line]
+ } elseif { [llength $buf] > 0 } {
+ lappend buf $line
+
+ if { [string match {*</spirit:fileSet>*} $line] == 1 } {
+ if { $kill == 0 } { foreach l $buf { puts $ofile $l } }
+ set buf [list]
+ set kill 0
+ } elseif { [string match {*<xilinx:subCoreRef>*} $line] == 1 } {
+ set kill 1
+ }
+ } else {
+ puts $ofile $line
+ }
+}
+close $ifile
+close $ofile
+"""
)
- tcl.append("ipx::update_checksums [ipx::find_open_core %s]" % block_vlnv)
- tcl.append("ipx::save_core [ipx::find_open_core %s]" % block_vlnv)
+
# export list of used Verilog files (for rtlsim later on)
tcl.append(
"set all_v_files [get_files -filter {USED_IN_SYNTHESIS == 1 "
diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py
index 632d1f813b4d2509407930bc9294f7531d4c90af..cff8b602674fec41a1e6fd1d467acdc989b4afe2 100644
--- a/src/finn/transformation/fpgadataflow/insert_dwc.py
+++ b/src/finn/transformation/fpgadataflow/insert_dwc.py
@@ -81,15 +81,11 @@ class InsertDWC(Transformation):
dwc_in_width = n0.get_outstream_width()
# determine dwc outwidth
dwc_out_width = n1.get_instream_width()
- larger_width = max(dwc_in_width, dwc_out_width)
- smaller_width = min(dwc_in_width, dwc_out_width)
- both_8bit_aligned = (larger_width % 8 == 0) and (
- smaller_width % 8 == 0
- )
- if both_8bit_aligned:
- impl_style = "vivado"
- else:
- impl_style = "hls"
+ # use hls mode by default since it supports more configs
+ # vivado mode can be manually enabled by user, but does not
+ # support e.g. node-by-node rtlsim neded for
+ # characterization-based FIFO sizing
+ impl_style = "hls"
# determine shape for dwc
dwc_shape = n0.get_normal_output_shape()
diff --git a/src/finn/transformation/fpgadataflow/make_deployment.py b/src/finn/transformation/fpgadataflow/make_deployment.py
deleted file mode 100644
index d4684dc83ce1f22ecae2ca04af5e5973519db4f6..0000000000000000000000000000000000000000
--- a/src/finn/transformation/fpgadataflow/make_deployment.py
+++ /dev/null
@@ -1,116 +0,0 @@
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import os
-import subprocess
-from distutils.dir_util import copy_tree
-from qonnx.transformation.base import Transformation
-from shutil import copy
-
-import finn.transformation.fpgadataflow.templates as templates
-from finn.util.basic import make_build_dir
-
-
-class DeployToPYNQ(Transformation):
- """Collects all necessary files for deployment and copies them to the PYNQ board.
- Expects information about PYNQ board to make scp possible:
-
- IP address of board, username and password for board and target directory where
- the files are stored on the board"""
-
- def __init__(self, ip, port, username, password, target_dir):
- super().__init__()
- self.ip = ip
- self.port = port
- self.username = username
- self.password = password
- self.target_dir = target_dir
-
- def apply(self, model):
- # set metadata properties accordingly to user input specifications
- model.set_metadata_prop("pynq_ip", self.ip)
- model.set_metadata_prop("pynq_port", str(self.port))
- model.set_metadata_prop("pynq_username", self.username)
- model.set_metadata_prop("pynq_password", self.password)
- model.set_metadata_prop("pynq_target_dir", self.target_dir)
-
- # create directory for deployment files
- deployment_dir = make_build_dir(prefix="pynq_deployment_")
- model.set_metadata_prop("pynq_deployment_dir", deployment_dir)
-
- # get and copy necessary files
- # .bit and .hwh file
- bitfile = model.get_metadata_prop("bitfile")
- hwh_file = model.get_metadata_prop("hw_handoff")
- deploy_files = [bitfile, hwh_file]
-
- for dfile in deploy_files:
- if dfile is not None:
- copy(dfile, deployment_dir)
-
- # helper script for Alveo
- platform = model.get_metadata_prop("platform")
- if platform == "alveo":
- alveo_run_sh = templates.alveo_run_sh_template
- fill_dict = {
- "$REMOTE_DEPLOY_DIR$": self.target_dir
- + "/"
- + os.path.basename(deployment_dir),
- "$CONDA_ENV_NAME$": "finn-pynq-alveo",
- "$REMOTE_XRT$": os.environ["XILINX_XRT"],
- "$REMOTE_PLATFORM_REPO_PATHS$": os.environ["PLATFORM_REPO_PATHS"],
- "$BITFILE$": os.path.basename(bitfile),
- }
- for key, value in fill_dict.items():
- alveo_run_sh = alveo_run_sh.replace(key, value)
- alveo_run_sh_path = deployment_dir + "/alveo_run.sh"
- with open(alveo_run_sh_path, "w") as f:
- f.write(alveo_run_sh)
-
- # driver.py and python libraries
- pynq_driver_dir = model.get_metadata_prop("pynq_driver_dir")
- copy_tree(pynq_driver_dir, deployment_dir)
- model.set_metadata_prop("pynq_deploy_dir", deployment_dir)
- model.set_metadata_prop("exec_mode", "remote_pynq")
-
- # create target directory on PYNQ board
- cmd = 'ssh {}@{} -p {} "mkdir -p {}"'.format(
- self.username, self.ip, self.port, self.target_dir
- )
- bash_command = ["/bin/bash", "-c", cmd]
- process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
- process_compile.communicate()
- # copy directory to PYNQ board using scp
- cmd = "scp -P{} -r {} {}@{}:{}".format(
- self.port, deployment_dir, self.username, self.ip, self.target_dir
- )
- bash_command = ["/bin/bash", "-c", cmd]
- process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
- process_compile.communicate()
-
- return (model, False)
diff --git a/tests/end2end/test_end2end_access_board.py b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py
similarity index 64%
rename from tests/end2end/test_end2end_access_board.py
rename to src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py
index ba3c49195b298059149303c63ef2db8ab6e16039..32871cc44a886fddcf3363fc06a3c6831a3d92bc 100644
--- a/tests/end2end/test_end2end_access_board.py
+++ b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2021, Xilinx
+# Copyright (C) 2023, Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -26,31 +26,24 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-import pytest
+from qonnx.custom_op.registry import getCustomOp
+from qonnx.transformation.base import Transformation
-import subprocess
+from finn.util.fpgadataflow import is_fpgadataflow_node
-from finn.util.test import get_build_env
+class MinimizeWeightBitWidth(Transformation):
+ """For relevant nodes, call the weight bit width minimization
+ functions to save on resources. May alter tensor weightDataType
+ if the node does not have runtime writeable weights."""
-@pytest.mark.board
-@pytest.mark.end2end
-def test_end2end_access_board():
- build_env = get_build_env("zynq", 5)
- if build_env["ip"] == "":
- pytest.skip("PYNQ board IP address not specified")
- remote_cmd_base = [
- "ssh",
- "-o",
- "PreferredAuthentications=publickey",
- "-o",
- "PasswordAuthentication=no",
- "%s@%s" % (build_env["username"], build_env["ip"]),
- ]
- test_text = "BoardIsAccessible"
- touch_cmd = remote_cmd_base + ["echo %s" % test_text]
- verif_res = subprocess.run(
- touch_cmd, stdout=subprocess.PIPE, universal_newlines=True
- )
- assert verif_res.returncode == 0
- assert verif_res.stdout.split("\n")[0] == test_text
+ def __init__(self):
+ super().__init__()
+
+ def apply(self, model):
+ for node in model.graph.node:
+ if is_fpgadataflow_node(node) is True:
+ inst = getCustomOp(node)
+ if hasattr(inst, "minimize_weight_bit_width"):
+ inst.minimize_weight_bit_width(model)
+ return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py
index 2301fccdd4fff6310340ffe1dd8de7732a4f9bd4..0a466afe13fa3b96b7bcfefede16cfdf2cb5449c 100644
--- a/src/finn/transformation/fpgadataflow/set_folding.py
+++ b/src/finn/transformation/fpgadataflow/set_folding.py
@@ -75,7 +75,9 @@ class SetFolding(Transformation):
* the producer of the node is expected to be a ConvolutionInputGenerator
with depthwise=1, whose SIMD value will be set equal to the PE value of
its consumer node
-
+ * the VVAU also supports SIMD ("input window") parallelism next to
+ PE ("channels"), but current ConvInpGen limitations require PE to be fully
+ unfolded before SIMD is increased
"""
def __init__(
@@ -106,7 +108,9 @@ class SetFolding(Transformation):
"Thresholding_Batch",
]
# these ops use SIMD parallelism, up to a max value of NumChannels
- # ConvolutionInputGenerator has a special case when depthwise=1
+ # ConvolutionInputGenerator* has a special case when depthwise=1
+ # ConvolutionInputGenerator_rtl supports additional parallelism by
+ # setting parallel_window=1 mode after maxing out SIMD
simd_ops = [
"DownSampler",
"FMPadding_Batch",
@@ -154,15 +158,36 @@ class SetFolding(Transformation):
max_pe = node_inst.get_nodeattr("Labels")
self.optimize_attribute_val(node_inst, max_pe, "PE")
elif op_type in depthwise_op_exceptions:
+ # init/reset SIMD of VVAU
+ if op_type == "VectorVectorActivation":
+ node_inst.set_nodeattr("SIMD", 1)
max_pe = node_inst.get_nodeattr("Channels")
self.optimize_attribute_val(node_inst, max_pe, "PE")
+ # increase SIMD for VVAU once PE is exhausted
+ pe = node_inst.get_nodeattr("PE")
+ cyc = node_inst.get_exp_cycles()
+ if (
+ op_type == "VectorVectorActivation"
+ and pe == max_pe
+ and cyc > self.target_cycles_per_frame
+ ):
+ max_simd = np.prod(node_inst.get_nodeattr("Kernel"))
+ self.optimize_attribute_val(node_inst, max_simd, "SIMD")
# also set the folding of the upsteam DW SWU
# which must be identical to this node
swu_node = model.find_producer(node.input[0])
if swu_node.op_type.startswith("ConvolutionInputGenerator"):
swu_node_inst = getCustomOp(swu_node)
- pe = node_inst.get_nodeattr("PE")
swu_node_inst.set_nodeattr("SIMD", pe)
+ # enable parallel_window mode of RTL SWG if needed
+ if swu_node.op_type == "ConvolutionInputGenerator_rtl":
+ if (
+ op_type == "VectorVectorActivation"
+ and node_inst.get_nodeattr("SIMD") > 1
+ ):
+ swu_node_inst.set_nodeattr("parallel_window", 1)
+ else:
+ swu_node_inst.set_nodeattr("parallel_window", 0)
else:
if op_type == "VectorVectorActivation":
ksize = np.prod(node_inst.get_nodeattr("Kernel"))
@@ -179,7 +204,19 @@ class SetFolding(Transformation):
depthwise = node_inst.get_nodeattr("depthwise")
if depthwise == 0:
max_simd = node_inst.get_nodeattr("IFMChannels")
+ # init/reset parallel_window mode of RTL SWG
+ if op_type == "ConvolutionInputGenerator_rtl":
+ node_inst.set_nodeattr("parallel_window", 0)
self.optimize_attribute_val(node_inst, max_simd, "SIMD")
+ # enable parallel_window mode of RTL SWG if needed
+ simd = node_inst.get_nodeattr("SIMD")
+ cyc = node_inst.get_exp_cycles()
+ if (
+ op_type == "ConvolutionInputGenerator_rtl"
+ and simd == max_simd
+ and cyc > self.target_cycles_per_frame
+ ):
+ node_inst.set_nodeattr("parallel_window", 1)
else:
# depthwise SWGs are handled separately
continue
diff --git a/src/finn/transformation/fpgadataflow/template_driver.py b/src/finn/transformation/fpgadataflow/template_driver.py
index 05ee6ad920d7e921dc9611a7936e28288ba53a0a..158825191e3372fc133e01b47ea7138b0aba899f 100644
--- a/src/finn/transformation/fpgadataflow/template_driver.py
+++ b/src/finn/transformation/fpgadataflow/template_driver.py
@@ -135,5 +135,5 @@ if __name__ == "__main__":
file.close()
print("Results written to nw_metrics.txt")
else:
- raise Exception("Exec mode has to be set to remote_pynq or throughput_test")
+ raise Exception("Exec mode has to be set to execute or throughput_test")
"""
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index f52bad0ffb35ae4714acc24aef368d01967db426..ce1545b5be88d87f65d5c39028057b5f4b651a41 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -242,22 +242,6 @@ report_utilization -hierarchical -hierarchical_depth 4 -file synth_report.xml -f
close_project
"""
-alveo_run_sh_template = """#!/bin/bash
-
-if [ "$#" -ne 2 ]; then
- echo "Usage: alveo_run.sh <exec_mode={execute, throughput_test}> <batch_size>"
- exit -1
-fi
-
-cd $REMOTE_DEPLOY_DIR$
-eval "$(conda shell.bash hook)"
-conda activate $CONDA_ENV_NAME$
-source $REMOTE_XRT$/setup.sh
-export PLATFORM_REPO_PATHS=$REMOTE_PLATFORM_REPO_PATHS$
-python3.6 driver.py --exec_mode=$1 --batchsize=$2 --bitfile=$BITFILE$ \
- --inputfile=input.npy --outputfile=output.npy --platform=alveo
-"""
-
vitis_gen_xml_report_tcl_template = """
open_project $VITIS_PROJ_PATH$/_x/link/vivado/vpl/prj/prj.xpr
open_run impl_1
diff --git a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py
index 5a3f176f1ff41f17bdf684d59433d4f184a7ccb5..d2aaee59a4767f36d2e948fa97b1deecb7f365ac 100644
--- a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py
+++ b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py
@@ -46,7 +46,7 @@ def _get_signed_from_upstream(model, trunc_node):
# Check if the input of this node already has a FINN datatype
signed = None
inp_dt = model.get_tensor_datatype(node.input[0])
- if inp_dt is not None and inp_dt is not DataType["FLOAT32"]:
+ if inp_dt is not None and inp_dt != DataType["FLOAT32"]:
signed = inp_dt.signed()
# Go further up the graph, since the datatype inference works top down
# these nodes should either be sign preserving ops or they already have a
@@ -67,23 +67,23 @@ def _get_signed_from_upstream(model, trunc_node):
)
next_node = next_node[0]
out_dt = model.get_tensor_datatype(next_node.output[0])
- if out_dt is not None and out_dt is not DataType["FLOAT32"]:
+ if out_dt is not None and out_dt != DataType["FLOAT32"]:
signed = out_dt.signed()
break
# Special cases where the node has an internal or intrinsic datatype.
if next_node.op_type == "MultiThreshold":
- mt_inst = getCustomOp(next_node)
+ mt_inst = getCustomOp(next_node, onnx_opset_version=9)
out_dt = DataType[mt_inst.get_nodeattr("out_dtype")]
- if out_dt is not None and out_dt is not DataType["FLOAT32"]:
+ if out_dt is not None and out_dt != DataType["FLOAT32"]:
signed = out_dt.signed()
break
if next_node.op_type == "BipolarQuant":
signed = True
break
if next_node.op_type == "Quant":
- q_inst = getCustomOp(next_node)
+ q_inst = getCustomOp(next_node, onnx_opset_version=9)
out_dt = q_inst.get_integer_datatype(model)
- if out_dt is not None and out_dt is not DataType["FLOAT32"]:
+ if out_dt is not None and out_dt != DataType["FLOAT32"]:
signed = out_dt.signed()
break
diff --git a/src/finn/transformation/qonnx/qonnx_activation_handlers.py b/src/finn/transformation/qonnx/qonnx_activation_handlers.py
index 9819086d826a51d1df5240d88c4fda8513cc9ba6..bbe5e1a0e319a8f62e9a1bcd4f0857f36295049e 100644
--- a/src/finn/transformation/qonnx/qonnx_activation_handlers.py
+++ b/src/finn/transformation/qonnx/qonnx_activation_handlers.py
@@ -286,6 +286,7 @@ class QuantReluHandler(QuantActBaseHandler):
def valid_predecessor_op_types(self):
return [
"Relu",
+ "Selu",
]
def _check_compatibility(self):
@@ -293,16 +294,19 @@ class QuantReluHandler(QuantActBaseHandler):
q_inst = getCustomOp(self._q_node)
narrow = q_inst.get_nodeattr("narrow")
signed = q_inst.get_nodeattr("signed")
- if signed or narrow:
- raise ValueError(
- "FINN only supports unsigned and non-narrow Quant nodes "
- "for Relu activations."
- )
if not self._model.get_initializer(self._q_node.input[2]) == 0:
raise ValueError(
"Only Quant nodes with zero-point == 0 "
"are currently supported for ReLu activations."
)
+ act_node = self._model.find_direct_predecessors(self._q_node)
+ act_node = act_node[0]
+ if act_node.op_type == "Relu":
+ if signed or narrow:
+ raise ValueError(
+ "FINN only supports unsigned and non-narrow Quant nodes "
+ "for Relu activations."
+ )
elif self._q_node.op_type == "BipolarQuant":
return
else:
@@ -312,7 +316,31 @@ class QuantReluHandler(QuantActBaseHandler):
# No bias allowed for Relu activations, see: https://github.com/Xilinx/
# brevitas/blob/a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/
# export/onnx/finn/handler/act.py#L48
- bias = np.array([0.0], dtype=np_default_dtype)
+ act_node = self._model.find_direct_predecessors(self._q_node)
+ act_node = act_node[0]
+ if act_node.op_type == "Relu":
+ bias = np.array([0.0], dtype=np_default_dtype)
+ elif act_node.op_type == "Selu":
+ # Gather parameters
+ q_inst = getCustomOp(self._q_node)
+ if self._q_node.op_type == "Quant":
+ bit_width = self._model.get_initializer(self._q_node.input[3])
+ narrow = q_inst.get_nodeattr("narrow")
+ elif self._q_node.op_type == "BipolarQuant":
+ bit_width = 1.0
+ else:
+ raise RuntimeError("Got an unexpected quantizer node type")
+ # Calculate bias, see: https://github.com/Xilinx/brevitas/blob/
+ # a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/export/
+ # onnx/finn/handler/act.py#L64
+ if bit_width == 1.0:
+ bias = np.array([-0.5], dtype=np_default_dtype)
+ else:
+ if narrow:
+ min_non_scaled_val = -(2 ** (bit_width - 1) - 1)
+ else:
+ min_non_scaled_val = -(2 ** (bit_width - 1))
+ bias = np.array([min_non_scaled_val], dtype=np_default_dtype)
return bias
def _calculate_thresholds(self):
@@ -326,24 +354,53 @@ class QuantReluHandler(QuantActBaseHandler):
quant_scale = self._model.get_initializer(self._q_node.input[1]).astype(
np.float32
)
- # q_inst = getCustomOp(self._q_node)
- # narrow = q_inst.get_nodeattr("narrow")
+ act_node = self._model.find_direct_predecessors(self._q_node)
+ act_node = act_node[0]
+ if act_node.op_type == "Relu":
- # Calculate thersholds, see: https://github.com/Xilinx/brevitas/blob/
- # a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/export/
- # onnx/finn/handler/act.py#L21
- num_distinct_values = 2**bit_width
- num_thresholds = int(num_distinct_values - 1)
- flat_scale = quant_scale.flatten().astype(np.float32)
- num_scale_channels = flat_scale.shape[0]
- step = np.abs(flat_scale).astype(np.float32)
- min_threshold = step / 2
- thresholds = np.empty(
- (num_scale_channels, num_thresholds), dtype=np_default_dtype
- )
- for c in range(num_scale_channels):
- for t in range(num_thresholds):
- thresholds[c][t] = min_threshold[c] + step[c] * t
+ # Calculate thersholds, see: https://github.com/Xilinx/brevitas/blob/
+ # a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/export/
+ # onnx/finn/handler/act.py#L21
+ num_distinct_values = 2**bit_width
+ num_thresholds = int(num_distinct_values - 1)
+ flat_scale = quant_scale.flatten().astype(np.float32)
+ num_scale_channels = flat_scale.shape[0]
+ step = np.abs(flat_scale).astype(np.float32)
+ min_threshold = step / 2
+ thresholds = np.empty(
+ (num_scale_channels, num_thresholds), dtype=np_default_dtype
+ )
+ for c in range(num_scale_channels):
+ for t in range(num_thresholds):
+ thresholds[c][t] = min_threshold[c] + step[c] * t
+
+ elif act_node.op_type == "Selu":
+ q_inst = getCustomOp(self._q_node)
+ narrow = q_inst.get_nodeattr("narrow")
+ if narrow:
+ num_distinct_values = 2**bit_width - 1
+ else:
+ num_distinct_values = 2**bit_width
+
+ num_thresholds = int(num_distinct_values - 1)
+ flat_scale = quant_scale.flatten().astype(np.float32)
+ num_scale_channels = flat_scale.shape[0]
+ scale = np.abs(flat_scale).astype(np.float32)
+ half_scale = scale / 2
+ # alpha and lambda
+ # from https://pytorch.org/docs/stable/generated/torch.nn.SELU.html
+ alpha = 1.6732632423543772848170429916717
+ selu_scale = 1.0507009873554804934193349852946
+ thresholds = np.empty(
+ (num_scale_channels, num_thresholds), dtype=np_default_dtype
+ )
+ for c in range(num_scale_channels):
+ for t in range(num_thresholds):
+ step = -1.0 + half_scale + scale[c] * t
+ if step <= 0:
+ thresholds[c][t] = np.log(step / (alpha * selu_scale) + 1)
+ else:
+ thresholds[c][t] = step / selu_scale
# ToDo: The index 1 needs to be changed to -1 for the channels last format
num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1]
@@ -371,10 +428,10 @@ class QuantReluHandler(QuantActBaseHandler):
"the Quant node must exist."
)
act_node = act_node[0]
- if not act_node.op_type == "Relu":
+ if act_node.op_type not in self.valid_predecessor_op_types():
raise RuntimeError(
- "The predecesor of the Quant node must be Relu for handling "
- "of Relu activations."
+ "The predecesor of the Quant node must be Relu or Selu for handling "
+ "of activations."
)
# Reroute upstream tensor
diff --git a/src/finn/util/data_packing.py b/src/finn/util/data_packing.py
index 797dad32a2cfeb3e00e224f264d91b5ee0e9247b..a41fe882e543db3f6809f0bc269b81c1e8a22ab5 100644
--- a/src/finn/util/data_packing.py
+++ b/src/finn/util/data_packing.py
@@ -220,7 +220,7 @@ def unpack_innermost_dim_from_hex_string(
if conv_dtype == DataType["BIPOLAR"]:
ar_list = [2 * x - 1 for x in ar_list]
# interpret values as signed values
- elif conv_dtype.name.startswith("INT"):
+ elif conv_dtype.signed() and conv_dtype.is_integer():
mask = 2 ** (conv_dtype.bitwidth() - 1)
ar_list = [-(x & mask) + (x & ~mask) for x in ar_list]
diff --git a/src/finn/util/gdrive.py b/src/finn/util/gdrive.py
deleted file mode 100644
index d525437300b6aee081bb073d40a517b5e3aa14be..0000000000000000000000000000000000000000
--- a/src/finn/util/gdrive.py
+++ /dev/null
@@ -1,65 +0,0 @@
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import gspread
-import os
-import warnings
-from datetime import datetime
-
-from finn.util.basic import get_finn_root
-
-
-def upload_to_end2end_dashboard(data_dict):
- gdrive_key = get_finn_root() + "/gdrive-key/service_account.json"
- if not os.path.isfile(gdrive_key):
- warnings.warn("Google Drive key not found, skipping dashboard upload")
- return
- gc = gspread.service_account(filename=gdrive_key)
- spreadsheet = gc.open("finn-end2end-dashboard")
- worksheet = spreadsheet.get_worksheet(0)
- keys = list(data_dict.keys())
- vals = list(data_dict.values())
- # check against existing header
- existing_keys = worksheet.row_values(1)
- if not set(existing_keys).issuperset(set(keys)):
- # create new worksheet
- dtstr = datetime.now().strftime("%Y-%m-%d %H:%M:%S")
- worksheet = spreadsheet.add_worksheet(
- title="Dashboard " + dtstr, rows=10, cols=len(keys), index=0
- )
- # create header row with keys
- worksheet.update("A1:1", [keys])
- # freeze and make header bold
- worksheet.freeze(rows=1)
- worksheet.format("A1:1", {"textFormat": {"bold": True}})
- # insert values into new row at appropriate positions
- worksheet.insert_row([], index=2)
- for i in range(len(keys)):
- colind = existing_keys.index(keys[i])
- col_letter = chr(ord("A") + colind)
- worksheet.update("%s2" % col_letter, vals[i])
diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py
index 8d188585694c172d97d73fa6b5820edb7b48a948..74523945242c1de68e56659087c87c349ebae4bc 100644
--- a/src/finn/util/pyverilator.py
+++ b/src/finn/util/pyverilator.py
@@ -118,6 +118,8 @@ def prepare_stitched_ip_for_verilator(model):
if not remove_entry:
filtered_verilog_files.append(vfile)
remove_entry = True
+ elif "swg_pkg" in vfile:
+ continue
else:
filtered_verilog_files.append(vfile)
@@ -315,8 +317,10 @@ def pyverilate_stitched_ip(
xpm_cdc = f"{vivado_path}/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv"
xpm_fifo = f"{vivado_path}/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv"
+ swg_pkg = os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv"
+
sim = PyVerilator.build(
- [top_module_file_name, xpm_fifo, xpm_memory, xpm_cdc],
+ [swg_pkg, top_module_file_name, xpm_fifo, xpm_memory, xpm_cdc],
verilog_path=[vivado_stitch_proj_dir, verilog_header_dir],
build_dir=build_dir,
trace_depth=get_rtlsim_trace_depth(),
diff --git a/src/finn/util/test.py b/src/finn/util/test.py
index bd8bde2820fa87ed972d699cae905d7f6cc310ff..4250079ef3e994f62a3e9f9150eb5b66371b5895 100644
--- a/src/finn/util/test.py
+++ b/src/finn/util/test.py
@@ -114,25 +114,14 @@ def get_build_env(kind, target_clk_ns):
if kind == "zynq":
ret["board"] = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
ret["part"] = pynq_part_map[ret["board"]]
- ret["ip"] = os.getenv("PYNQ_IP", "")
- ret["username"] = os.getenv("PYNQ_USERNAME", "xilinx")
- ret["password"] = os.getenv("PYNQ_PASSWORD", "xilinx")
- ret["port"] = os.getenv("PYNQ_PORT", 22)
- ret["target_dir"] = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
ret["build_fxn"] = ZynqBuild(ret["board"], target_clk_ns)
elif kind == "alveo":
ret["board"] = os.getenv("ALVEO_BOARD", default="U250")
ret["part"] = alveo_part_map[ret["board"]]
- ret["platform"] = alveo_default_platform[ret["board"]]
- ret["ip"] = os.getenv("ALVEO_IP", "")
- ret["username"] = os.getenv("ALVEO_USERNAME", "")
- ret["password"] = os.getenv("ALVEO_PASSWORD", "")
- ret["port"] = os.getenv("ALVEO_PORT", 22)
- ret["target_dir"] = os.getenv("ALVEO_TARGET_DIR", "/tmp/finn_alveo_deploy")
ret["build_fxn"] = VitisBuild(
ret["part"],
target_clk_ns,
- ret["platform"],
+ alveo_default_platform[ret["board"]],
strategy=VitisOptStrategy.BUILD_SPEED,
)
else:
diff --git a/tests/brevitas/king_charles.jpg b/tests/brevitas/king_charles.jpg
index c1400a484e686c3efe045c56e4fe02f3e0f8d17b..d3639a69e953954008284cb68cc6da1083e54710 100755
Binary files a/tests/brevitas/king_charles.jpg and b/tests/brevitas/king_charles.jpg differ
diff --git a/tests/brevitas/test_brevitas_avg_pool_export.py b/tests/brevitas/test_brevitas_avg_pool_export.py
index 669601ecb6ebfd6758d3382ab097a1e93dc848c7..9550031b326b8002c74b943529ba24a193e26a5d 100644
--- a/tests/brevitas/test_brevitas_avg_pool_export.py
+++ b/tests/brevitas/test_brevitas_avg_pool_export.py
@@ -30,10 +30,8 @@ import pytest
import numpy as np
import os
import torch
-from brevitas.export import FINNManager
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
-from brevitas.nn import QuantAvgPool2d
-from brevitas.quant_tensor import QuantTensor
+from brevitas.export import export_qonnx
+from brevitas.nn import QuantAvgPool2d, QuantIdentity, QuantReLU
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.infer_datatypes import InferDataTypes
@@ -48,10 +46,9 @@ base_export_onnx_path = "test_brevitas_avg_pool_export.onnx"
@pytest.mark.brevitas_export
-@pytest.mark.parametrize("QONNX_export", [False, True])
@pytest.mark.parametrize("kernel_size", [2, 3])
@pytest.mark.parametrize("stride", [1, 2])
-@pytest.mark.parametrize("signed", [True, False])
+@pytest.mark.parametrize("signed", [True]) # TODO: Add unsigned test case
@pytest.mark.parametrize("bit_width", [2, 4])
@pytest.mark.parametrize("input_bit_width", [4, 8, 16])
@pytest.mark.parametrize("channels", [2, 4])
@@ -64,79 +61,56 @@ def test_brevitas_avg_pool_export(
input_bit_width,
channels,
idim,
- QONNX_export,
):
- export_onnx_path = base_export_onnx_path.replace(
- ".onnx", f"test_QONNX-{QONNX_export}.onnx"
- )
+ export_onnx_path = base_export_onnx_path.replace(".onnx", "test_QONNX.onnx")
+ if signed:
+ quant_node = QuantIdentity(
+ bit_width=input_bit_width,
+ return_quant_tensor=True,
+ )
+ else:
+ quant_node = QuantReLU(
+ bit_width=input_bit_width,
+ return_quant_tensor=True,
+ )
quant_avgpool = QuantAvgPool2d(
kernel_size=kernel_size,
stride=stride,
bit_width=bit_width,
return_quant_tensor=False,
+ float_to_int_impl_type="FLOOR",
)
- quant_avgpool.eval()
+ model_brevitas = torch.nn.Sequential(quant_node, quant_avgpool)
+ model_brevitas.eval()
# determine input
- prefix = "INT" if signed else "UINT"
- dt_name = prefix + str(input_bit_width)
- dtype = DataType[dt_name]
input_shape = (1, channels, idim, idim)
- input_array = gen_finn_dt_tensor(dtype, input_shape)
- # Brevitas QuantAvgPool layers need QuantTensors to export correctly
- # which requires setting up a QuantTensor instance with the scale
- # factor, zero point, bitwidth and signedness
- scale_array = np.ones((1, channels, 1, 1)).astype(np.float32)
- scale_array *= 0.5
- input_tensor = torch.from_numpy(input_array * scale_array).float()
- scale_tensor = torch.from_numpy(scale_array).float()
- zp = torch.tensor(0.0)
- input_quant_tensor = QuantTensor(
- input_tensor, scale_tensor, zp, input_bit_width, signed, training=False
- )
+ input_array = gen_finn_dt_tensor(DataType["FLOAT32"], input_shape)
- # export
- if QONNX_export:
- BrevitasONNXManager.export(
- quant_avgpool,
- export_path=export_onnx_path,
- input_t=input_quant_tensor,
- )
- model = ModelWrapper(export_onnx_path)
+ input_tensor = torch.from_numpy(input_array).float()
- # Statically set the additional inputs generated by the BrevitasONNXManager
- model.graph.input.remove(model.graph.input[3])
- model.graph.input.remove(model.graph.input[2])
- model.graph.input.remove(model.graph.input[1])
- model.set_initializer("1", scale_array)
- model.set_initializer("2", np.array(0.0).astype(np.float32))
- model.set_initializer("3", np.array(input_bit_width).astype(np.float32))
- model.save(export_onnx_path)
+ # export
+ export_qonnx(
+ model_brevitas,
+ export_path=export_onnx_path,
+ input_t=input_tensor,
+ )
+ model = ModelWrapper(export_onnx_path)
+ model.save(export_onnx_path)
- qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)
- model = ModelWrapper(export_onnx_path)
- model = model.transform(ConvertQONNXtoFINN())
- model.save(export_onnx_path)
- else:
- FINNManager.export(
- quant_avgpool, export_path=export_onnx_path, input_t=input_quant_tensor
- )
+ qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)
model = ModelWrapper(export_onnx_path)
+ model = model.transform(ConvertQONNXtoFINN())
model = model.transform(InferShapes())
model = model.transform(InferDataTypes())
# reference brevitas output
- ref_output_array = quant_avgpool(input_quant_tensor).detach().numpy()
+ ref_output_array = model_brevitas(input_tensor).detach().numpy()
# finn output
- if QONNX_export:
- # Manually apply the Quant tensor scaling for QONNX
- idict = {model.graph.input[0].name: input_array * scale_array}
- else:
- idict = {model.graph.input[0].name: input_array}
+ idict = {model.graph.input[0].name: input_array}
odict = oxe.execute_onnx(model, idict, True)
finn_output = odict[model.graph.output[0].name]
# compare outputs
assert np.isclose(ref_output_array, finn_output).all()
# cleanup
- # assert False
os.remove(export_onnx_path)
diff --git a/tests/brevitas/test_brevitas_cnv.py b/tests/brevitas/test_brevitas_cnv.py
index 62aab2e3c2b85c6462c24194c917bdc2d8eec448..1a96815105b70a9bc58d51a8214c15bbc09aa69c 100644
--- a/tests/brevitas/test_brevitas_cnv.py
+++ b/tests/brevitas/test_brevitas_cnv.py
@@ -30,11 +30,10 @@ import pkg_resources as pk
import pytest
-import brevitas.onnx as bo
import numpy as np
import os
import torch
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
from qonnx.transformation.general import GiveUniqueNodeNames, RemoveStaticGraphInputs
@@ -58,13 +57,13 @@ def test_brevitas_cnv_export_exec(wbits, abits, QONNX_export):
cnv = get_test_model_trained("CNV", wbits, abits)
ishape = (1, 3, 32, 32)
if QONNX_export:
- BrevitasONNXManager.export(cnv, ishape, export_onnx_path)
+ export_qonnx(cnv, torch.randn(ishape), export_onnx_path)
qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(ConvertQONNXtoFINN())
model.save(export_onnx_path)
else:
- bo.export_finn_onnx(cnv, ishape, export_onnx_path)
+ export_finn_onnx(cnv, torch.randn(ishape), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(GiveUniqueNodeNames())
model = model.transform(InferShapes())
diff --git a/tests/brevitas/test_brevitas_debug.py b/tests/brevitas/test_brevitas_debug.py
index 181d610fff7a703a8ccbcf3bbb19bed2e5d7e89d..547c026e2174e1b46a0e72967076f32db73b18a5 100644
--- a/tests/brevitas/test_brevitas_debug.py
+++ b/tests/brevitas/test_brevitas_debug.py
@@ -34,7 +34,7 @@ import onnx
import onnx.numpy_helper as nph
import os
import torch
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from pkgutil import get_data
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
@@ -58,7 +58,7 @@ def test_brevitas_debug(QONNX_export, QONNX_FINN_conversion):
ishape = (1, 1, 28, 28)
if QONNX_export:
dbg_hook = bo.enable_debug(fc, proxy_level=True)
- BrevitasONNXManager.export(fc, ishape, finn_onnx)
+ export_qonnx(fc, torch.randn(ishape), finn_onnx)
# DebugMarkers have the brevitas.onnx domain, so that needs adjusting
model = ModelWrapper(finn_onnx)
dbg_nodes = model.get_nodes_by_op_type("DebugMarker")
@@ -72,7 +72,7 @@ def test_brevitas_debug(QONNX_export, QONNX_FINN_conversion):
model.save(finn_onnx)
else:
dbg_hook = bo.enable_debug(fc)
- bo.export_finn_onnx(fc, ishape, finn_onnx)
+ export_finn_onnx(fc, torch.randn(ishape), finn_onnx)
model = ModelWrapper(finn_onnx)
# DebugMarkers have the brevitas.onnx domain, so that needs adjusting
# ToDo: We should probably have transformation pass, which does this
diff --git a/tests/brevitas/test_brevitas_fc.py b/tests/brevitas/test_brevitas_fc.py
index 211fdb629b7c0465a145a094bab428064227afc9..3aaa96f9a5f74112cdfe2a90c425eec55661a3b1 100644
--- a/tests/brevitas/test_brevitas_fc.py
+++ b/tests/brevitas/test_brevitas_fc.py
@@ -28,12 +28,11 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import onnx
import onnx.numpy_helper as nph
import torch
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from pkgutil import get_data
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
@@ -68,13 +67,13 @@ def test_brevitas_fc_onnx_export_and_exec(size, wbits, abits, QONNX_export):
fc = get_test_model_trained(size, wbits, abits)
ishape = (1, 1, 28, 28)
if QONNX_export:
- BrevitasONNXManager.export(fc, ishape, finn_onnx)
+ export_qonnx(fc, torch.randn(ishape), finn_onnx)
qonnx_cleanup(finn_onnx, out_file=finn_onnx)
model = ModelWrapper(finn_onnx)
model = model.transform(ConvertQONNXtoFINN())
model.save(finn_onnx)
else:
- bo.export_finn_onnx(fc, ishape, finn_onnx)
+ export_finn_onnx(fc, torch.randn(ishape), finn_onnx)
model = ModelWrapper(finn_onnx)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/brevitas/test_brevitas_mobilenet.py b/tests/brevitas/test_brevitas_mobilenet.py
index b1475b6f4ec8c4a6ed34b4249b961031780d4be8..b469b197fa7b86db32c6ea9a79485c3794b8b3c4 100644
--- a/tests/brevitas/test_brevitas_mobilenet.py
+++ b/tests/brevitas/test_brevitas_mobilenet.py
@@ -28,9 +28,9 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import torch
+from brevitas.export import export_finn_onnx
from PIL import Image
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
@@ -76,7 +76,7 @@ def test_brevitas_mobilenet():
std = 0.226
ch = 3
preproc = NormalizePreProc(mean, std, ch)
- bo.export_finn_onnx(preproc, (1, 3, 224, 224), preproc_onnx)
+ export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx)
preproc_model = ModelWrapper(preproc_onnx)
# set input finn datatype to UINT8
preproc_model.set_tensor_datatype(
@@ -89,7 +89,7 @@ def test_brevitas_mobilenet():
finn_onnx = export_onnx_path + "/quant_mobilenet_v1_4b_exported.onnx"
mobilenet = get_test_model_trained("mobilenet", 4, 4)
- bo.export_finn_onnx(mobilenet, (1, 3, 224, 224), finn_onnx)
+ export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx)
# do forward pass in PyTorch/Brevitas
input_tensor = preproc.forward(img_torch)
@@ -121,4 +121,6 @@ def test_brevitas_mobilenet():
produced = odict[model.graph.output[0].name]
produced_prob = odict["TopK_0_out0"] * a0
assert (produced.flatten() == expected_top5).all()
- assert np.isclose(produced_prob.flatten(), expected_top5_prob).all()
+ assert np.isclose(
+ produced_prob.flatten(), expected_top5_prob, atol=2.2 * 1e-1
+ ).all()
diff --git a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py
index 5d70acb10264dc10a3681589075507f06a9c903b..ad6a7e53de993b76f5b35dadd4e257c8bd88f4de 100644
--- a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py
+++ b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py
@@ -28,7 +28,6 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import onnx # noqa
import os
@@ -36,7 +35,7 @@ import torch
from brevitas.core.quant import QuantType
from brevitas.core.restrict_val import RestrictValueType
from brevitas.core.scaling import ScalingImplType
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from brevitas.nn import QuantHardTanh
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.infer_shapes import InferShapes
@@ -78,13 +77,13 @@ def test_brevitas_act_export_qhardtanh_nonscaled(
)
if QONNX_export:
m_path = export_onnx_path
- BrevitasONNXManager.export(b_act, ishape, m_path)
+ export_qonnx(b_act, torch.randn(ishape), m_path)
qonnx_cleanup(m_path, out_file=m_path)
model = ModelWrapper(m_path)
model = model.transform(ConvertQONNXtoFINN())
model.save(m_path)
else:
- bo.export_finn_onnx(b_act, ishape, export_onnx_path)
+ export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(
diff --git a/tests/brevitas/test_brevitas_qconv2d.py b/tests/brevitas/test_brevitas_qconv2d.py
index 214c55e5fd8b8c25c1ccca880f76690556af6397..faeb3ff48e2d7157008a87eab544766c83dc37d2 100644
--- a/tests/brevitas/test_brevitas_qconv2d.py
+++ b/tests/brevitas/test_brevitas_qconv2d.py
@@ -28,7 +28,6 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import os
import torch
@@ -36,7 +35,7 @@ from brevitas.core.quant import QuantType
from brevitas.core.restrict_val import RestrictValueType
from brevitas.core.scaling import ScalingImplType
from brevitas.core.stats import StatsOp
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from brevitas.nn import QuantConv2d
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
@@ -96,13 +95,13 @@ def test_brevitas_QConv2d(dw, bias, in_channels, QONNX_export):
b_conv.eval()
if QONNX_export:
m_path = export_onnx_path
- BrevitasONNXManager.export(b_conv, ishape, m_path)
+ export_qonnx(b_conv, torch.randn(ishape), m_path)
qonnx_cleanup(m_path, out_file=m_path)
model = ModelWrapper(m_path)
model = model.transform(ConvertQONNXtoFINN())
model.save(m_path)
else:
- bo.export_finn_onnx(b_conv, ishape, export_onnx_path)
+ export_finn_onnx(b_conv, torch.randn(ishape), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
inp_tensor = np.random.uniform(low=-1.0, high=1.0, size=ishape).astype(np.float32)
diff --git a/tests/brevitas/test_brevitas_qlinear.py b/tests/brevitas/test_brevitas_qlinear.py
index bcd75a545544122c1faacf4c321b19a489defe85..1ad52fb5df9fff6584fb6b649481377f32fa666d 100644
--- a/tests/brevitas/test_brevitas_qlinear.py
+++ b/tests/brevitas/test_brevitas_qlinear.py
@@ -28,12 +28,11 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import os
import torch
from brevitas.core.quant import QuantType
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from brevitas.nn import QuantLinear
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
@@ -75,13 +74,13 @@ def test_brevitas_qlinear(
b_linear.eval()
if QONNX_export:
m_path = export_onnx_path
- BrevitasONNXManager.export(b_linear, i_shape, m_path)
+ export_qonnx(b_linear, torch.randn(i_shape), m_path)
qonnx_cleanup(m_path, out_file=m_path)
model = ModelWrapper(m_path)
model = model.transform(ConvertQONNXtoFINN())
model.save(m_path)
else:
- bo.export_finn_onnx(b_linear, i_shape, export_onnx_path)
+ export_finn_onnx(b_linear, torch.randn(i_shape), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
inp_tensor = gen_finn_dt_tensor(i_dtype, i_shape)
diff --git a/tests/brevitas/test_brevitas_relu_act_export.py b/tests/brevitas/test_brevitas_relu_act_export.py
index 3dc46ec31e49d7115b19b3373d54be6ddc29bb80..a4657d79248c00227c12e9c2bdf7453dfc49706a 100644
--- a/tests/brevitas/test_brevitas_relu_act_export.py
+++ b/tests/brevitas/test_brevitas_relu_act_export.py
@@ -28,20 +28,16 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import onnx # noqa
import os
import torch
-from brevitas.core.quant import QuantType
-from brevitas.core.restrict_val import RestrictValueType
from brevitas.core.scaling import ScalingImplType
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from brevitas.nn import QuantReLU
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.infer_shapes import InferShapes
from qonnx.util.cleanup import cleanup as qonnx_cleanup
-from torch import nn
import finn.core.onnx_exec as oxe
from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN
@@ -51,63 +47,35 @@ export_onnx_path = "test_brevitas_relu_act_export.onnx"
@pytest.mark.brevitas_export
@pytest.mark.parametrize("abits", [2, 4, 8])
-@pytest.mark.parametrize("max_val", [1.0, 1.5, 1 - 2 ** (-7)])
-@pytest.mark.parametrize(
- "scaling_impl_type", [ScalingImplType.CONST, ScalingImplType.PARAMETER]
-)
+@pytest.mark.parametrize("ishape", [(1, 15), (1, 32, 1, 1)])
@pytest.mark.parametrize("QONNX_export", [False, True])
-def test_brevitas_act_export_relu(abits, max_val, scaling_impl_type, QONNX_export):
- min_val = -1.0
- ishape = (1, 15)
+def test_brevitas_act_export_relu(
+ abits,
+ ishape,
+ QONNX_export,
+):
b_act = QuantReLU(
bit_width=abits,
- max_val=max_val,
- scaling_impl_type=scaling_impl_type,
- restrict_scaling_type=RestrictValueType.LOG_FP,
- quant_type=QuantType.INT,
)
- if scaling_impl_type == ScalingImplType.PARAMETER:
- checkpoint = {
- "act_quant_proxy.fused_activation_quant_proxy.tensor_quant.\
-scaling_impl.learned_value": torch.tensor(
- 0.49
- ).type(
- torch.FloatTensor
- )
- }
- b_act.load_state_dict(checkpoint)
if QONNX_export:
m_path = export_onnx_path
- BrevitasONNXManager.export(b_act, ishape, m_path)
+ export_qonnx(b_act, torch.randn(ishape), m_path)
qonnx_cleanup(m_path, out_file=m_path)
model = ModelWrapper(m_path)
model = model.transform(ConvertQONNXtoFINN())
model.save(m_path)
else:
- bo.export_finn_onnx(b_act, ishape, export_onnx_path)
+ export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
- inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(
- np.float32
- )
+ inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32)
idict = {model.graph.input[0].name: inp_tensor}
odict = oxe.execute_onnx(model, idict, True)
produced = odict[model.graph.output[0].name]
inp_tensor = torch.from_numpy(inp_tensor).float()
b_act.eval()
expected = b_act.forward(inp_tensor).detach().numpy()
- if not np.isclose(produced, expected, atol=1e-3).all():
- print(abits, max_val, scaling_impl_type)
- print("scale: ", b_act.quant_act_scale().type(torch.FloatTensor).detach())
- if abits < 5:
- print(
- "thres:",
- ", ".join(["{:8.4f}".format(x) for x in b_act.export_thres[0]]),
- )
- print("input:", ", ".join(["{:8.4f}".format(x) for x in inp_tensor[0]]))
- print("prod :", ", ".join(["{:8.4f}".format(x) for x in produced[0]]))
- print("expec:", ", ".join(["{:8.4f}".format(x) for x in expected[0]]))
assert np.isclose(produced, expected, atol=1e-3).all()
os.remove(export_onnx_path)
@@ -115,148 +83,40 @@ scaling_impl.learned_value": torch.tensor(
@pytest.mark.brevitas_export
@pytest.mark.parametrize("abits", [2, 4, 8])
-@pytest.mark.parametrize("max_val", [1.0, 1.5, 1 - 2 ** (-7)])
-@pytest.mark.parametrize("scaling_per_channel", [True, False])
+@pytest.mark.parametrize("ishape", [(1, 15, 4, 4), (1, 32, 1, 1)])
@pytest.mark.parametrize("QONNX_export", [False, True])
-def test_brevitas_act_export_relu_imagenet(
- abits, max_val, scaling_per_channel, QONNX_export
+def test_brevitas_act_export_relu_channel(
+ abits,
+ ishape,
+ QONNX_export,
):
- out_channels = 32
- ishape = (1, out_channels, 1, 1)
- min_val = -1.0
+
+ ch = ishape[1]
b_act = QuantReLU(
bit_width=abits,
- quant_type=QuantType.INT,
- scaling_impl_type=ScalingImplType.PARAMETER,
- scaling_per_channel=scaling_per_channel,
- restrict_scaling_type=RestrictValueType.LOG_FP,
- scaling_min_val=2e-16,
max_val=6.0,
- return_quant_tensor=False,
- per_channel_broadcastable_shape=(1, out_channels, 1, 1),
+ scaling_impl_type=ScalingImplType.CONST,
+ scaling_per_output_channel=True,
+ per_channel_broadcastable_shape=(1, ch, 1, 1),
)
- if scaling_per_channel is True:
- rand_tensor = (2) * torch.rand((1, out_channels, 1, 1))
- else:
- rand_tensor = torch.tensor(1.2398)
- checkpoint = {
- "act_quant_proxy.fused_activation_quant_proxy.tensor_quant.\
-scaling_impl.learned_value": rand_tensor.type(
- torch.FloatTensor
- )
- }
- b_act.load_state_dict(checkpoint)
if QONNX_export:
m_path = export_onnx_path
- BrevitasONNXManager.export(b_act, ishape, m_path)
+ export_qonnx(b_act, torch.randn(ishape), m_path)
qonnx_cleanup(m_path, out_file=m_path)
model = ModelWrapper(m_path)
model = model.transform(ConvertQONNXtoFINN())
model.save(m_path)
else:
- bo.export_finn_onnx(b_act, ishape, export_onnx_path)
+ export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
- inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(
- np.float32
- )
+ inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32)
idict = {model.graph.input[0].name: inp_tensor}
odict = oxe.execute_onnx(model, idict, True)
produced = odict[model.graph.output[0].name]
inp_tensor = torch.from_numpy(inp_tensor).float()
b_act.eval()
expected = b_act.forward(inp_tensor).detach().numpy()
- if not np.isclose(produced, expected, atol=1e-3).all():
- print(abits, max_val)
- print("scale: ", b_act.quant_act_scale().type(torch.FloatTensor).detach())
- if abits < 5:
- print(
- "thres:",
- ", ".join(["{:8.4f}".format(x) for x in b_act.export_thres[0]]),
- )
- print("input:", ", ".join(["{:8.4f}".format(x) for x in inp_tensor[0]]))
- print("prod :", ", ".join(["{:8.4f}".format(x) for x in produced[0]]))
- print("expec:", ", ".join(["{:8.4f}".format(x) for x in expected[0]]))
-
- assert np.isclose(produced, expected, atol=1e-3).all()
- os.remove(export_onnx_path)
-
-
-class PyTorchTestModel(nn.Module):
- def __init__(self, abits):
- super(PyTorchTestModel, self).__init__()
- out_channels = 32
- self.b_act = QuantReLU(
- bit_width=abits,
- quant_type=QuantType.INT,
- scaling_impl_type=ScalingImplType.PARAMETER,
- scaling_per_channel=True,
- restrict_scaling_type=RestrictValueType.LOG_FP,
- scaling_min_val=2e-16,
- max_val=6.0,
- return_quant_tensor=False,
- per_channel_broadcastable_shape=(1, out_channels, 1, 1),
- )
-
- def forward(self, x):
- act_out = self.b_act(x)
- y0 = act_out * 2.0
- y1 = act_out * -1.0
- y = y0 + y1
- return y
-
-
-@pytest.mark.brevitas_export
-@pytest.mark.parametrize("abits", [2, 4, 8])
-@pytest.mark.parametrize("max_val", [1.0, 1.5, 1 - 2 ** (-7)])
-@pytest.mark.parametrize("scaling_per_channel", [True])
-@pytest.mark.parametrize("QONNX_export", [True])
-def test_brevitas_act_export_relu_forking(
- abits, max_val, scaling_per_channel, QONNX_export
-):
- out_channels = 32
- ishape = (1, out_channels, 1, 1)
- min_val = -1.0
- model_pyt = PyTorchTestModel(abits)
-
- rand_tensor = (2) * torch.rand((1, out_channels, 1, 1))
-
- checkpoint = {
- "b_act.act_quant_proxy.fused_activation_quant_proxy."
- "tensor_quant.scaling_impl.learned_value": rand_tensor.type(torch.FloatTensor)
- }
- model_pyt.load_state_dict(checkpoint)
-
- if QONNX_export:
- m_path = export_onnx_path
- BrevitasONNXManager.export(model_pyt, ishape, m_path)
- qonnx_cleanup(m_path, out_file=m_path)
- model = ModelWrapper(m_path)
- model = model.transform(ConvertQONNXtoFINN())
- model.save(m_path)
-
- model = ModelWrapper(export_onnx_path)
- model = model.transform(InferShapes())
- inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(
- np.float32
- )
- idict = {model.graph.input[0].name: inp_tensor}
- odict = oxe.execute_onnx(model, idict, True)
- produced = odict[model.graph.output[0].name]
- inp_tensor = torch.from_numpy(inp_tensor).float()
- model_pyt.eval()
- expected = model_pyt.forward(inp_tensor).detach().numpy()
- if not np.isclose(produced, expected, atol=1e-3).all():
- print(abits, max_val)
- print("scale: ", model_pyt.quant_act_scale().type(torch.FloatTensor).detach())
- if abits < 5:
- print(
- "thres:",
- ", ".join(["{:8.4f}".format(x) for x in model_pyt.export_thres[0]]),
- )
- print("input:", ", ".join(["{:8.4f}".format(x) for x in inp_tensor[0]]))
- print("prod :", ", ".join(["{:8.4f}".format(x) for x in produced[0]]))
- print("expec:", ", ".join(["{:8.4f}".format(x) for x in expected[0]]))
assert np.isclose(produced, expected, atol=1e-3).all()
os.remove(export_onnx_path)
diff --git a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py
index 403d406105e8e60e6ef87f833c495dc2974de68c..d35cc8d2dda58f2be188622cdac59c19cee25e13 100644
--- a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py
+++ b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py
@@ -28,7 +28,6 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import onnx # noqa
import os
@@ -36,7 +35,7 @@ import torch
from brevitas.core.quant import QuantType
from brevitas.core.restrict_val import RestrictValueType
from brevitas.core.scaling import ScalingImplType
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from brevitas.nn import QuantHardTanh
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.infer_shapes import InferShapes
@@ -91,13 +90,13 @@ tensor_quant.scaling_impl.learned_value": torch.tensor(
b_act.load_state_dict(checkpoint)
if QONNX_export:
m_path = export_onnx_path
- BrevitasONNXManager.export(b_act, ishape, m_path)
+ export_qonnx(b_act, torch.randn(ishape), m_path)
qonnx_cleanup(m_path, out_file=m_path)
model = ModelWrapper(m_path)
model = model.transform(ConvertQONNXtoFINN())
model.save(m_path)
else:
- bo.export_finn_onnx(b_act, ishape, export_onnx_path)
+ export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(
diff --git a/tests/brevitas/test_brevitas_selu_act_export.py b/tests/brevitas/test_brevitas_selu_act_export.py
new file mode 100644
index 0000000000000000000000000000000000000000..3f4807c5d7286c265a856d73e9aaa886f342555e
--- /dev/null
+++ b/tests/brevitas/test_brevitas_selu_act_export.py
@@ -0,0 +1,74 @@
+# Copyright (c) 2023, Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of Xilinx nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import pytest
+
+import numpy as np
+import onnx # noqa
+import os
+import torch
+from brevitas.export import export_qonnx
+from brevitas.nn import QuantIdentity
+from qonnx.core.modelwrapper import ModelWrapper
+from qonnx.util.basic import get_preferred_onnx_opset
+from qonnx.util.cleanup import cleanup as qonnx_cleanup
+
+import finn.core.onnx_exec as oxe
+from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN
+
+
+@pytest.mark.brevitas_export
+@pytest.mark.parametrize("abits", [2, 4, 8])
+@pytest.mark.parametrize("ishape", [(1, 15), (1, 32, 1, 1)])
+@pytest.mark.parametrize("narrow", [True, False])
+def test_brevitas_act_export_selu(abits, ishape, narrow):
+ export_path = "test_brevitas_selu_act_export_%s.onnx" % str(abits)
+ b_act = torch.nn.Sequential(
+ torch.nn.SELU(), QuantIdentity(bit_width=abits, narrow=narrow)
+ )
+
+ export_qonnx(
+ b_act,
+ torch.randn(ishape),
+ export_path,
+ opset_version=get_preferred_onnx_opset(),
+ )
+ qonnx_cleanup(export_path, out_file=export_path)
+ model = ModelWrapper(export_path)
+ model = model.transform(ConvertQONNXtoFINN())
+
+ inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32)
+ idict = {model.graph.input[0].name: inp_tensor}
+ odict = oxe.execute_onnx(model, idict, True)
+ produced = odict[model.graph.output[0].name]
+ inp_tensor = torch.from_numpy(inp_tensor).float()
+ b_act.eval()
+ expected = b_act.forward(inp_tensor).detach().numpy()
+
+ assert np.isclose(produced, expected, atol=1e-3).all()
+ os.remove(export_path)
diff --git a/tests/brevitas/test_brevitas_validate_mobilenet.py b/tests/brevitas/test_brevitas_validate_mobilenet.py
index 55915838e8a10d19d3aa6446d0bb667785bbd905..20e8ddad501e8b07502decef6eacd4afe061917a 100644
--- a/tests/brevitas/test_brevitas_validate_mobilenet.py
+++ b/tests/brevitas/test_brevitas_validate_mobilenet.py
@@ -35,6 +35,7 @@ import os
import torch
import torchvision.datasets as datasets
import torchvision.transforms as transforms
+from brevitas.export import export_finn_onnx
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
from qonnx.transformation.general import (
@@ -113,7 +114,7 @@ def test_brevitas_compare_exported_mobilenet():
# export preprocessing
preproc_onnx = export_onnx_path + "/quant_mobilenet_v1_4b_preproc.onnx"
preproc = NormalizePreProc(mean, std, ch)
- bo.export_finn_onnx(preproc, (1, 3, 224, 224), preproc_onnx)
+ export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx)
preproc_model = ModelWrapper(preproc_onnx)
preproc_model = preproc_model.transform(InferShapes())
preproc_model = preproc_model.transform(GiveUniqueNodeNames())
@@ -124,7 +125,7 @@ def test_brevitas_compare_exported_mobilenet():
mobilenet = get_test_model_trained("mobilenet", 4, 4)
if debug_mode:
dbg_hook = bo.enable_debug(mobilenet)
- bo.export_finn_onnx(mobilenet, (1, 3, 224, 224), finn_onnx)
+ export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx)
model = ModelWrapper(finn_onnx)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py
index 858363d6d31c7c17803bffdb87e7b168dec4b76d..27aaa1986df15b4d6f51462679b1f8e7179684cb 100644
--- a/tests/end2end/test_end2end_bnn_pynq.py
+++ b/tests/end2end/test_end2end_bnn_pynq.py
@@ -28,20 +28,16 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
# as of Feb'20 there is a bug that segfaults ONNX shape inference if we
# import pytorch before onnx, so we make sure to import onnx first
import onnx # NOQA
import os
-import subprocess
import torch
import warnings
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
-from collections import OrderedDict
+from brevitas.export import export_finn_onnx, export_qonnx
from dataset_loading import cifar, mnist
-from datetime import datetime
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.custom_op.registry import getCustomOp
@@ -60,13 +56,12 @@ from qonnx.transformation.insert_topk import InsertTopK
from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul
from qonnx.transformation.merge_onnx_models import MergeONNXModels
from qonnx.util.cleanup import cleanup as qonnx_cleanup
-from scipy.stats import linregress
import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls
import finn.transformation.streamline.absorb as absorb
from finn.analysis.fpgadataflow.dataflow_performance import dataflow_performance
from finn.core.onnx_exec import execute_onnx
-from finn.core.throughput_test import throughput_test_remote, throughput_test_rtlsim
+from finn.core.throughput_test import throughput_test_rtlsim
from finn.transformation.fpgadataflow.annotate_cycles import AnnotateCycles
from finn.transformation.fpgadataflow.annotate_resources import AnnotateResources
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
@@ -76,8 +71,13 @@ from finn.transformation.fpgadataflow.create_dataflow_partition import (
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
-from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
+from finn.transformation.fpgadataflow.minimize_accumulator_width import (
+ MinimizeAccumulatorWidth,
+)
+from finn.transformation.fpgadataflow.minimize_weight_bit_width import (
+ MinimizeWeightBitWidth,
+)
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
@@ -90,7 +90,6 @@ from finn.transformation.streamline.reorder import (
MoveScalarLinearPastInvariants,
)
from finn.util.basic import get_finn_root
-from finn.util.gdrive import upload_to_end2end_dashboard
from finn.util.pytorch import ToTensor
from finn.util.test import (
execute_parent,
@@ -117,24 +116,6 @@ def get_checkpoint_name(topology, wbits, abits, QONNX_export, step):
)
-def get_dashboard_data(topology, wbits, abits):
- stats_file = build_dir + "/end2end_%s_w%da%d.txt" % (topology, wbits, abits)
- stats_dict = OrderedDict()
- if os.path.isfile(stats_file):
- with open(stats_file, "r") as f:
- stats_dict_txt = f.read()
- stats_dict = eval(stats_dict_txt)
- return stats_dict
-
-
-def update_dashboard_data(topology, wbits, abits, key, val):
- stats_dict = get_dashboard_data(topology, wbits, abits)
- stats_dict[key] = val
- stats_file = build_dir + "/end2end_%s_w%da%d.txt" % (topology, wbits, abits)
- with open(stats_file, "w") as f:
- f.write(str(stats_dict))
-
-
def fold_tfc(model):
fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation")
# (PE, SIMD, ramstyle) for each layer
@@ -269,7 +250,7 @@ def measure_top1_accuracy(model_chkpt, dataset, parent_chkpt=None):
raise Exception("Unrecognized dataset")
# move from dataset_loader layout to ONNX layout: NHWC -> NCHW
testx = testx.transpose(0, 3, 1, 2)
- model = ModelWrapper(model_chkpt)
+ model = load_test_checkpoint_or_skip(model_chkpt)
iname = model.graph.input[0].name
oname = model.graph.output[0].name
if parent_chkpt is None:
@@ -323,22 +304,13 @@ class TestEnd2End:
(model, ishape) = get_trained_network_and_ishape(topology, wbits, abits)
chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "export")
if QONNX_export:
- BrevitasONNXManager.export(model, ishape, chkpt_name)
+ export_qonnx(model, torch.randn(ishape), chkpt_name)
qonnx_cleanup(chkpt_name, out_file=chkpt_name)
model = ModelWrapper(chkpt_name)
model = model.transform(ConvertQONNXtoFINN())
model.save(chkpt_name)
else:
- bo.export_finn_onnx(model, ishape, chkpt_name)
- nname = "%s_w%da%d" % (topology, wbits, abits)
- update_dashboard_data(topology, wbits, abits, "network", nname)
- dtstr = datetime.now().strftime("%Y-%m-%d %H:%M:%S")
- update_dashboard_data(topology, wbits, abits, "datetime", dtstr)
- finn_commit = subprocess.check_output(
- ["git", "rev-parse", "HEAD"], cwd=get_finn_root()
- )
- finn_commit = finn_commit.decode("utf-8").strip()
- update_dashboard_data(topology, wbits, abits, "finn-commit", finn_commit)
+ export_finn_onnx(model, torch.randn(ishape), chkpt_name)
assert os.path.isfile(chkpt_name)
def test_import_and_tidy(self, topology, wbits, abits, QONNX_export):
@@ -369,7 +341,7 @@ class TestEnd2End:
chkpt_preproc_name = get_checkpoint_name(
topology, wbits, abits, QONNX_export, "preproc"
)
- bo.export_finn_onnx(totensor_pyt, ishape, chkpt_preproc_name)
+ export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)
assert os.path.isfile(chkpt_preproc_name)
# join preprocessing and core model
pre_model = ModelWrapper(chkpt_preproc_name)
@@ -511,11 +483,23 @@ class TestEnd2End:
model = folding_fxn(model)
model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold"))
+ def test_minimize_bit_width(self, topology, wbits, abits, QONNX_export):
+ prev_chkpt_name = get_checkpoint_name(
+ topology, wbits, abits, QONNX_export, "fold"
+ )
+ model = load_test_checkpoint_or_skip(prev_chkpt_name)
+ model = model.transform(MinimizeAccumulatorWidth())
+ model = model.transform(MinimizeWeightBitWidth())
+ curr_chkpt_name = get_checkpoint_name(
+ topology, wbits, abits, QONNX_export, "minimize_bit_width"
+ )
+ model.save(curr_chkpt_name)
+
@pytest.mark.slow
@pytest.mark.vivado
def test_cppsim(self, topology, wbits, abits, QONNX_export):
prev_chkpt_name = get_checkpoint_name(
- topology, wbits, abits, QONNX_export, "fold"
+ topology, wbits, abits, QONNX_export, "minimize_bit_width"
)
model = load_test_checkpoint_or_skip(prev_chkpt_name)
model = model.transform(PrepareCppSim())
@@ -627,10 +611,6 @@ class TestEnd2End:
ret = throughput_test_rtlsim(model, batchsize=batchsize)
res_cycles = ret["cycles"]
est_cycles = latency + cycles_per_sample_est * batchsize
- # warnings.warn("Estimated & rtlsim performance: " + str(perf))
- # for (k, v) in perf.items():
- # update_dashboard_data(topology, wbits, abits, k, v)
- update_dashboard_data(topology, wbits, abits, "cycles_rtlsim", latency)
assert (abs(res_cycles - est_cycles) / res_cycles) < 0.15
@pytest.mark.slow
@@ -674,10 +654,6 @@ class TestEnd2End:
cfg = get_build_env(kind, target_clk_ns)
model = model.transform(cfg["build_fxn"])
model = model.transform(AnnotateResources("synth"))
- synth_dct = eval(model.get_metadata_prop("res_total_top_synth"))
- for (k, v) in synth_dct.items():
- update_dashboard_data(topology, wbits, abits, k, v)
- update_dashboard_data(topology, wbits, abits, "board", cfg["board"])
model.save(
get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind)
)
@@ -698,121 +674,3 @@ class TestEnd2End:
model.save(
get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + kind)
)
-
- @pytest.mark.parametrize("kind", ["zynq", "alveo"])
- def test_deploy(self, topology, wbits, abits, QONNX_export, kind):
- prev_chkpt_name = get_checkpoint_name(
- topology, wbits, abits, QONNX_export, "driver_" + kind
- )
- model = load_test_checkpoint_or_skip(prev_chkpt_name)
- cfg = get_build_env(kind, target_clk_ns)
- if cfg["ip"] == "":
- pytest.skip("PYNQ board IP address not specified")
- model = model.transform(
- DeployToPYNQ(
- cfg["ip"],
- cfg["port"],
- cfg["username"],
- cfg["password"],
- cfg["target_dir"],
- )
- )
- # save the model to be able to link it to the parent
- model.save(
- get_checkpoint_name(topology, wbits, abits, QONNX_export, "deploy_" + kind)
- )
-
- @pytest.mark.parametrize("kind", ["zynq", "alveo"])
- def test_run_on_hw(self, topology, wbits, abits, QONNX_export, kind):
- prev_chkpt_name = get_checkpoint_name(
- topology, wbits, abits, QONNX_export, "deploy_" + kind
- )
- model = load_test_checkpoint_or_skip(prev_chkpt_name) # NOQA
- cfg = get_build_env(kind, target_clk_ns)
- if cfg["ip"] == "":
- pytest.skip("PYNQ board IP address not specified")
- (input_tensor_npy, output_tensor_npy) = get_golden_io_pair(
- topology, wbits, abits, return_topk=1
- )
- parent_model = load_test_checkpoint_or_skip(
- get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent")
- )
- iname = parent_model.graph.input[0].name
- oname = parent_model.graph.output[0].name
- sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
- sdp_node = getCustomOp(sdp_node)
- sdp_node.set_nodeattr("model", prev_chkpt_name)
- ret = execute_onnx(parent_model, {iname: input_tensor_npy}, True)
- y = ret[oname]
- assert np.isclose(y, output_tensor_npy).all()
-
- @pytest.mark.parametrize("kind", ["zynq", "alveo"])
- def test_throughput_hw(self, topology, wbits, abits, QONNX_export, kind):
- prev_chkpt_name = get_checkpoint_name(
- topology, wbits, abits, QONNX_export, "deploy_" + kind
- )
- end2end_example = "%s_w%da%d_%s" % (topology, wbits, abits, kind)
- model = load_test_checkpoint_or_skip(prev_chkpt_name) # NOQA
- cfg = get_build_env(kind, target_clk_ns)
- if cfg["ip"] == "":
- pytest.skip("PYNQ board IP address not specified")
- ret = dict()
- # try a range of batch sizes, some may fail due to insufficient DMA
- # buffers
- bsize_range_in = [8**i for i in range(5)]
- bsize_range = []
- for bsize in bsize_range_in:
- res = throughput_test_remote(model, bsize)
- if res is not None:
- ret[bsize] = res
- bsize_range.append(bsize)
- else:
- # assume we reached largest possible N
- break
- y = [ret[key]["runtime[ms]"] for key in bsize_range]
- lrret = linregress(bsize_range, y)
- ret_str = ""
- ret_str += "\n" + "%s Throughput Test Results" % end2end_example
- ret_str += "\n" + "-----------------------------"
- ret_str += "\n" + "From linear regression:"
- ret_str += "\n" + "Invocation overhead: %f ms" % lrret.intercept
- ret_str += "\n" + "Time per sample: %f ms" % lrret.slope
- ret_str += "\n" + "Raw data:"
-
- ret_str += "\n" + "{:<8} {:<16} {:<16} {:<16} {:<16} {:<16}".format(
- "N", "runtime[ms]", "fclk[mhz]", "fps", "DRAM rd[MB/s]", "DRAM wr[MB/s]"
- )
- for k in bsize_range:
- v = ret[k]
- ret_str += "\n" + "{:<8} {:<16} {:<16} {:<16} {:<16} {:<16}".format(
- k,
- np.round(v["runtime[ms]"], 4),
- v["fclk[mhz]"],
- np.round(v["throughput[images/s]"], 2),
- np.round(v["DRAM_in_bandwidth[MB/s]"], 2),
- np.round(v["DRAM_out_bandwidth[MB/s]"], 2),
- )
- ret_str += "\n" + "-----------------------------"
- warnings.warn(ret_str)
- largest_bsize = bsize_range[-1]
- update_dashboard_data(
- topology, wbits, abits, "fclk[mhz]", ret[largest_bsize]["fclk[mhz]"]
- )
- update_dashboard_data(
- topology,
- wbits,
- abits,
- "throughput[images/s]",
- ret[largest_bsize]["throughput[images/s]"],
- )
-
- def test_upload_results_to_dashboard(self, topology, wbits, abits, QONNX_export):
- # ToDo: Extend the dashboard to also upload QONNX exported models?
- if QONNX_export:
- pytest.skip("Dashboard data upload is disabled for QONNX exported models.")
- else:
- dashboard_data = get_dashboard_data(topology, wbits, abits)
- if len(dashboard_data.keys()) > 0:
- upload_to_end2end_dashboard(dashboard_data)
- else:
- pytest.skip("No data to upload to dashboard")
diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py
index 290afc308498490cbee2fc75c30e22bb474eb96a..5e402bdeb44a73a0cb750083cd6f4d431e9bb7c9 100644
--- a/tests/end2end/test_end2end_cybsec_mlp.py
+++ b/tests/end2end/test_end2end_cybsec_mlp.py
@@ -30,17 +30,14 @@ import pkg_resources as pk
import pytest
-import brevitas.onnx as bo
import json
import numpy as np
import os
import shutil
-import subprocess
import torch
import torch.nn as nn
-import wget
from brevitas.core.quant import QuantType
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+from brevitas.export import export_finn_onnx, export_qonnx
from brevitas.nn import QuantIdentity, QuantLinear, QuantReLU
from brevitas.quant_tensor import QuantTensor
from qonnx.core.datatype import DataType
@@ -133,10 +130,10 @@ def test_end2end_cybsec_mlp_export(QONNX_export):
)
if QONNX_export:
- # With the BrevitasONNXManager we need to manually set
+ # With the onnx export from Brevitas we need to manually set
# the FINN DataType at the input
- BrevitasONNXManager.export(
- model_for_export, input_shape, export_path=export_onnx_path
+ export_qonnx(
+ model_for_export, torch.randn(input_shape), export_path=export_onnx_path
)
model = ModelWrapper(export_onnx_path)
model.set_tensor_datatype(model.graph.input[0].name, DataType["BIPOLAR"])
@@ -146,7 +143,7 @@ def test_end2end_cybsec_mlp_export(QONNX_export):
model = model.transform(ConvertQONNXtoFINN())
model.save(export_onnx_path)
else:
- bo.export_finn_onnx(
+ export_finn_onnx(
model_for_export, export_path=export_onnx_path, input_t=input_qt
)
assert os.path.isfile(export_onnx_path)
@@ -223,65 +220,6 @@ def test_end2end_cybsec_mlp_build(QONNX_export):
assert est_cycles_dict["MatrixVectorActivation_1"] == 64
with open(est_res_report, "r") as f:
est_res_dict = json.load(f)
- assert est_res_dict["total"]["LUT"] == 11360.0
+ assert est_res_dict["total"]["LUT"] == 7904.0
assert est_res_dict["total"]["BRAM_18K"] == 36.0
shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build", QONNX_export))
-
-
-@pytest.mark.end2end
-@pytest.mark.xfail
-@pytest.mark.parametrize("QONNX_export", [False, True])
-def test_end2end_cybsec_mlp_run_on_hw(QONNX_export):
- build_env = get_build_env(build_kind, target_clk_ns)
- assets_dir = pk.resource_filename("finn.qnn-data", "cybsec-mlp/")
- deploy_dir = get_checkpoint_name("build", QONNX_export)
- if not os.path.isdir(deploy_dir):
- pytest.skip(deploy_dir + " not found from previous test step, skipping")
- driver_dir = deploy_dir + "/driver"
- assert os.path.isdir(driver_dir)
- # put all assets into driver dir
- shutil.copy(assets_dir + "/validate-unsw-nb15.py", driver_dir)
- # put a copy of binarized dataset into driver dir
- dataset_url = (
- "https://zenodo.org/record/4519767/files/unsw_nb15_binarized.npz?download=1"
- )
- dataset_local = driver_dir + "/unsw_nb15_binarized.npz"
- if not os.path.isfile(dataset_local):
- wget.download(dataset_url, out=dataset_local)
- assert os.path.isfile(dataset_local)
- # create a shell script for running validation: 10 batches x 10 imgs
- with open(driver_dir + "/validate.sh", "w") as f:
- f.write(
- """#!/bin/bash
-cd %s/driver
-echo %s | sudo -S python3.6 validate-unsw-nb15.py --batchsize=10 --limit_batches=10
- """
- % (
- build_env["target_dir"] + "/end2end_cybsecmlp_build",
- build_env["password"],
- )
- )
- # set up rsync command
- remote_target = "%s@%s:%s" % (
- build_env["username"],
- build_env["ip"],
- build_env["target_dir"],
- )
- rsync_res = subprocess.run(["rsync", "-avz", deploy_dir, remote_target])
- assert rsync_res.returncode == 0
- remote_verif_cmd = [
- "ssh",
- "%s@%s" % (build_env["username"], build_env["ip"]),
- "sh",
- build_env["target_dir"] + "/end2end_cybsecmlp_build/driver/validate.sh",
- ]
- verif_res = subprocess.run(
- remote_verif_cmd,
- stdout=subprocess.PIPE,
- universal_newlines=True,
- input=build_env["password"],
- )
- assert verif_res.returncode == 0
- log_output = verif_res.stdout.split("\n")
- assert log_output[-3] == "batch 10 / 10 : total OK 93 NOK 7"
- assert log_output[-2] == "Final accuracy: 93.000000"
diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py
index 2f4df956acb79c2c4047e6430ccb6f17b76be2e0..3a3c0fe237a34bbd59f5c1de82232c429060f280 100644
--- a/tests/end2end/test_end2end_mobilenet_v1.py
+++ b/tests/end2end/test_end2end_mobilenet_v1.py
@@ -27,11 +27,11 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import pytest
-import brevitas.onnx as bo
import numpy as np
import os
import time
import torch
+from brevitas.export import export_finn_onnx
from PIL import Image
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
@@ -95,7 +95,7 @@ def test_end2end_mobilenet_export():
std = 0.226
ch = 3
preproc = NormalizePreProc(mean, std, ch)
- bo.export_finn_onnx(preproc, (1, 3, 224, 224), preproc_onnx)
+ export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx)
preproc_model = ModelWrapper(preproc_onnx)
# set input finn datatype to UINT8
preproc_model.set_tensor_datatype(
@@ -111,7 +111,7 @@ def test_end2end_mobilenet_export():
# export mobilenet
finn_onnx = build_dir + "/end2end_mobilenet_export.onnx"
mobilenet = get_test_model_trained("mobilenet", 4, 4)
- bo.export_finn_onnx(mobilenet, (1, 3, 224, 224), finn_onnx)
+ export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx)
# calculate golden output with pytorch/brevitas and save as .npy
# get single image as input and prepare image
diff --git a/tests/end2end/test_ext_weights.py b/tests/end2end/test_ext_weights.py
index 0a92c74a38d64ade37d576f3830f3a5628c94d88..bef2e0ffa77cb96ff45956e380aeb376def61228 100644
--- a/tests/end2end/test_ext_weights.py
+++ b/tests/end2end/test_ext_weights.py
@@ -110,69 +110,3 @@ def test_end2end_ext_weights_build():
if os.path.isdir(get_checkpoint_name("build")):
shutil.rmtree(get_checkpoint_name("build"))
shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build"))
-
-
-@pytest.mark.board
-@pytest.mark.end2end
-@pytest.mark.xfail
-def test_end2end_ext_weights_dataset():
- # make sure we have local copies of mnist dataset files
- subprocess.check_output(["mkdir", "-p", mnist_local])
- for f in mnist_files:
- if not os.path.isfile(mnist_local + "/" + f):
- wget.download(mnist_url + "/" + f, out=mnist_local + "/" + f)
- assert os.path.isfile(mnist_local + "/" + f)
- # rsync to board
- build_env = get_build_env(build_kind, target_clk_ns)
- mnist_target = "%s@%s:%s" % (build_env["username"], build_env["ip"], "/tmp/")
-
- rsync_dataset_cmd = ["rsync", "-rv", mnist_local + "/", mnist_target]
- subprocess.check_output(rsync_dataset_cmd)
-
-
-@pytest.mark.end2end
-@pytest.mark.xfail
-def test_end2end_ext_weights_run_on_hw():
- build_env = get_build_env(build_kind, target_clk_ns)
- deploy_dir = get_checkpoint_name("build")
- if not os.path.isdir(deploy_dir):
- pytest.skip(deploy_dir + " not found from previous test step, skipping")
- driver_dir = deploy_dir + "/driver"
- assert os.path.isdir(driver_dir)
- # create a shell script for running validation: 10 batches x 10 imgs
- with open(driver_dir + "/validate.sh", "w") as f:
- f.write(
- """#!/bin/bash
-cd %s/driver
-echo %s | sudo -S python3.6 validate.py --dataset mnist --bitfile %s
- """
- % (
- build_env["target_dir"] + "/end2end_ext_weights_build",
- build_env["password"],
- "../bitfile/finn-accel.bit",
- )
- )
- # set up rsync command
- remote_target = "%s@%s:%s" % (
- build_env["username"],
- build_env["ip"],
- build_env["target_dir"],
- )
- rsync_res = subprocess.run(["rsync", "-avz", deploy_dir, remote_target])
- assert rsync_res.returncode == 0
- remote_verif_cmd = [
- "ssh",
- "%s@%s" % (build_env["username"], build_env["ip"]),
- "sh",
- build_env["target_dir"] + "/end2end_ext_weights_build/driver/validate.sh",
- ]
- verif_res = subprocess.run(
- remote_verif_cmd,
- stdout=subprocess.PIPE,
- universal_newlines=True,
- input=build_env["password"],
- )
- assert verif_res.returncode == 0
- log_output = verif_res.stdout.split("\n")
- assert log_output[-3] == "batch 100 / 100 : total OK 9296 NOK 704"
- assert log_output[-2] == "Final accuracy: 92.960000"
diff --git a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py b/tests/fpgadataflow/test_convert_to_hls_conv_layer.py
index de31ef0f125cb96ea82f953eadb9d5ccf7aab16c..7b2793712d41d2a73545c1b5632071334a2ac694 100644
--- a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py
+++ b/tests/fpgadataflow/test_convert_to_hls_conv_layer.py
@@ -73,9 +73,6 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod
if use_rtl_swg and exec_mode == "cppsim":
pytest.skip("cppsim not supported for RTL SWG")
- if use_rtl_swg and kernel_size == 1:
- pytest.skip("1x1 kernel not supported by current RTL SWG")
-
if depthwise is True:
group = out_chn = in_chn
conv_param_shape = [out_chn, 1, kernel_size, kernel_size]
@@ -164,7 +161,7 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod
inp_dict = {model.graph.input[0].name: x}
assert oxe.compare_execution(model, new_model, inp_dict)
- if kernel_size == 1 and stride > 1 and pad == 0:
+ if not use_rtl_swg and kernel_size == 1 and stride > 1 and pad == 0:
assert new_model.graph.node[1].op_type == "DownSampler"
if exec_mode == "rtlsim":
node = new_model.get_nodes_by_op_type("DownSampler")[0]
diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py
index 9997f28438db113e85ce92138b3c08b223185a2c..73721b6cc5744bb1345815e4bcf1c98aadb2d4f1 100644
--- a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py
+++ b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py
@@ -30,9 +30,10 @@ import pkg_resources as pk
import pytest
-import brevitas.onnx as bo
import numpy as np
import os
+import torch
+from brevitas.export import export_finn_onnx
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.custom_op.registry import getCustomOp
from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount
@@ -61,7 +62,7 @@ export_onnx_path_cnv = "test_convert_to_hls_layers_cnv.onnx"
@pytest.mark.parametrize("fused_activation", [True, False])
def test_convert_to_hls_layers_cnv_w1a1(fused_activation):
cnv = get_test_model_trained("CNV", 1, 1)
- bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path_cnv)
+ export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv)
model = ModelWrapper(export_onnx_path_cnv)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py
index fd4e3679d7f19471509f8144ac72b4964f5b4a52..5a45638ba1908582a0dd62c9d69f259b85376145 100644
--- a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py
+++ b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py
@@ -28,12 +28,12 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import onnx
import onnx.numpy_helper as nph
import os
import torch
+from brevitas.export import export_finn_onnx
from pkgutil import get_data
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.custom_op.registry import getCustomOp
@@ -59,7 +59,7 @@ export_onnx_path = "test_convert_to_hls_layers_fc.onnx"
@pytest.mark.vivado
def test_convert_to_hls_layers_tfc_w1a1():
tfc = get_test_model_trained("TFC", 1, 1)
- bo.export_finn_onnx(tfc, (1, 1, 28, 28), export_onnx_path)
+ export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
@@ -130,7 +130,7 @@ def test_convert_to_hls_layers_tfc_w1a1():
@pytest.mark.vivado
def test_convert_to_hls_layers_tfc_w1a2():
tfc = get_test_model_trained("TFC", 1, 2)
- bo.export_finn_onnx(tfc, (1, 1, 28, 28), export_onnx_path)
+ export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/fpgadataflow/test_fifosizing.py b/tests/fpgadataflow/test_fifosizing.py
index f4f2b8dbfff0d720ec4eb901704581b096c0ea40..922232c2c2453902b4ed1c4b96b5d9b0f187690a 100644
--- a/tests/fpgadataflow/test_fifosizing.py
+++ b/tests/fpgadataflow/test_fifosizing.py
@@ -31,7 +31,8 @@ import pytest
import json
import shutil
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+import torch
+from brevitas.export import export_qonnx
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.custom_op.registry import getCustomOp
@@ -45,7 +46,7 @@ def fetch_test_model(topology, wbits=2, abits=2):
tmp_output_dir = make_build_dir("build_fifosizing_%s_" % topology)
(model, ishape) = get_trained_network_and_ishape(topology, wbits, abits)
chkpt_name = tmp_output_dir + "/model.onnx"
- BrevitasONNXManager.export(model, ishape, chkpt_name)
+ export_qonnx(model, torch.randn(ishape), chkpt_name)
return tmp_output_dir
@@ -55,7 +56,7 @@ def fetch_test_model(topology, wbits=2, abits=2):
@pytest.mark.parametrize(
"method", ["largefifo_rtlsim_python", "largefifo_rtlsim_cpp", "characterize"]
)
-@pytest.mark.parametrize("topology", ["tfc"])
+@pytest.mark.parametrize("topology", ["tfc", "cnv"])
def test_fifosizing_linear(method, topology):
force_python_rtlsim = "python" in method
method_key = "largefifo_rtlsim" if "largefifo_rtlsim" in method else "characterize"
@@ -68,7 +69,7 @@ def test_fifosizing_linear(method, topology):
force_python_rtlsim=force_python_rtlsim,
synth_clk_period_ns=10.0,
board="Pynq-Z1",
- rtlsim_batch_size=100,
+ rtlsim_batch_size=100 if topology == "tfc" else 2,
shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ,
generate_outputs=[
build_cfg.DataflowOutputType.ESTIMATE_REPORTS,
@@ -83,7 +84,7 @@ def test_fifosizing_linear(method, topology):
with open(tmp_output_dir + "/report/rtlsim_performance.json") as f:
sim_data = json.load(f)
assert (
- float(sim_data["throughput[images/s]"])
+ float(sim_data["stable_throughput[images/s]"])
/ float(est_data["estimated_throughput_fps"])
> 0.9
)
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py
index 58fc5ec04cc471b0e8f201e235ac9bd033e3f5c4..e8236c0c6b8c7fbb9e4394fb3cada785f9c050ac 100755
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py
@@ -140,9 +140,9 @@ def prepare_inputs(input_tensor):
# input datatype
@pytest.mark.parametrize("idt", [DataType["UINT4"]])
# kernel size
-@pytest.mark.parametrize("k", [[2, 2], [3, 3], [1, 3]])
+@pytest.mark.parametrize("k", [[3, 3], [1, 5]])
# input dimension
-@pytest.mark.parametrize("ifm_dim", [[24, 24], [15, 6], [13, 13], [1, 14]])
+@pytest.mark.parametrize("ifm_dim", [[13, 13], [1, 21]])
# input channels
@pytest.mark.parametrize("ifm_ch", [6])
# Stride
@@ -152,9 +152,9 @@ def prepare_inputs(input_tensor):
# depthwise
@pytest.mark.parametrize("dw", [0, 1])
# input channel parallelism ("SIMD")
-@pytest.mark.parametrize("simd", [1, 2, 3, 6])
+@pytest.mark.parametrize("simd", [1, 3, 6])
# parallel_window enable (MMV_out = M*K)
-@pytest.mark.parametrize("parallel_window", [0])
+@pytest.mark.parametrize("parallel_window", [0, 1])
# in/out MMV ("M")
@pytest.mark.parametrize("m", [1])
# Flip dimensions
@@ -198,12 +198,13 @@ def test_fpgadataflow_slidingwindow_rtl(
pytest.skip(
"Illegal convolution configuration: kernel or stride > FM dimension"
)
- if (k_h == 1 and (stride_h != 1 or dilation_h != 1)) or (
- k_w == 1 and (stride_w != 1 or dilation_w != 1)
- ):
+ if (k_h == 1 and dilation_h != 1) or (k_w == 1 and dilation_w != 1):
pytest.skip(
- """Illegal convolution configuration:
- stride or dilation defined for unitary kernel dim"""
+ "Illegal convolution configuration: dilation for unitary kernel dim"
+ )
+ if (stride_h > k_h) or (stride_w > k_w) and not parallel_window:
+ pytest.skip(
+ "Not all combinations for stride > k edge case supported in default mode"
)
if k_h == 1 and k_w == 1 and simd != ifm_ch:
pytest.skip("1x1 Kernel only supported in parallel mode (SIMD=C)")
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py
index 7f7bf649a9284e7716aec5adfb91957fdabb55d5..e586984b31f741d2b4744acd1886e76a4179a59e 100644
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py
@@ -189,6 +189,10 @@ cfg0 = {
"ofm": 64,
"depthwise": True,
"pad_mode": "SAME_UPPER",
+ # run synthesis for one configuration
+ # this helped expose a bug in enum decls previously
+ # (which config the synth runs on does not matter)
+ "do_synth": True,
}
cfg1 = {
"idims": [(32, 16), (16, 8)],
@@ -198,6 +202,7 @@ cfg1 = {
"ofm": 8,
"depthwise": False,
"pad_mode": "SAME_UPPER",
+ "do_synth": False,
}
cfg2 = {
"idims": [(64, 128), (2, 4)],
@@ -207,6 +212,7 @@ cfg2 = {
"ofm": 64,
"depthwise": True,
"pad_mode": "SAME_UPPER",
+ "do_synth": False,
}
@@ -215,6 +221,7 @@ cfg2 = {
@pytest.mark.vivado
@pytest.mark.fpgadataflow
def test_fpgadataflow_conv_dynamic(cfg):
+ do_synth = cfg["do_synth"]
pad_mode = cfg["pad_mode"]
depthwise = cfg["depthwise"]
idims = cfg["idims"]
@@ -292,7 +299,7 @@ def test_fpgadataflow_conv_dynamic(cfg):
model = model.transform(GiveReadableTensorNames())
model = model.transform(PrepareIP("xc7z020clg400-1", 5))
model = model.transform(HLSSynthIP())
- model = model.transform(CreateStitchedIP("xc7z020clg400-1", 5))
+ model = model.transform(CreateStitchedIP("xc7z020clg400-1", 5, vitis=do_synth))
model.set_metadata_prop("exec_mode", "rtlsim")
# loop through experiment configurations
diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
index b220338e6919e8eeaeef0f6e5343fed9b1dfca10..7e4069f5c481344560509d17c086ca2cbdbd0fda 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py
@@ -206,7 +206,6 @@ def test_fpgadataflow_ipstitch_gen_model(mem_mode):
assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
assert os.path.isfile(sdp_node.get_nodeattr("model"))
model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model"))
- model.set_metadata_prop("exec_mode", "remote_pynq")
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP(test_fpga_part, 5))
diff --git a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py
index b3cf7b4229c39f27c7f3689ef51fb7d22c7aa0f2..2ff7dd8b3290adf9fa09effa6df4ebb98e1804b9 100644
--- a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py
+++ b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py
@@ -101,7 +101,7 @@ def test_res_estimate():
"MatrixVectorActivation_0": {
"BRAM_18K": 0,
"BRAM_efficiency": 1,
- "LUT": 357,
+ "LUT": 317,
"DSP": 0,
"URAM_efficiency": 1,
"URAM": 0,
@@ -119,7 +119,7 @@ def test_res_estimate():
{
"BRAM_18K": 0,
"BRAM_efficiency": 1,
- "LUT": 352,
+ "LUT": 313,
"DSP": 1,
"URAM": 0,
"URAM_efficiency": 1,
@@ -127,7 +127,7 @@ def test_res_estimate():
{
"BRAM_18K": 0,
"BRAM_efficiency": 1,
- "LUT": 357,
+ "LUT": 317,
"DSP": 0,
"URAM": 0,
"URAM_efficiency": 1,
diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py
index 96cd69c3453793c1634f132cb159f0cc8a94a28c..445afdf458c0e99d4a4dcc4eeb2f6fb305dbac4a 100644
--- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py
+++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py
@@ -132,10 +132,6 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode):
odt = act
n_steps = act.get_num_possible_values() - 1
T = np.random.randint(idt.min(), idt.max() + 1, (ich, n_steps)).astype(np.float32)
- # make the vivado_hls threshold bug appear (incorrect rtlsim result when first
- # threshold of first channel is zero, while using BIPOLAR output)
- if act == DataType["BIPOLAR"]:
- T[0][0] = 0
# provide non-decreasing thresholds
T = np.sort(T, axis=1)
diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py
index abf8ba0b9efde67c77711abc8451475887430cae..95501078d6dcf82f7aa3f0eb887436e7640dfeae 100644
--- a/tests/fpgadataflow/test_fpgadataflow_vvau.py
+++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py
@@ -35,6 +35,8 @@ from qonnx.core.modelwrapper import ModelWrapper
from qonnx.custom_op.general.multithreshold import multithreshold
from qonnx.custom_op.registry import getCustomOp
from qonnx.transformation.general import GiveUniqueNodeNames
+from qonnx.transformation.infer_datatypes import InferDataTypes
+from qonnx.transformation.infer_shapes import InferShapes
from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model
import finn.core.onnx_exec as oxe
@@ -77,6 +79,7 @@ def _calculate_dot_prod_range(dt_a, dt_b, len):
def _make_single_vvau_modelwrapper(
W,
pe,
+ simd,
k_h,
k_w,
channels,
@@ -103,7 +106,10 @@ def _make_single_vvau_modelwrapper(
if T is not None:
no_act = 0
node_inp_list = ["inp", "weights", "thresh"]
- actval = odt.min()
+ if odt == DataType["BIPOLAR"]:
+ actval = 0
+ else:
+ actval = odt.min()
else:
no_act = 1
node_inp_list = ["inp", "weights"]
@@ -116,6 +122,7 @@ def _make_single_vvau_modelwrapper(
domain="finn.custom_op.fpgadataflow",
backend="fpgadataflow",
PE=pe,
+ SIMD=simd,
Dim=[dim_h, dim_w],
Channels=channels,
Kernel=[k_h, k_w],
@@ -146,6 +153,9 @@ def _make_single_vvau_modelwrapper(
model.set_tensor_datatype("thresh", tdt)
model.set_initializer("thresh", T)
+ model = model.transform(InferShapes())
+ model = model.transform(InferDataTypes())
+
return model
@@ -154,13 +164,15 @@ def prepare_inputs(input_tensor):
# input datatype
-@pytest.mark.parametrize("idt", [DataType["UINT4"], DataType["UINT8"]])
+@pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["UINT4"]])
# weight datatype
-@pytest.mark.parametrize("wdt", [DataType["INT4"]])
+@pytest.mark.parametrize("wdt", [DataType["BIPOLAR"], DataType["UINT4"]])
# activation: None or DataType
-@pytest.mark.parametrize("act", [DataType["UINT4"], None])
+@pytest.mark.parametrize("act", [DataType["BIPOLAR"], DataType["UINT4"], None])
# PE
-@pytest.mark.parametrize("pe", [1, "channels"])
+@pytest.mark.parametrize("pe", [1, 3, 6])
+# SIMD
+@pytest.mark.parametrize("simd", [1, 9])
# Input image shape
@pytest.mark.parametrize("dim_h", [10])
@pytest.mark.parametrize("dim_w", [10, 1])
@@ -168,7 +180,7 @@ def prepare_inputs(input_tensor):
@pytest.mark.parametrize("k_h", [3])
@pytest.mark.parametrize("k_w", [3, 1])
# Number of input and output channels
-@pytest.mark.parametrize("channels", [3, 4])
+@pytest.mark.parametrize("channels", [3, 6])
# memory mode
@pytest.mark.parametrize("mem_mode", ["const", "decoupled"])
# execution mode
@@ -177,17 +189,17 @@ def prepare_inputs(input_tensor):
@pytest.mark.slow
@pytest.mark.vivado
def test_fpgadataflow_vvau(
- idt, wdt, act, pe, dim_h, dim_w, k_h, k_w, channels, mem_mode, exec_mode
+ idt, wdt, act, pe, simd, dim_h, dim_w, k_h, k_w, channels, mem_mode, exec_mode
):
- if pe == "channels":
- pe = channels
-
if dim_w == 1 and k_w != 1:
pytest.skip("1D image requires 1D kernel, skipping.")
if channels % pe != 0:
pytest.skip("Requirement Channels divisable by PE is violated.")
+ if (k_h * k_w) % simd != 0:
+ pytest.skip("Requirement kernel (k_h * k_w) divisable by SIMD is violated.")
+
# Generate weights in expected shape for ONNX and HLS node
W = gen_finn_dt_tensor(wdt, (channels, 1, k_h, k_w)) # shape: [channels, 1, k, k]
W_onnx = _infer_sparse_weight_tensor(
@@ -203,17 +215,26 @@ def test_fpgadataflow_vvau(
if act is None:
T = None
tdt = None
- odt = DataType["INT32"]
+ if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]:
+ odt = DataType["UINT32"]
+ else:
+ odt = DataType["INT32"]
else:
odt = act
- (min_v, max_v) = _calculate_dot_prod_range(idt, wdt, k_h * k_w * channels)
+ (min_v, max_v) = _calculate_dot_prod_range(idt, wdt, k_h * k_w)
n_steps = act.get_num_possible_values() - 1
T = np.random.randint(min_v, max_v - 1, (channels, n_steps)).astype(np.float32)
T = np.sort(T, axis=1)
- tdt = DataType["INT32"]
+ if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]:
+ tdt = DataType["UINT32"]
+ # bias thresholds to be positive
+ T = np.ceil((T + (k_h * k_w)) / 2)
+ assert (T >= 0).all()
+ else:
+ tdt = DataType["INT32"]
model = _make_single_vvau_modelwrapper(
- W, pe, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T, tdt, mem_mode
+ W, pe, simd, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T, tdt, mem_mode
)
if exec_mode == "cppsim":
@@ -232,20 +253,31 @@ def test_fpgadataflow_vvau(
input_dict = prepare_inputs(x_vvau)
# Calculate output
- y_expected = np.matmul(x, W_onnx) # Y is in [N, H, W, C] format
+ if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]:
+ # Simulate XNOR-popcount matrix multiplication, see
+ # qonnx.custom_op.general.xnorpopcount (not usable due to sparse W)
+ y_expected = np.matmul(x, W_onnx)
+ y_expected = (y_expected + (k_h * k_w)) / 2
+ else:
+ y_expected = np.matmul(x, W_onnx) # Y is in [N, H, W, C] format
+
if T is not None:
# Reshape Y, as multithreshold expects Y to be in [N, C, H, W] format
y_expected = np.transpose(y_expected, (0, 3, 1, 2))
y_expected = multithreshold(y_expected, T)
y_expected = np.transpose(y_expected, (0, 2, 3, 1))
- # signed offset
- y_expected += act.min()
+ if act == DataType["BIPOLAR"]:
+ # binary to bipolar
+ y_expected = 2 * y_expected - 1
+ else:
+ # signed offset
+ y_expected += act.min()
y_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=False)[
"outp"
]
- assert (y_produced == y_expected).all(), "cppsim failed"
+ assert (y_produced == y_expected).all(), "incorrect result"
if exec_mode == "rtlsim":
node = model.get_nodes_by_op_type("VectorVectorActivation")[0]
diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py
new file mode 100644
index 0000000000000000000000000000000000000000..dc4a076a1808932b027f87d10b4d31a400ac1ad5
--- /dev/null
+++ b/tests/fpgadataflow/test_minimize_bit_width.py
@@ -0,0 +1,320 @@
+# Copyright (C) 2023, Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import pytest
+
+import numpy as np
+from onnx import TensorProto, helper
+from qonnx.core.datatype import BipolarType, DataType, IntType
+from qonnx.core.modelwrapper import ModelWrapper
+from qonnx.custom_op.registry import getCustomOp
+from qonnx.util.basic import gen_finn_dt_tensor, roundup_to_integer_multiple
+from typing import Optional, Union
+
+from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation
+from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation
+from finn.transformation.fpgadataflow.minimize_accumulator_width import (
+ MinimizeAccumulatorWidth,
+)
+from finn.transformation.fpgadataflow.minimize_weight_bit_width import (
+ MinimizeWeightBitWidth,
+)
+
+
+def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = None):
+ """Creates a toy finn-onnx model for unit testing. The VVAU-MVAU pair is based
+ on the first pair of MobileNetV1"""
+ inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, 32, 32, 288])
+ outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, 32, 32, 64])
+ layer1 = helper.make_node(
+ "VectorVectorActivation",
+ ["inp", "params0", "thresh0"] if tdt is not None else ["inp", "params0"],
+ ["hid"],
+ domain="finn.custom_op.fpgadataflow",
+ backend="fpgadataflow",
+ PE=1,
+ Channels=32,
+ Dim=(32, 32),
+ Kernel=(3, 3),
+ inputDataType=idt.name,
+ outputDataType=idt.name,
+ weightDataType=wdt.name,
+ ActVal=tdt.min() if tdt is not None else 0,
+ noActivation=0 if tdt is not None else 1,
+ )
+ layer2 = helper.make_node(
+ "MatrixVectorActivation",
+ ["hid", "params1", "thresh1"] if tdt is not None else ["hid", "params1"],
+ ["outp"],
+ domain="finn.custom_op.fpgadataflow",
+ backend="fpgadataflow",
+ MW=32, # matrix_width (num_inputs)
+ MH=64, # matrix_height (num_outputs)
+ SIMD=1,
+ PE=1,
+ inputDataType=idt.name,
+ outputDataType=idt.name,
+ weightDataType=wdt.name,
+ ActVal=tdt.min() if tdt is not None else 0,
+ noActivation=0 if tdt is not None else 1,
+ binaryXnorMode=0,
+ )
+ graph = helper.make_graph(
+ nodes=[layer1, layer2], name="fclayer_graph", inputs=[inp], outputs=[outp]
+ )
+
+ model = helper.make_model(graph, producer_name="fclayer-model")
+ model = ModelWrapper(model)
+
+ model.set_tensor_datatype("inp", idt)
+ model.set_tensor_datatype("outp", idt)
+ model.set_tensor_datatype("hid", idt)
+ model.set_tensor_datatype("params0", wdt)
+ model.set_tensor_datatype("params1", wdt)
+ model.set_initializer("params0", gen_finn_dt_tensor(wdt, (32, 1, 3, 3)))
+ model.set_initializer("params1", gen_finn_dt_tensor(wdt, (32, 64)))
+ # if the threshold data type is specified, then we need to generate
+ # some dummy threshold values
+ if tdt is not None:
+ model.set_tensor_datatype("thresh0", tdt)
+ model.set_tensor_datatype("thresh1", tdt)
+ # Create threshold tensors
+ n_steps: int = idt.get_num_possible_values() - 1
+ thresholds: Optional[np.ndarray] = np.random.randint(
+ tdt.min(), tdt.max() - 1, (32, n_steps)
+ ).astype(
+ np.float32
+ ) # generate thresholds for the activations
+ thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds
+ model.set_initializer("thresh0", thresholds)
+ thresholds: Optional[np.ndarray] = np.random.randint(
+ tdt.min(), tdt.max() - 1, (64, n_steps)
+ ).astype(
+ np.float32
+ ) # generate thresholds for the activations
+ thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds
+ model.set_initializer("thresh1", thresholds)
+ return model
+
+
+weight_data_types = [
+ DataType["INT8"],
+ DataType["UINT8"],
+ DataType["INT7"],
+ DataType["UINT7"],
+ DataType["INT3"],
+ DataType["UINT3"],
+ # DataType["BIPOLAR"], # TODO - add support for bipolar weights
+ DataType["TERNARY"],
+]
+
+
+input_data_types = [
+ DataType["INT8"],
+ DataType["UINT8"],
+ DataType["INT3"],
+ DataType["UINT3"],
+ DataType["BIPOLAR"],
+ DataType["TERNARY"],
+]
+
+
+@pytest.mark.parametrize("wdt", weight_data_types)
+@pytest.mark.parametrize("rww", [True, False])
+@pytest.mark.fpgadataflow
+def test_minimize_weight_bit_width(wdt: DataType, rww: bool):
+ """Testing MinimizeWeightBitWidth for VVAU and MVAU.
+
+ :param wdt: (DataType) The data type that we are testing for the weights
+ :param rww: (bool) Whether or not to use runtime-writeable weights"""
+ if isinstance(wdt, BipolarType):
+ # current MinimizeWeightBitWidth sets {-1,1} to INT2, need to check
+ # for 0 in weights to minimize weight bit width to bipolar
+ pytest.skip("Not well-supported for this optimization")
+
+ # Create a w8a8 model
+ def_wdt = DataType["UINT8"]
+ model = make_unit_test_model(def_wdt, DataType["INT8"])
+
+ # Create new weights for the model based on wdt
+ params0 = gen_finn_dt_tensor(wdt, (32, 1, 3, 3))
+ params1 = gen_finn_dt_tensor(wdt, (32, 64))
+ model.set_initializer("params0", params0)
+ model.set_initializer("params1", params1)
+
+ # If runtime-writeable weights, specify as a node attribute
+ for node in model.graph.node:
+ inst = getCustomOp(node)
+ if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)):
+ inst.set_nodeattr("runtime_writeable_weights", int(rww))
+
+ # Apply the optimization
+ model = model.transform(MinimizeWeightBitWidth())
+
+ # Iterate through each node to make sure it functioned properly
+ for node in model.graph.node:
+ inst = getCustomOp(node)
+ if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)):
+ cur_wdt = DataType[inst.get_nodeattr("weightDataType")]
+ exp_wdt = def_wdt if rww else wdt
+ assert cur_wdt.bitwidth() == exp_wdt.bitwidth(), "Mismatched data types"
+
+
+def calculate_accumulator_bit_width(
+ inst: Union[MatrixVectorActivation, VectorVectorActivation], model: ModelWrapper
+) -> Union[DataType, IntType]:
+ """Calculate the accumulator bit width using the closed-form expressions
+ derived in `Quantized Neural Networks for Low-Precision Accumulation
+ with Guaranteed Overflow Avoidance` (2023) by I.Colbert, A. Pappalardo,
+ J. Petri-Koenig
+
+ :param inst: (HLSCustomOp) The instance of the MVAU or VVAU
+ :param model: (ModelWrapper) The instance of the whole model
+ """
+
+ def phi(x: float) -> float:
+ return np.log2(1 + pow(2, -x))
+
+ weights = model.get_initializer(inst.onnx_node.input[1])
+ # since in the calculation the values of the weight matrix are used,
+ # for the bipolar case they need to be converted to bipolar
+ if inst.get_nodeattr("binaryXnorMode"):
+ weights = 2 * weights - 1
+ # modify the weights based on if the node is a VVAU or MVAU
+ if isinstance(inst, MatrixVectorActivation):
+ K = inst.get_nodeattr("MW") # matrix_width = num_inputs
+ elif isinstance(inst, VectorVectorActivation):
+ k_h, k_w = inst.get_nodeattr("Kernel")
+ K = k_h * k_w # size of kernels = num_inputs
+ fm = inst.get_nodeattr("Channels")
+ # put weights into the shape expected by calculate_matvec_accumulator_range
+ weights = weights.reshape(fm, k_h * k_w).transpose()
+ else:
+ raise Exception("Considering only MVAU and VVAU currently")
+ # collect attributes used to determine the accumulator bit width bound
+ wdt = inst.get_weight_datatype()
+ idt = inst.get_input_datatype()
+ rww = inst.get_nodeattr("runtime_writeable_weights")
+ # if runtime-writeable weights, then use the lower bound on the accumulator bit
+ # width as determined by the input and weight data types and size of dot product
+ if rww:
+ alpha = np.log2(K) + idt.bitwidth() + wdt.bitwidth() - 1.0 - float(idt.signed())
+ P = np.ceil(alpha + phi(alpha) + 1.0)
+ # if not runtime-writable weights, then use the tighter bound on the accumulator
+ # bit width as determined by the weight values themselves
+ else:
+ beta = (
+ np.log2(abs(weights).sum(axis=0).max())
+ + idt.bitwidth()
+ - float(idt.signed())
+ )
+ P = np.ceil(beta + phi(beta) + 1.0)
+ # if the node is the last in the graph, then round up to the nearest 8 bits
+ if model.find_direct_successors(inst.onnx_node) is None:
+ P = roundup_to_integer_multiple(P, 8)
+ return DataType[f"INT{int(P)}"]
+
+
+thresh_data_types = [
+ None,
+ DataType["INT32"],
+ DataType["INT24"],
+ DataType["INT16"],
+]
+
+# Removing unsigned data types fro weights
+weight_data_types = [
+ DataType["INT8"],
+ DataType["INT7"],
+ DataType["INT3"],
+ # DataType["BIPOLAR"], # TODO - add support for bipolar weights
+ DataType["TERNARY"],
+]
+
+
+@pytest.mark.parametrize("wdt", weight_data_types)
+@pytest.mark.parametrize("idt", input_data_types)
+@pytest.mark.parametrize("tdt", thresh_data_types)
+@pytest.mark.parametrize("rww", [True, False])
+@pytest.mark.fpgadataflow
+def test_minimize_accumulator_width(
+ wdt: DataType, idt: DataType, tdt: DataType, rww: bool
+):
+ """Testing MinimizeAccumulatorWidth for VVAU and MVAU.
+
+ :param wdt: (DataType) The data type that we are testing for the weights
+ :param idt: (DataType) The data type that we are testing for the activations
+ :param tdt: (DataType) The data type that we are testing for the thresholds
+ :param rww: (bool) Whether or not to use runtime-writeable weights"""
+ if (not wdt.signed()) or isinstance(wdt, BipolarType):
+ pytest.skip(
+ "Closed-form accumulator calculation is designed to consider signed weights"
+ )
+
+ # Create uniform-precision model
+ model = make_unit_test_model(wdt, idt, tdt)
+ def_adt = DataType["INT32"]
+
+ # If runtime-writeable weights, specify as a node attribute
+ for node in model.graph.node:
+ inst = getCustomOp(node)
+ if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)):
+ inst.set_nodeattr("runtime_writeable_weights", int(rww))
+ cur_adt = DataType[inst.get_nodeattr("accDataType")]
+ assert (
+ cur_adt.bitwidth() == def_adt.bitwidth()
+ ), "Default data type is incorrect"
+
+ # Apply the optimization
+ model = model.transform(MinimizeAccumulatorWidth())
+
+ # Iterate through each node to make sure it functioned properly
+ for node in model.graph.node:
+ inst = getCustomOp(node)
+ if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)):
+ cur_adt = DataType[inst.get_nodeattr("accDataType")]
+ cur_odt = DataType[inst.get_nodeattr("outputDataType")]
+ # Calculating expected accumulator bit width using a closed-form expression
+ # that is a slight over-approximation of the lower bound. The accumulator
+ # bit width minimization logic in the MVAU and VVAU is exact and should be
+ # less than or equal to this calculation
+ exp_adt = calculate_accumulator_bit_width(inst, model)
+ assert (
+ cur_adt.bitwidth() <= exp_adt.bitwidth()
+ ), "Mismatched accumulation data types"
+ if model.find_direct_successors(inst.onnx_node) is None:
+ assert (
+ cur_adt.bitwidth() % 8
+ ) == 0, "bit width of last node needs to be divisible by 8"
+ assert (
+ cur_adt.bitwidth() == cur_odt.bitwidth()
+ ), "outputDataType and accDataType should be equal"
+ else:
+ assert (
+ cur_odt.bitwidth() == idt.bitwidth()
+ ), "outputDataType should not be changed"
diff --git a/tests/fpgadataflow/test_split_large_fifos.py b/tests/fpgadataflow/test_split_large_fifos.py
index 85b4a2bfa8dc0de3cbdd0ca34ec5b1ee68f37acf..0437d006cf09fe2ad5076d2e62105c9adea6ff41 100644
--- a/tests/fpgadataflow/test_split_large_fifos.py
+++ b/tests/fpgadataflow/test_split_large_fifos.py
@@ -31,7 +31,8 @@ import pytest
import json
import shutil
-from brevitas.export.onnx.generic.manager import BrevitasONNXManager
+import torch
+from brevitas.export import export_qonnx
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.custom_op.registry import getCustomOp
@@ -46,7 +47,7 @@ def fetch_test_model(topology, wbits=2, abits=2):
tmp_output_dir = make_build_dir("build_fifosizing_%s_" % topology)
(model, ishape) = get_trained_network_and_ishape(topology, wbits, abits)
chkpt_name = tmp_output_dir + "/model.onnx"
- BrevitasONNXManager.export(model, ishape, chkpt_name)
+ export_qonnx(model, torch.randn(ishape), chkpt_name)
return tmp_output_dir
diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py
new file mode 100644
index 0000000000000000000000000000000000000000..819b4ccde0333cfdf6e16f30e25fb5303fbf1f70
--- /dev/null
+++ b/tests/notebooks/test_jupyter_notebooks.py
@@ -0,0 +1,52 @@
+import pytest
+
+import nbformat
+from nbconvert.preprocessors import ExecutePreprocessor
+
+from finn.util.basic import get_finn_root
+
+notebook_timeout_seconds = 3600
+notebook_basic_dir = get_finn_root() + "/notebooks/basics/"
+notebook_advanced_dir = get_finn_root() + "/notebooks/advanced/"
+notebook_cyber_dir = get_finn_root() + "/notebooks/end2end_example/cybersecurity/"
+notebook_bnn_dir = get_finn_root() + "/notebooks/end2end_example/bnn-pynq/"
+
+basics_notebooks = [
+ pytest.param(notebook_basic_dir + "0_how_to_work_with_onnx.ipynb"),
+ pytest.param(notebook_basic_dir + "1a_brevitas_network_import_via_FINN-ONNX.ipynb"),
+ pytest.param(notebook_basic_dir + "1b_brevitas_network_import_via_QONNX.ipynb"),
+]
+
+advanced_notebooks = [
+ pytest.param(notebook_advanced_dir + "0_custom_analysis_pass.ipynb"),
+ pytest.param(notebook_advanced_dir + "1_custom_transformation_pass.ipynb"),
+ pytest.param(notebook_advanced_dir + "2_custom_op.ipynb"),
+]
+
+cyber_notebooks = [
+ pytest.param(notebook_cyber_dir + "1-train-mlp-with-brevitas.ipynb"),
+ pytest.param(notebook_cyber_dir + "2-import-into-finn-and-verify.ipynb"),
+ pytest.param(notebook_cyber_dir + "3-build-accelerator-with-finn.ipynb"),
+]
+
+bnn_notebooks = [
+ pytest.param(notebook_bnn_dir + "cnv_end2end_example.ipynb"),
+ pytest.param(notebook_bnn_dir + "tfc_end2end_example.ipynb"),
+ pytest.param(notebook_bnn_dir + "tfc_end2end_verification.ipynb"),
+]
+
+
+@pytest.mark.notebooks
+@pytest.mark.parametrize(
+ "notebook", basics_notebooks + advanced_notebooks + cyber_notebooks + bnn_notebooks
+)
+def test_notebook_exec(notebook):
+ with open(notebook) as f:
+ nb = nbformat.read(f, as_version=4)
+ ep = ExecutePreprocessor(
+ timeout=notebook_timeout_seconds, kernel_name="python3"
+ )
+ try:
+ assert ep.preprocess(nb) is not None, f"Got empty notebook for {notebook}"
+ except Exception:
+ assert False, f"Failed executing {notebook}"
diff --git a/tests/transformation/streamline/test_sign_to_thres.py b/tests/transformation/streamline/test_sign_to_thres.py
index 839680bd7ad2d40cb622b313257e819737027a2f..72e400346d3491c66c5ba0f0a1c7da63eeff96fa 100644
--- a/tests/transformation/streamline/test_sign_to_thres.py
+++ b/tests/transformation/streamline/test_sign_to_thres.py
@@ -28,10 +28,11 @@
import pytest
-import brevitas.onnx as bo
import onnx
import onnx.numpy_helper as nph
import os
+import torch
+from brevitas.export import export_finn_onnx
from pkgutil import get_data
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
@@ -47,7 +48,7 @@ export_onnx_path = "test_sign_to_thres.onnx"
@pytest.mark.streamline
def test_sign_to_thres():
lfc = get_test_model_trained("LFC", 1, 1)
- bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path)
+ export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/transformation/streamline/test_streamline_cnv.py b/tests/transformation/streamline/test_streamline_cnv.py
index 6a829250127ee289733ec8ce1b08b63de7a573c5..b7d6a825bba4ad33287516ba637804526d0b53f9 100644
--- a/tests/transformation/streamline/test_streamline_cnv.py
+++ b/tests/transformation/streamline/test_streamline_cnv.py
@@ -30,8 +30,9 @@ import pkg_resources as pk
import pytest
-import brevitas.onnx as bo
import numpy as np
+import torch
+from brevitas.export import export_finn_onnx
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
from qonnx.transformation.general import (
@@ -63,7 +64,7 @@ def test_streamline_cnv(size, wbits, abits):
nname = "%s_%dW%dA" % (size, wbits, abits)
finn_onnx = export_onnx_path + "/%s.onnx" % nname
fc = get_test_model_trained(size, wbits, abits)
- bo.export_finn_onnx(fc, (1, 3, 32, 32), finn_onnx)
+ export_finn_onnx(fc, torch.randn(1, 3, 32, 32), finn_onnx)
model = ModelWrapper(finn_onnx)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/transformation/streamline/test_streamline_fc.py b/tests/transformation/streamline/test_streamline_fc.py
index 90008214352d1a75fba61130f5aedbc358e1fe74..6131c3b03ea8542f2a04e14e82b6007c6ae9c6b4 100644
--- a/tests/transformation/streamline/test_streamline_fc.py
+++ b/tests/transformation/streamline/test_streamline_fc.py
@@ -28,10 +28,11 @@
import pytest
-import brevitas.onnx as bo
import numpy as np
import onnx
import onnx.numpy_helper as nph
+import torch
+from brevitas.export import export_finn_onnx
from pkgutil import get_data
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
@@ -66,7 +67,7 @@ def test_streamline_fc(size, wbits, abits):
nname = "%s_%dW%dA" % (size, wbits, abits)
finn_onnx = export_onnx_path + "/%s.onnx" % nname
fc = get_test_model_trained(size, wbits, abits)
- bo.export_finn_onnx(fc, (1, 1, 28, 28), finn_onnx)
+ export_finn_onnx(fc, torch.randn(1, 1, 28, 28), finn_onnx)
model = ModelWrapper(finn_onnx)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py
index fd4e37807c860058a8503439a04a58879edc7954..60e81ffe815645abbc0b34c0a9078c701cf68b9a 100644
--- a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py
+++ b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py
@@ -30,11 +30,12 @@ import pkg_resources as pk
import pytest
-import brevitas.onnx as bo
import numpy as np
import onnx
import onnx.numpy_helper as nph
import os
+import torch
+from brevitas.export import export_finn_onnx
from pkgutil import get_data
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.batchnorm_to_affine import BatchNormToAffine
@@ -50,7 +51,7 @@ export_onnx_path = "test_output_bn2affine.onnx"
@pytest.mark.transform
def test_batchnorm_to_affine_cnv_w1a1():
lfc = get_test_model_trained("CNV", 1, 1)
- bo.export_finn_onnx(lfc, (1, 3, 32, 32), export_onnx_path)
+ export_finn_onnx(lfc, torch.randn(1, 3, 32, 32), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
@@ -75,7 +76,7 @@ def test_batchnorm_to_affine_cnv_w1a1():
@pytest.mark.transform
def test_batchnorm_to_affine_lfc_w1a1():
lfc = get_test_model_trained("LFC", 1, 1)
- bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path)
+ export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py
index 952ce306a447ba0b4d46256ec6e80e5da79be4bc..71822a2903fd284cab9dfee119915a61940cd59b 100644
--- a/tests/transformation/test_infer_data_layouts_cnv.py
+++ b/tests/transformation/test_infer_data_layouts_cnv.py
@@ -28,9 +28,10 @@
import pytest
-import brevitas.onnx as bo
import os
import qonnx.core.data_layout as DataLayout
+import torch
+from brevitas.export import export_finn_onnx
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount
from qonnx.transformation.fold_constants import FoldConstants
@@ -51,7 +52,7 @@ export_onnx_path_cnv = "test_infer_data_layouts.onnx"
@pytest.mark.transform
def test_infer_data_layouts_cnv():
cnv = get_test_model_trained("CNV", 1, 1)
- bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path_cnv)
+ export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv)
model = ModelWrapper(export_onnx_path_cnv)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/transformation/test_infer_datatypes_lfc.py b/tests/transformation/test_infer_datatypes_lfc.py
index 979800534951abbc77d203aa6b5bd9c797aa9028..173532cb76645cab8b48c24c8d55f2d28e7160bf 100644
--- a/tests/transformation/test_infer_datatypes_lfc.py
+++ b/tests/transformation/test_infer_datatypes_lfc.py
@@ -28,8 +28,9 @@
import pytest
-import brevitas.onnx as bo
import os
+import torch
+from brevitas.export import export_finn_onnx
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
@@ -45,7 +46,7 @@ export_onnx_path = "test_infer_datatypes.onnx"
@pytest.mark.transform
def test_infer_datatypes_lfc():
lfc = get_test_model_trained("LFC", 1, 1)
- bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path)
+ export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path)
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
diff --git a/tests/transformation/test_qonnx_to_finn.py b/tests/transformation/test_qonnx_to_finn.py
index 7e438b4b8ba9d9befca79100bb9727735afa27d3..e5f1eefe12aaadcdf9b6da4fd4ace01026ce25af 100644
--- a/tests/transformation/test_qonnx_to_finn.py
+++ b/tests/transformation/test_qonnx_to_finn.py
@@ -31,12 +31,11 @@ import pkg_resources as pk
import pytest
-import brevitas.export.onnx.generic as b_onnx
-import brevitas.onnx as bo
import numpy as np
import onnx
import onnx.numpy_helper as nph
import torch
+from brevitas.export import export_finn_onnx, export_qonnx
from pkgutil import get_data
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.fold_constants import FoldConstants
@@ -117,8 +116,10 @@ def test_QONNX_to_FINN(model_name, wbits, abits):
torch_input_tensor = torch.from_numpy(input_tensor).float()
brev_output = brev_model.forward(torch_input_tensor).detach().numpy()
- # Get "clean" FINN model and it's output
- _ = bo.export_finn_onnx(brev_model, in_shape, finn_base_path.format("raw"))
+ # Get "clean" FINN model and its output
+ _ = export_finn_onnx(
+ brev_model, torch.randn(in_shape), finn_base_path.format("raw")
+ )
model = ModelWrapper(finn_base_path.format("raw"))
model = model.transform(GiveUniqueNodeNames())
model = model.transform(InferShapes())
@@ -137,10 +138,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits):
).all(), "The output of the Brevitas model and the FINN model should match."
# Get the equivalent QONNX model
- b_onnx.function.DOMAIN_STRING = "qonnx.custom_op.general"
- _ = b_onnx.manager.BrevitasONNXManager.export(
- brev_model, in_shape, qonnx_base_path.format("raw")
- )
+ _ = export_qonnx(brev_model, torch.randn(in_shape), qonnx_base_path.format("raw"))
cleanup(qonnx_base_path.format("raw"), out_file=qonnx_base_path.format("clean"))
# Compare output