From e2dd285de2d54c5b93c7423a7a3d5b3da3d2a7e1 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 5 Aug 2020 14:16:36 +0200
Subject: [PATCH] [ZYNQ] add debug/chipscope option
---
.../transformation/fpgadataflow/make_zynq_proj.py | 11 ++++++++---
src/finn/transformation/fpgadataflow/templates.py | 12 ++++++++++++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
index 7b6037d54..994c41fd0 100644
--- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
@@ -90,9 +90,10 @@ class MakeZYNQProject(Transformation):
value.
"""
- def __init__(self, platform):
+ def __init__(self, platform, enable_debug=False):
super().__init__()
self.platform = platform
+ self.enable_debug = 1 if enable_debug else 0
def apply(self, model):
@@ -222,6 +223,7 @@ class MakeZYNQProject(Transformation):
self.platform,
pynq_part_map[self.platform],
config,
+ self.enable_debug,
get_num_default_workers(),
)
)
@@ -267,11 +269,12 @@ class MakeZYNQProject(Transformation):
class ZynqBuild(Transformation):
"""Best-effort attempt at building the accelerator for Zynq."""
- def __init__(self, platform, period_ns):
+ def __init__(self, platform, period_ns, enable_debug=False):
super().__init__()
self.fpga_part = pynq_part_map[platform]
self.period_ns = period_ns
self.platform = platform
+ self.enable_debug = enable_debug
def apply(self, model):
# first infer layouts
@@ -311,5 +314,7 @@ class ZynqBuild(Transformation):
)
kernel_model.save(dataflow_model_filename)
# Assemble design from IPs
- model = model.transform(MakeZYNQProject(self.platform))
+ model = model.transform(
+ MakeZYNQProject(self.platform, enable_debug=self.enable_debug)
+ )
return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index bb4583ef4..d22163cbe 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -376,6 +376,18 @@ connect_bd_net [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins smartconnec
#custom IP instantiations/connections start here
%s
+# set up debug
+if {%d == 1} {
+ set_property HDL_ATTRIBUTE.DEBUG true [get_bd_intf_nets {idma0_m_axis_0}]
+ set_property HDL_ATTRIBUTE.DEBUG true [get_bd_intf_nets {StreamingDataflowPartition_1_m_axis_0}]
+ set_property HDL_ATTRIBUTE.DEBUG true [get_bd_intf_nets {smartconnect_0_M00_AXI}]
+ apply_bd_automation -rule xilinx.com:bd_rule:debug -dict [list \
+ [get_bd_intf_nets smartconnect_0_M00_AXI] {AXI_R_ADDRESS "Data and Trigger" AXI_R_DATA "Data and Trigger" AXI_W_ADDRESS "Data and Trigger" AXI_W_DATA "Data and Trigger" AXI_W_RESPONSE "Data and Trigger" CLK_SRC "/zynq_ps/FCLK_CLK0" SYSTEM_ILA "Auto" APC_EN "0" } \
+ [get_bd_intf_nets idma0_m_axis_0] {AXIS_SIGNALS "Data and Trigger" CLK_SRC "/zynq_ps/FCLK_CLK0" SYSTEM_ILA "Auto" APC_EN "0" } \
+ [get_bd_intf_nets StreamingDataflowPartition_1_m_axis_0] {AXIS_SIGNALS "Data and Trigger" CLK_SRC "/zynq_ps/FCLK_CLK0" SYSTEM_ILA "Auto" APC_EN "0" } \
+ ]
+}
+
#finalize clock and reset connections for interconnects
set i 0
while {$i < $NUM_AXILITE} {
--
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