From df5535fe5eb9d77bab0ce9b694ee1355a36d9f36 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Wed, 25 May 2022 19:21:38 +0100
Subject: [PATCH] [Transformation] Set axilite from axi-info node to correct
clk
---
.../fpgadataflow/create_stitched_ip.py | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 5c376fdfc..39c4a3815 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -256,6 +256,18 @@ class CreateStitchedIP(Transformation):
"connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins %s/ap_rst_n]"
% signature_name
)
+ fclk_mhz = 1 / (self.clk_ns * 0.001)
+ fclk_hz = fclk_mhz * 1000000
+ self.connect_cmds.append(
+ "set_property -dict [list "
+ "CONFIG.FREQ_HZ {%f} "
+ "CONFIG.CLK_DOMAIN {ap_clk} "
+ "] [get_bd_intf_pins %s/s_axi]"
+ % (
+ fclk_hz,
+ signature_name,
+ )
+ )
# make axilite interface external
self.connect_cmds.append(
"make_bd_intf_pins_external [get_bd_intf_pins %s/s_axi]" % signature_name
--
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