From d6ca2e2e67abcc79f399f9c826e2278c49b52db2 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Sat, 20 Nov 2021 00:50:31 +0100
Subject: [PATCH] [Build] better resolution for unspec'd Vitis platform for
Alveo
---
src/finn/builder/build_dataflow_config.py | 15 ++++++++++++++-
src/finn/builder/build_dataflow_steps.py | 2 +-
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py
index 807fd7068..9bda8cb50 100644
--- a/src/finn/builder/build_dataflow_config.py
+++ b/src/finn/builder/build_dataflow_config.py
@@ -34,7 +34,7 @@ from enum import Enum
from typing import Any, List, Optional
from finn.transformation.fpgadataflow.vitis_build import VitisOptStrategy
-from finn.util.basic import alveo_part_map, pynq_part_map
+from finn.util.basic import alveo_default_platform, alveo_part_map, pynq_part_map
class ShellFlowType(str, Enum):
@@ -257,6 +257,8 @@ class DataflowBuildConfig:
#: Which Vitis platform will be used.
#: Only relevant when `shell_flow_type = ShellFlowType.VITIS_ALVEO`
#: e.g. "xilinx_u250_xdma_201830_2"
+ #: If not specified but "board" is specified, will use the FINN
+ #: default (if any) for that Alveo board
vitis_platform: Optional[str] = None
#: Path to JSON config file assigning each layer to an SLR.
@@ -356,6 +358,17 @@ class DataflowBuildConfig:
}
return name_to_strategy[self.vitis_opt_strategy]
+ def _resolve_vitis_platform(self):
+ if self.vitis_platform is not None:
+ return self.vitis_platform
+ elif (self.vitis_platform is None) and (self.board is not None):
+ return alveo_default_platform[self.board]
+ else:
+ raise Exception(
+ "Could not resolve Vitis platform:"
+ " need either board or vitis_platform specified"
+ )
+
def _resolve_verification_steps(self):
if self.verify_steps is None:
return []
diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py
index 9fc37dec2..771424b5d 100644
--- a/src/finn/builder/build_dataflow_steps.py
+++ b/src/finn/builder/build_dataflow_steps.py
@@ -644,7 +644,7 @@ def step_synthesize_bitfile(model: ModelWrapper, cfg: DataflowBuildConfig):
VitisBuild(
cfg._resolve_fpga_part(),
cfg.synth_clk_period_ns,
- cfg.vitis_platform,
+ cfg._resolve_vitis_platform(),
strategy=cfg._resolve_vitis_opt_strategy(),
enable_debug=cfg.enable_hw_debug,
floorplan_file=cfg.vitis_floorplan_file,
--
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