From d04e15abd374eea65778502a428db8bf108b48cb Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 24 Aug 2022 13:22:58 +0200
Subject: [PATCH] [FIFO] round up depth to power-of-2 for impl_style=vivado
---
.../custom_op/fpgadataflow/streamingfifo.py | 28 +++++++++++++++----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py
index a7c3cd0be..06b557982 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfifo.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py
@@ -73,6 +73,22 @@ class StreamingFIFO(HLSCustomOp):
return my_attrs
+ def get_adjusted_depth(self):
+ impl = self.get_nodeattr("impl_style")
+ depth = self.get_nodeattr("depth")
+ if impl == "vivado":
+ old_depth = depth
+ # round up depth to nearest power-of-2
+ # Vivado FIFO impl may fail otherwise
+ depth = (1 << (depth - 1).bit_length()) if impl == "vivado" else depth
+ if old_depth != depth:
+ warnings.warn(
+ "%s: rounding-up FIFO depth from %d to %d for impl_style=vivado"
+ % (self.onnx_node.name, old_depth, depth)
+ )
+
+ return depth
+
def make_shape_compatible_op(self, model):
exp_ishape = self.get_normal_input_shape()
oshape = self.get_normal_output_shape()
@@ -181,7 +197,7 @@ class StreamingFIFO(HLSCustomOp):
self.code_gen_dict.clear()
def get_normal_input_shape(self):
- depth = self.get_nodeattr("depth")
+ depth = self.get_adjusted_depth()
# depth has to be between 2 and 256 with the current
# StreamingFIFO implementation
assert depth >= 2, """Depth is too low"""
@@ -328,7 +344,7 @@ class StreamingFIFO(HLSCustomOp):
elif impl_style == "vivado":
cmd = []
node_name = self.onnx_node.name
- depth = self.get_nodeattr("depth")
+ depth = self.get_adjusted_depth()
ram_style = self.get_nodeattr("ram_style")
# create a hierarchy for this layer, with the same port names
clk_name = self.get_verilog_top_module_intf_names()["clk"][0]
@@ -393,7 +409,7 @@ class StreamingFIFO(HLSCustomOp):
"""Calculates resource estimation for BRAM"""
impl = self.get_nodeattr("impl_style")
ram_type = self.get_nodeattr("ram_style")
- depth = self.get_nodeattr("depth")
+ depth = self.get_adjusted_depth()
W = self.get_instream_width()
if impl == "rtl" or (impl == "vivado" and ram_type != "block"):
@@ -418,7 +434,7 @@ class StreamingFIFO(HLSCustomOp):
impl = self.get_nodeattr("impl_style")
ram_type = self.get_nodeattr("ram_style")
- depth = self.get_nodeattr("depth")
+ depth = self.get_adjusted_depth()
W = self.get_instream_width()
if impl == "rtl" or (impl == "vivado" and ram_type != "ultra"):
@@ -428,7 +444,7 @@ class StreamingFIFO(HLSCustomOp):
return (math.ceil(depth / 4096)) * (math.ceil(W / 72))
def bram_efficiency_estimation(self):
- depth = self.get_nodeattr("depth")
+ depth = self.get_adjusted_depth()
W = self.get_instream_width()
bram16_est = self.bram_estimation()
if bram16_est == 0:
@@ -441,7 +457,7 @@ class StreamingFIFO(HLSCustomOp):
"""Calculates resource estimations for LUTs"""
impl = self.get_nodeattr("impl_style")
ram_type = self.get_nodeattr("ram_style")
- depth = self.get_nodeattr("depth")
+ depth = self.get_adjusted_depth()
W = self.get_instream_width()
address_luts = 2 * math.ceil(math.log(depth, 2))
--
GitLab