From cfcbc6b544c0c20d7b897c697dd53dd033e391de Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Wed, 22 Sep 2021 10:29:01 +0200
Subject: [PATCH] [Zynq, Vitis] set instance_name, handle 0-inp nodes, no
driver gen
---
src/finn/transformation/fpgadataflow/make_zynq_proj.py | 9 +++++----
src/finn/transformation/fpgadataflow/vitis_build.py | 9 +++++----
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
index 2d4ec536f..713045b38 100644
--- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
@@ -42,7 +42,6 @@ from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.fpgadataflow.insert_iodma import InsertIODMA
-from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
from finn.transformation.infer_data_layouts import InferDataLayouts
@@ -145,7 +144,10 @@ class MakeZYNQProject(Transformation):
# assume only one connection from each ip to the next
# all aximm allocated to DDR[0]
# all kernels allocated to SLR0
- producer = model.find_producer(node.input[0])
+ if len(node.input) == 0:
+ producer = None
+ else:
+ producer = model.find_producer(node.input[0])
consumer = model.find_consumers(node.output[0])
# define kernel instances
# name kernels connected to graph inputs as idmaxx
@@ -202,6 +204,7 @@ class MakeZYNQProject(Transformation):
% (instance_names[node.name], axilite_intf_name)
)
axilite_idx += 1
+ sdp_node.set_nodeattr("instance_name", instance_names[node.name])
config.append(
"connect_bd_net [get_bd_pins %s/ap_clk] "
@@ -350,6 +353,4 @@ class ZynqBuild(Transformation):
# set platform attribute for correct remote execution
model.set_metadata_prop("platform", "zynq-iodma")
- # create driver
- model = model.transform(MakePYNQDriver(platform="zynq-iodma"))
return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/vitis_build.py b/src/finn/transformation/fpgadataflow/vitis_build.py
index 502b6f2bf..f47a3ad96 100644
--- a/src/finn/transformation/fpgadataflow/vitis_build.py
+++ b/src/finn/transformation/fpgadataflow/vitis_build.py
@@ -43,7 +43,6 @@ from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.fpgadataflow.insert_iodma import InsertIODMA
-from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.general import (
GiveReadableTensorNames,
@@ -207,7 +206,10 @@ class VitisLink(Transformation):
# has axis, aximm and axilite
# everything else is axis-only
# assume only one connection from each ip to the next
- producer = model.find_producer(node.input[0])
+ if len(node.input) == 0:
+ producer = None
+ else:
+ producer = model.find_producer(node.input[0])
consumer = model.find_consumers(node.output[0])
# define kernel instances
# name kernels connected to graph inputs as idmaxx
@@ -223,6 +225,7 @@ class VitisLink(Transformation):
else:
instance_names[node.name] = node.name
config.append("nk=%s:1:%s" % (node.name, instance_names[node.name]))
+ sdp_node.set_nodeattr("instance_name", instance_names[node.name])
# explicitly assign SLRs if the slr attribute is not -1
node_slr = sdp_node.get_nodeattr("slr")
if node_slr != -1:
@@ -439,6 +442,4 @@ class VitisBuild(Transformation):
# set platform attribute for correct remote execution
model.set_metadata_prop("platform", "alveo")
- # create driver
- model = model.transform(MakePYNQDriver(platform="alveo"))
return (model, False)
--
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