From cf86258fb469a27f271cf95fa4530c8c5849460f Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Fri, 28 Aug 2020 00:05:12 +0200
Subject: [PATCH] [Zynq] fix ZynqBuild link script for UltraScale+ parts
---
src/finn/transformation/fpgadataflow/templates.py | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index 1c449919f..35ed8cd55 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -397,10 +397,10 @@ if {%d == 1} {
}
#finalize clock and reset connections for interconnects
-set i 0
-while {$i < $NUM_AXILITE} {
- apply_bd_automation -quiet -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ps/FCLK_CLK0} Freq {} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/M0${i}_ACLK]
- incr i
+if {$ZYNQ_TYPE == "zynq_us+"} {
+ apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ps/pl_clk0} } [get_bd_pins axi_interconnect_0/M*_ACLK]
+} elseif {$ZYNQ_TYPE == "zynq_7000"} {
+ apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ps/FCLK_CLK0} } [get_bd_pins axi_interconnect_0/M*_ACLK]
}
save_bd_design
--
GitLab