From cf25f7e1eaa7a0a9027dffa9b6300ec42e18db27 Mon Sep 17 00:00:00 2001
From: Lucian Petrica <lucianp@xilinx.com>
Date: Fri, 4 Sep 2020 16:05:44 +0000
Subject: [PATCH] Fixed rtlsim (node-by-node and stitched) for decoupled
memories
---
src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py | 3 ++-
src/finn/transformation/fpgadataflow/create_stitched_ip.py | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index ea6922123..ee4990897 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -743,8 +743,9 @@ class StreamingFCLayer_Batch(HLSCustomOp):
wei = npy_to_rtlsim_input(
"{}/weights.npy".format(code_gen_dir), export_wdt, wnbits
)
+ num_w_reps = np.prod(self.get_nodeattr("numInputVectors"))
io_dict = {
- "inputs": {"in0": inp, "weights": wei},
+ "inputs": {"in0": inp, "weights": np.tile(wei, num_w_reps)},
"outputs": {"out": []},
}
self.rtlsim_multi_io(sim, io_dict)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 6e9ce3563..aa5de589a 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -408,7 +408,7 @@ class CreateStitchedIP(Transformation):
tcl.append("ipx::update_checksums [ipx::find_open_core %s]" % block_vlnv)
tcl.append("ipx::save_core [ipx::find_open_core %s]" % block_vlnv)
# export list of used Verilog files (for rtlsim later on)
- tcl.append("set all_v_files [get_files -filter {FILE_TYPE == Verilog}]")
+ tcl.append("set all_v_files [get_files -filter {FILE_TYPE == Verilog && USED_IN_SYNTHESIS == 1} ]")
v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
tcl.append("set fp [open %s w]" % v_file_list)
# write each verilog filename to all_verilog_srcs.txt
--
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