From ccb04f3a86b36d19a581352eb2626bb2f6666762 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Tue, 21 Apr 2020 21:39:48 +0100
Subject: [PATCH] [PYNQ] connect AXI lite port into shell
---
src/finn/transformation/fpgadataflow/make_pynq_proj.py | 2 ++
src/finn/transformation/fpgadataflow/templates.py | 5 ++++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 9921ce7ca..1e479f24d 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -108,6 +108,7 @@ class MakePYNQProject(Transformation):
out_if_name = "out_r_0"
clk_name = "ap_clk_0"
nrst_name = "ap_rst_n_0"
+ axi_lite_if_name = "s_axi_control_0"
vivado_ip_cache = os.getenv("VIVADO_IP_CACHE", default="")
# create a temporary folder for the project
@@ -129,6 +130,7 @@ class MakePYNQProject(Transformation):
out_if_name,
clk_name,
nrst_name,
+ axi_lite_if_name,
vivado_ip_cache,
)
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index 4a7845ee4..d72f607d8 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -35,6 +35,7 @@ variable config_ip_bytes_out
variable config_ip_axis_name_in
variable config_ip_axis_name_out
variable config_ip_use_axilite
+variable config_ip_axilite_name
variable config_ip_project_dir
variable config_output_products_dir
variable config_remote_cache
@@ -67,7 +68,9 @@ set config_ip_clk_name %s
# the name of the active-low reset signal
set config_ip_nrst_name %s
# whether the IP needs an AXI Lite interface for control
-set config_ip_use_axilite 0
+set config_ip_use_axilite 1
+# name of AXI Lite interface
+set config_ip_axilite_name %s
# Vivado OOC IP cache
set config_remote_cache "%s"
"""
--
GitLab