From cb0bf3cbec75701d9ec910279c9dd6369f15c27b Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@amd.com>
Date: Sun, 16 Oct 2022 17:38:58 +0300
Subject: [PATCH] [Pad] switch top-level template SystemVerilog->Verilog
this keeps Vivado happy for interface inference for blocks
---
.../hdl/{fmpadding_template.sv => fmpadding_template.v} | 0
src/finn/custom_op/fpgadataflow/fmpadding_rtl.py | 9 +++++----
2 files changed, 5 insertions(+), 4 deletions(-)
rename finn-rtllib/fmpadding/hdl/{fmpadding_template.sv => fmpadding_template.v} (100%)
diff --git a/finn-rtllib/fmpadding/hdl/fmpadding_template.sv b/finn-rtllib/fmpadding/hdl/fmpadding_template.v
similarity index 100%
rename from finn-rtllib/fmpadding/hdl/fmpadding_template.sv
rename to finn-rtllib/fmpadding/hdl/fmpadding_template.v
diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py
index 0b1556260..0ca11c6be 100644
--- a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py
+++ b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py
@@ -293,7 +293,7 @@ class FMPadding_rtl(HLSCustomOp):
def generate_hdl(self):
rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fmpadding/hdl"
- template_path = rtlsrc + "/fmpadding_template.sv"
+ template_path = rtlsrc + "/fmpadding_template.v"
dims = self.get_nodeattr("ImgDim")
pads = self.get_nodeattr("Padding")
chans = self.get_nodeattr("NumChannels")
@@ -313,7 +313,7 @@ class FMPadding_rtl(HLSCustomOp):
template = template.replace(key, str(code_gen_dict[key_name]))
with open(
- os.path.join(code_gen_dir, self.get_verilog_top_module_name() + ".sv"),
+ os.path.join(code_gen_dir, self.get_verilog_top_module_name() + ".v"),
"w",
) as f:
f.write(template)
@@ -341,7 +341,7 @@ class FMPadding_rtl(HLSCustomOp):
"fmpadding_axi.sv",
"fmpadding.sv",
"axi2we.sv",
- self.get_nodeattr("gen_top_module") + ".sv",
+ self.get_nodeattr("gen_top_module") + ".v",
]
# build the Verilator emu library
@@ -363,7 +363,8 @@ class FMPadding_rtl(HLSCustomOp):
sourcefiles = [
"fmpadding_axi.sv",
"fmpadding.sv",
- self.get_nodeattr("gen_top_module") + ".sv",
+ "axi2we.sv",
+ self.get_nodeattr("gen_top_module") + ".v",
]
sourcefiles = [os.path.join(code_gen_dir, f) for f in sourcefiles]
--
GitLab