From ca5b1ff762b25be90887ed3d896b0ce2e5f27b3c Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Mon, 27 Apr 2020 01:46:56 +0100
Subject: [PATCH] [Core] add rtlsim caching to stitched IP rtlsim
---
src/finn/core/rtlsim_exec.py | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/finn/core/rtlsim_exec.py b/src/finn/core/rtlsim_exec.py
index 0841fedeb..af84a75e2 100644
--- a/src/finn/core/rtlsim_exec.py
+++ b/src/finn/core/rtlsim_exec.py
@@ -35,11 +35,18 @@ from finn.util.fpgadataflow import (
pyverilate_stitched_ip,
)
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
+
def rtlsim_exec(model, execution_context):
"""Use PyVerilator to execute given model with stitched IP. The execution
context contains the input values."""
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
# ensure stitched ip project already exists
assert os.path.isfile(
model.get_metadata_prop("wrapper_filename")
@@ -74,7 +81,12 @@ def rtlsim_exec(model, execution_context):
packed_input = npy_to_rtlsim_input(i_tensor, i_dt, i_stream_w)
num_out_values = last_node.get_number_output_values()
# prepare pyverilator model
- sim = pyverilate_stitched_ip(model)
+ rtlsim_so = model.get_metadata_prop("rtlsim_so")
+ if (rtlsim_so is None) or (not os.path.isfile(rtlsim_so)):
+ sim = pyverilate_stitched_ip(model)
+ model.set_metadata_prop("rtlsim_so", sim.lib._name)
+ else:
+ sim = PyVerilator(rtlsim_so)
_reset_rtlsim(sim)
_toggle_clk(sim)
ret = _run_rtlsim(sim, packed_input, num_out_values, trace_file)
--
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