diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index c22a21ebdfd19178d3937de3a235dfadb7ee1d71..0e898f63db785f80cfce2683df0c9b6268e3ec7e 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -27,6 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
+import warnings
import subprocess
from finn.transformation import Transformation
@@ -48,9 +49,15 @@ class CreateStitchedIP(Transformation):
The packaged block design IP can be found under the ip subdirectory.
"""
- def __init__(self, fpgapart):
+ def __init__(self, fpgapart, clk_ns = 10.0):
super().__init__()
self.fpgapart = fpgapart
+ self.clk_ns = clk_ns
+ if float(clk_ns) not in [5.0, 10.0, 20.0]:
+ warnings.warn(
+ """The chosen frequency may lead to failure due to clock divider
+ constraints."""
+ )
def apply(self, model):
ip_dirs = ["list"]
@@ -147,8 +154,9 @@ class CreateStitchedIP(Transformation):
tcl.append('create_bd_design "%s"' % block_name)
tcl.extend(create_cmds)
tcl.extend(connect_cmds)
- # TODO get from Transformation arg or metadata_prop
- fclk_hz = 100 * 1000000
+ fclk_mhz = 1 / (self.clk_ns * 0.001)
+ fclk_hz = fclk_mhz * 1000000
+ model.set_metadata_prop("clk_ns", str(self.clk_ns))
tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk_0]" % fclk_hz)
tcl.append("regenerate_bd_layout")
tcl.append("validate_bd_design")
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 429b74bb5ea7e359ea720a0a86706f2c653ee6ce..91f6bd2c4ab19c736fcf21322979cac17a163f24 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -27,6 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
+import warnings
import subprocess
from finn.custom_op.registry import getCustomOp
@@ -110,8 +111,6 @@ class MakePYNQProject(Transformation):
nrst_name = "ap_rst_n_0"
axi_lite_if_name = "s_axi_control_0"
vivado_ip_cache = os.getenv("VIVADO_IP_CACHE", default="")
- # TODO get from Transformation arg or metadata_prop
- fclk_mhz = 100.0
# create a temporary folder for the project
vivado_pynq_proj_dir = make_build_dir(prefix="vivado_pynq_proj_")
@@ -120,6 +119,15 @@ class MakePYNQProject(Transformation):
synth_report_filename = vivado_pynq_proj_dir + "/synth_report.xml"
model.set_metadata_prop("vivado_synth_rpt", synth_report_filename)
+ # get metadata property clk_ns to calculate clock frequency
+ clk_ns = float(model.get_metadata_prop("clk_ns"))
+ if clk_ns not in [5.0, 10.0, 20.0]:
+ warnings.warn(
+ """The chosen frequency may lead to failure due to clock divider
+ constraints."""
+ )
+ fclk_mhz = 1 / (clk_ns * 0.001)
+
ip_config_tcl = templates.ip_config_tcl_template % (
vivado_pynq_proj_dir,
ip_dirs_str,
diff --git a/src/finn/transformation/fpgadataflow/prepare_ip.py b/src/finn/transformation/fpgadataflow/prepare_ip.py
index 00182773558ec30ab0271de6599615233785bdd7..7d5da940010896cde3a49bd45a79c69ef455bc72 100644
--- a/src/finn/transformation/fpgadataflow/prepare_ip.py
+++ b/src/finn/transformation/fpgadataflow/prepare_ip.py
@@ -27,7 +27,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
-
import finn.custom_op.registry as registry
from finn.transformation import Transformation
from finn.util.basic import make_build_dir
diff --git a/tests/end2end/test_end2end_cnv_w1a1.py b/tests/end2end/test_end2end_cnv_w1a1.py
index 703cb7ad92d6f4ec6dd67a05345f323a73ee178d..7dd45cbc732a50f8f41c1932601308f0dfd77c20 100644
--- a/tests/end2end/test_end2end_cnv_w1a1.py
+++ b/tests/end2end/test_end2end_cnv_w1a1.py
@@ -178,7 +178,7 @@ def test_end2end_cnv_w1a1_gen_hls_ip():
def test_end2end_cnv_w1a1_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CreateStitchedIP(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
model.save(build_dir + "/end2end_cnv_w1a1_ipstitch.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index b5f3f4e27ff24723db69f887cb7f1cce9c4df617..74cd46549f45b7512a03da450e011c4f2e80e16e 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -164,7 +164,7 @@ def test_end2end_tfc_w1a1_gen_hls_ip():
def test_end2end_tfc_w1a1_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CreateStitchedIP(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
model.save(build_dir + "/end2end_tfc_w1a1_ipstitch.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w1a2.py b/tests/end2end/test_end2end_tfc_w1a2.py
index ecc0d48a6af37bc2bdd48f9306976aa8582ca1b0..5ee2942845c41f4c6705b4ee3ecee89154d9faa9 100644
--- a/tests/end2end/test_end2end_tfc_w1a2.py
+++ b/tests/end2end/test_end2end_tfc_w1a2.py
@@ -156,7 +156,7 @@ def test_end2end_tfc_w1a2_gen_hls_ip():
def test_end2end_tfc_w1a2_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CreateStitchedIP(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch.onnx")
diff --git a/tests/end2end/test_end2end_tfc_w2a2.py b/tests/end2end/test_end2end_tfc_w2a2.py
index 8c13352d9e9d146d58d76b1cf1e17878f27513f5..2477318efd1e02b0865dadb40bad1a74ac8ea0b4 100644
--- a/tests/end2end/test_end2end_tfc_w2a2.py
+++ b/tests/end2end/test_end2end_tfc_w2a2.py
@@ -156,7 +156,7 @@ def test_end2end_tfc_w2a2_gen_hls_ip():
def test_end2end_tfc_w2a2_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CreateStitchedIP(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
model.save(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py
index fe27d7d4273be2b938e5bf70338bb374ce16b6b2..9158a0b0e72017b2468627e4f30fd3432c418d38 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fifo.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py
@@ -98,7 +98,7 @@ def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
assert y.shape == tuple(Shape), """The output shape is incorrect."""
model = model.transform(ReplaceVerilogRelPaths())
- model = model.transform(CreateStitchedIP(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
model = model.transform(MakePYNQProject(test_pynq_board))
model = model.transform(SynthPYNQProject())
model = model.transform(MakePYNQDriver())
diff --git a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
index f26ba428bf4cbe174c048dcd35a4d63dc58519ab..30b86d639ae52143320dfdfeb25488bae865b4d2 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
@@ -220,7 +220,7 @@ def test_fpgadataflow_ipstitch_do_stitch():
ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model.onnx"
)
model = model.transform(rvp.ReplaceVerilogRelPaths())
- model = model.transform(CreateStitchedIP(test_fpga_part))
+ model = model.transform(CreateStitchedIP(test_fpga_part, 5))
vivado_stitch_proj_dir = model.get_metadata_prop("vivado_stitch_proj")
assert vivado_stitch_proj_dir is not None
assert os.path.isdir(vivado_stitch_proj_dir)