From bfd1a8cc552c4564d899138d865e6e237a3a4952 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Mon, 12 Oct 2020 23:03:26 +0200
Subject: [PATCH] [StreamingFC] expose AXI lite streamer cfg port to top level
---
.../fpgadataflow/streamingfclayer_batch.py | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index 37c6ad489..3b601a4ea 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -1048,9 +1048,15 @@ class StreamingFCLayer_Batch(HLSCustomOp):
rst_name = self.get_verilog_top_module_intf_names()["rst"][0]
dout_name = self.get_verilog_top_module_intf_names()["m_axis"][0]
din_name = self.get_verilog_top_module_intf_names()["s_axis"][0]
+ axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0]
cmd.append("create_bd_cell -type hier %s" % node_name)
cmd.append("create_bd_pin -dir I -type clk /%s/%s" % (node_name, clk_name))
cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name))
+ cmd.append(
+ "create_bd_intf_pin -mode Slave "
+ "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s"
+ % (node_name, axilite_name)
+ )
cmd.append(
"create_bd_intf_pin -mode Master "
"-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s"
@@ -1125,6 +1131,11 @@ class StreamingFCLayer_Batch(HLSCustomOp):
"[get_bd_intf_pins %s/%s/%s]"
% (node_name, dout_name, node_name, node_name, dout_name)
)
+ cmd.append(
+ "connect_bd_intf_net [get_bd_intf_pins %s/%s] "
+ "[get_bd_intf_pins %s/%s/%s]"
+ % (node_name, axilite_name, node_name, strm_inst, axilite_name)
+ )
cmd.append("save_bd_design")
elif mem_mode == "const":
# base class impl sufficient for const mode
@@ -1138,4 +1149,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
mem_mode = self.get_nodeattr("mem_mode")
if mem_mode == "external":
intf_names["s_axis"] = ["in0_V_V", "weights_V_V"]
+ if mem_mode == "decoupled":
+ intf_names["axilite"] = ["s_axilite"]
+
return intf_names
--
GitLab