From b9d5dc18e391f9717991231267b25eb454d09db7 Mon Sep 17 00:00:00 2001
From: Lucian Petrica <lucianp@xilinx.com>
Date: Thu, 14 May 2020 17:28:54 +0000
Subject: [PATCH] Changed how pyverilator is called, to support Vivado 2019.2
---
src/finn/custom_op/fpgadataflow/__init__.py | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py
index d47b687b6..51a3bc0c2 100644
--- a/src/finn/custom_op/fpgadataflow/__init__.py
+++ b/src/finn/custom_op/fpgadataflow/__init__.py
@@ -122,18 +122,23 @@ class HLSCustomOp(CustomOp):
code_gen_dir != ""
), """Node attribute "code_gen_dir_ipgen" is
not set. Please run HLSSynthIP first."""
- verilog_file = self.get_verilog_top_filename()
- assert os.path.isfile(verilog_file), "Cannot find top-level Verilog file."
+
+ verilog_path = "{}/project_{}/sol1/impl/verilog/".format(
+ code_gen_dir, self.onnx_node.name
+ )
+
+ verilog_files = []
+ for f in os.listdir(verilog_path):
+ if f.endswith(".v"):
+ verilog_files += [f]
+
# build the Verilator emu library
sim = PyVerilator.build(
- verilog_file,
+ verilog_files,
build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"),
- verilog_path=[
- "{}/project_{}/sol1/impl/verilog/".format(
- code_gen_dir, self.onnx_node.name
- )
- ],
+ verilog_path=[verilog_path],
trace_depth=get_rtlsim_trace_depth(),
+ top_module_name=self.get_verilog_top_module_name(),
)
# save generated lib filename in attribute
self.set_nodeattr("rtlsim_so", sim.lib._name)
--
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