From ae5cb636a00b970ae1b560cc35d93b2110b33c3e Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Sat, 13 Nov 2021 13:35:08 +0100
Subject: [PATCH] [Build] pass large_fifo_mem_style correctly
---
src/finn/builder/build_dataflow_steps.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py
index c977f15e7..9fc37dec2 100644
--- a/src/finn/builder/build_dataflow_steps.py
+++ b/src/finn/builder/build_dataflow_steps.py
@@ -451,7 +451,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig):
InsertAndSetFIFODepths(
cfg._resolve_fpga_part(),
cfg._resolve_hls_clk_period(),
- vivado_ram_style=cfg.large_fifo_mem_style.value,
+ vivado_ram_style=cfg.large_fifo_mem_style,
)
)
else:
--
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