diff --git a/.gitignore b/.gitignore
index 91879240b36709b5c827ec951366cc55ad515cce..0411de3941d790fd1668fe2328b248cd3c09be08 100644
--- a/.gitignore
+++ b/.gitignore
@@ -83,3 +83,6 @@ MANIFEST
/finn-hlslib/
/pyverilator/
/PYNQ-HelloWorld/
+
+# Jenkins cfg dir
+/docker/jenkins_home
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 8e4e82db3a046e454373c2f0b58d55865cda9c5b..c513c5493d674b067b82fdae9e675d7f9b6eb024 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -27,7 +27,8 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
exclude: '^docs/conf.py'
-
+default_language_version:
+ python: python3
repos:
# black
- repo: https://github.com/ambv/black
diff --git a/AUTHORS.rst b/AUTHORS.rst
index a87cf170b065879f0c5e01e4726bc57608e5c4f2..e231e61d38991e11e2e43a7c9a3a78c50c878244 100644
--- a/AUTHORS.rst
+++ b/AUTHORS.rst
@@ -2,6 +2,7 @@
Contributors
============
-* Yaman Umuroglu
-* Jakoba Petri-Koenig
-* Andrea Rigoni
+* Yaman Umuroglu (@maltanar)
+* Jakoba Petri-Koenig (@auphelia)
+* Andrea Rigoni (@AndreaRigoni)
+* Hendrik Borras (@HenniOVP)
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
new file mode 100644
index 0000000000000000000000000000000000000000..f12dafa857b8a99493d7266ad029bec3f725d9ec
--- /dev/null
+++ b/CONTRIBUTING.md
@@ -0,0 +1,34 @@
+We welcome contributions to FINN.
+
+Please follow the steps below and be sure that your contribution complies with our guidelines.
+
+1. Share your proposal via <a href="https://github.com/Xilinx/finn/issues" target="_blank">Github issues</a>. If you are looking for some issues to get started with, we have a list of <a href="https://github.com/Xilinx/finn/labels/good%20first%20issue">good first issues</a> in the issue tracker. Feel free to ask questions on the <a href="https://gitter.im/xilinx-finn/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge">FINN gitter channel as well</a>.
+
+ We welcome submissions to:
+
+ 1. The FINN flow like additional custom ONNX nodes, transformation and analysis passes.
+ 2. Contributions to the documentation and Jupyter notebooks
+
+ To ensure clean separation of toolflow and examples, we do not keep example networks in this repo. If you want to add example networks, we ask you to make them into a separate repo and use FINN as a dependency -- we'll be happy to add it to the list of <a href="https://xilinx.github.io/finn/community">FINN community projects</a>.
+
+2. Submitting your pull request:
+
+ 1. Fork this repository to your own GitHub account using the *fork* button above.
+
+ 2. Clone the fork to your local computer using *git clone*. Checkout the branch you want to work on.
+
+ 3. Please install <a href="https://pre-commit.com/" target="_blank">pre-commit</a> to ensure your code is formatted to our style guidelines. The hooks we use for pre-commit can be found in <a href="https://github.com/Xilinx/finn/blob/master/.pre-commit-config.yaml" target="_blank">this file</a>
+
+ 4. Modify the Python source code, Jupyter notebooks and Sphinx documentation etc. as needed.
+
+ 5. Use *git add*, *git commit*, *git push* to add changes to your fork.
+
+ 6. If you are introducing new functionality, add at least one unit test under the `test/` folder and make sure it passes before you submit the pull request.
+
+ 7. Submit a pull request by clicking the *pull request* button on your GitHub repo:
+ 1. The <a href="https://github.com/Xilinx/finn" target="_blank">master branch</a> should always be treated as stable and clean. Only hot fixes are allowed to be pull-requested. The hot fix is supposed to be very important such that without this fix, a lot of things will break.
+ 2. For new features, smaller bug fixes, doc updates, and many other fixes, users should pull request against the <a href="https://github.com/Xilinx/finn/tree/dev" target="_blank">development branch</a>.
+
+3. We will review your contribution and, if any additional fixes or modifications are
+necessary, may provide feedback to guide you. When accepted, your pull request will
+be merged to the repository. If you have more questions please contact us via the <a href="https://gitter.im/xilinx-finn/community" target="_blank">FINN gitter channel</a>.
diff --git a/docker/Dockerfile.finn_ci b/docker/Dockerfile.finn_ci
new file mode 100644
index 0000000000000000000000000000000000000000..fb257b05c7c5e63922fe9c51241c18ab671ec0ba
--- /dev/null
+++ b/docker/Dockerfile.finn_ci
@@ -0,0 +1,82 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+FROM pytorch/pytorch:1.1.0-cuda10.0-cudnn7.5-devel
+MAINTAINER Yaman Umuroglu <yamanu@xilinx.com>
+ARG PYTHON_VERSION=3.6
+ARG BUILD_PATH
+ARG FINN_CI_BRANCH
+
+WORKDIR /workspace
+
+RUN apt-get update
+RUN apt-get -y upgrade
+RUN apt-get install -y build-essential libglib2.0-0 libsm6 libxext6 libxrender-dev
+RUN apt install verilator
+RUN apt-get -y install sshpass
+RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config
+
+# cloning dependency repos
+# Brevitas
+RUN git clone https://github.com/Xilinx/brevitas.git /workspace/brevitas
+# Brevitas examples
+RUN git clone https://github.com/maltanar/brevitas_cnv_lfc.git /workspace/brevitas_cnv_lfc
+# CNPY
+RUN git clone https://github.com/rogersce/cnpy.git /workspace/cnpy
+# FINN hlslib
+RUN git clone https://github.com/maltanar/finn-hlslib.git /workspace/finn-hlslib
+# PyVerilator
+RUN git clone https://github.com/maltanar/pyverilator /workspace/pyverilator
+# PYNQ-HelloWorld
+RUN git clone https://github.com/maltanar/PYNQ-HelloWorld.git /workspace/PYNQ-HelloWorld
+
+# checkout desired FINN branch for testing
+RUN git clone --branch $FINN_CI_BRANCH https://github.com/Xilinx/finn /workspace/finn
+
+RUN pip install -r /workspace/finn/requirements.txt
+RUN apt update; apt install nano
+RUN pip install pytest-dependency
+
+ENV PYTHONPATH "${PYTHONPATH}:/workspace/finn/src"
+ENV PYTHONPATH "${PYTHONPATH}:/workspace/brevitas_cnv_lfc/training_scripts"
+ENV PYTHONPATH "${PYTHONPATH}:/workspace/brevitas"
+ENV PYTHONPATH "${PYTHONPATH}:/workspace/pyverilator"
+ENV PYNQSHELL_PATH "/workspace/PYNQ-HelloWorld/boards"
+ENV VIVADO_IP_CACHE "$BUILD_PATH/vivado_ip_cache"
+
+# colorful terminal output
+RUN echo "PS1='\[\033[1;36m\]\u\[\033[1;31m\]@\[\033[1;32m\]\h:\[\033[1;35m\]\w\[\033[1;31m\]\$\[\033[0m\] '" >> /root/.bashrc
+RUN mkdir -p $BUILD_PATH
+RUN mkdir -p $VIVADO_IP_CACHE
+
+WORKDIR /workspace/finn
+
+COPY finn_entrypoint.sh /usr/local/bin/
+RUN chmod 755 /usr/local/bin/finn_entrypoint.sh
+ENTRYPOINT ["finn_entrypoint.sh"]
+CMD ["bash"]
diff --git a/Dockerfile b/docker/Dockerfile.finn_dev
similarity index 76%
rename from Dockerfile
rename to docker/Dockerfile.finn_dev
index 9cbb364b936c27c09bcfab71ef3866dff23f95ee..48ad00a555aebf678f68036d1f5ec576f4c70c3f 100644
--- a/Dockerfile
+++ b/docker/Dockerfile.finn_dev
@@ -29,81 +29,78 @@
FROM pytorch/pytorch:1.1.0-cuda10.0-cudnn7.5-devel
MAINTAINER Yaman Umuroglu <yamanu@xilinx.com>
ARG PYTHON_VERSION=3.6
+ARG GID
+ARG GNAME
+ARG UNAME
+ARG UID
+ARG PASSWD
+ARG JUPYTER_PORT
+ARG NETRON_PORT
+
+EXPOSE $JUPYTER_PORT
+EXPOSE $NETRON_PORT
WORKDIR /workspace
+RUN apt-get update
+RUN apt-get -y upgrade
+RUN apt-get install -y build-essential libglib2.0-0 libsm6 libxext6 libxrender-dev
+RUN apt-get install verilator
+RUN apt-get install nano
+RUN apt-get -y install sshpass
+RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config
+
COPY requirements.txt .
RUN pip install -r requirements.txt
RUN rm requirements.txt
-RUN apt update; apt install nano
RUN pip install jupyter
RUN pip install netron
RUN pip install matplotlib
RUN pip install pytest-dependency
-RUN apt-get update
-RUN apt-get -y upgrade
-RUN apt-get install -y build-essential libglib2.0-0 libsm6 libxext6 libxrender-dev
-RUN apt install verilator
-RUN apt-get -y install sshpass
-RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config
RUN pip install sphinx
RUN pip install sphinx_rtd_theme
-# cloning dependency repos
-# Brevitas
-RUN git clone --branch feature/finn_onnx_export https://github.com/Xilinx/brevitas.git /workspace/brevitas
-RUN git -C /workspace/brevitas checkout ed1a3b70a14a91853066ece630421e89660d93e9
+# switch user
+RUN groupadd -g $GID $GNAME
+RUN useradd -M -u $UID $UNAME -g $GNAME
+RUN usermod -aG sudo $UNAME
+RUN echo "$UNAME:$PASSWD" | chpasswd
+RUN echo "root:$PASSWD" | chpasswd
+RUN ln -s /workspace /home/$UNAME
+RUN chown -R $UNAME:$GNAME /home/$UNAME
+USER $UNAME
+# cloning dependency repos (as user)
+# Brevitas
+RUN git clone https://github.com/Xilinx/brevitas.git /workspace/brevitas
# Brevitas examples
RUN git clone https://github.com/maltanar/brevitas_cnv_lfc.git /workspace/brevitas_cnv_lfc
-RUN git -C /workspace/brevitas_cnv_lfc checkout a443708b382cbcfd69d19c9fc3fe94b2a2c03d71
-
# CNPY
RUN git clone https://github.com/rogersce/cnpy.git /workspace/cnpy
-RUN git -C /workspace/cnpy checkout 4e8810b1a8637695171ed346ce68f6984e585ef4
-
# FINN hlslib
-RUN git clone https://github.com/Xilinx/finn-hlslib.git /workspace/finn-hlslib
-RUN git -C /workspace/finn-hlslib checkout b5dc957a16017b8356a7010144b0a4e2f8cfd124
-
+RUN git clone https://github.com/maltanar/finn-hlslib.git /workspace/finn-hlslib
# PyVerilator
RUN git clone https://github.com/maltanar/pyverilator /workspace/pyverilator
-RUN git -C /workspace/pyverilator checkout 307fc5c82db748620836307a2002fdc9fe170226
-
# PYNQ-HelloWorld
RUN git clone https://github.com/maltanar/PYNQ-HelloWorld.git /workspace/PYNQ-HelloWorld
-RUN git -C /workspace/PYNQ-HelloWorld checkout ef4c438dff4bd346e5f6b8d4eddfd1c8a3999c03
-# Note that we expect the cloned finn directory on the host to be
-# mounted on /workspace/finn -- see run-docker.sh for an example
-# of how to do this.
-# This branch assumes the same for brevitas and brevitas_cnv_lfc for easier
-# co-development.
+# for this developer-oriented Docker container we assume the FINN repo is cloned and mounted from the host
+# at /workspace/finn -- see run-docker.sh for an example of how to do this.
ENV PYTHONPATH "${PYTHONPATH}:/workspace/finn/src"
ENV PYTHONPATH "${PYTHONPATH}:/workspace/brevitas_cnv_lfc/training_scripts"
ENV PYTHONPATH "${PYTHONPATH}:/workspace/brevitas"
ENV PYTHONPATH "${PYTHONPATH}:/workspace/pyverilator"
ENV PYNQSHELL_PATH "/workspace/PYNQ-HelloWorld/boards"
-ARG GID
-ARG GNAME
-ARG UNAME
-ARG UID
-ARG PASSWD
-ARG JUPYTER_PORT
-ARG NETRON_PORT
+WORKDIR /home/$UNAME/finn
+RUN echo "PS1='\[\033[1;36m\]\u\[\033[1;31m\]@\[\033[1;32m\]\h:\[\033[1;35m\]\w\[\033[1;31m\]\$\[\033[0m\] '" >> /home/$UNAME/.bashrc
+RUN echo "source \$VIVADO_PATH/settings64.sh" >> /home/$UNAME/.bashrc
-RUN groupadd -g $GID $GNAME
-RUN useradd -M -u $UID $UNAME -g $GNAME
-RUN usermod -aG sudo $UNAME
-RUN echo "$UNAME:$PASSWD" | chpasswd
-RUN echo "root:$PASSWD" | chpasswd
-RUN ln -s /workspace /home/$UNAME
-RUN chown -R $UNAME:$GNAME /home/$UNAME
+# copy entrypoint script
+USER root
+COPY docker/finn_entrypoint.sh /usr/local/bin/
+RUN chmod 755 /usr/local/bin/finn_entrypoint.sh
USER $UNAME
-RUN echo "source \$VIVADO_PATH/settings64.sh" >> /home/$UNAME/.bashrc
-RUN echo "PS1='\[\033[1;36m\]\u\[\033[1;31m\]@\[\033[1;32m\]\h:\[\033[1;35m\]\w\[\033[1;31m\]\$\[\033[0m\] '" >> /home/$UNAME/.bashrc
-EXPOSE $JUPYTER_PORT
-EXPOSE $NETRON_PORT
-WORKDIR /home/$UNAME/finn
+ENTRYPOINT ["finn_entrypoint.sh"]
+CMD ["bash"]
diff --git a/docker/Dockerfile.jenkins b/docker/Dockerfile.jenkins
new file mode 100644
index 0000000000000000000000000000000000000000..e1939b642e1493ee97daf6472009649d3634632f
--- /dev/null
+++ b/docker/Dockerfile.jenkins
@@ -0,0 +1,11 @@
+FROM jenkins/jenkins:lts
+# if we want to install via apt
+USER root
+RUN apt-get update
+RUN apt-get install -y gnupg-agent curl ca-certificates apt-transport-https software-properties-common
+RUN curl -fsSL https://download.docker.com/linux/debian/gpg | apt-key add -
+RUN add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/debian $(lsb_release -cs) stable"
+RUN apt-get update
+RUN apt-get install -y docker-ce-cli
+# drop back to the regular jenkins user - good practice
+USER jenkins
diff --git a/docker/Jenkinsfile b/docker/Jenkinsfile
new file mode 100644
index 0000000000000000000000000000000000000000..e64280222a6d2e558f00d20a25a4a79d55526a97
--- /dev/null
+++ b/docker/Jenkinsfile
@@ -0,0 +1,54 @@
+pipeline {
+ agent any
+ parameters {
+ string(name: 'FINN_CI_BRANCH', defaultValue: '', description: 'FINN branch to build')
+ string(name: 'VIVADO_PATH', defaultValue: '', description: 'Path to Vivado installation')
+ string(name: 'PYNQ_BOARD', defaultValue: 'Pynq-Z1', description: 'PYNQ board type')
+ string(name: 'PYNQ_IP', defaultValue: '', description: 'PYNQ board IP address')
+ string(name: 'PYNQ_USERNAME', defaultValue: 'xilinx', description: 'PYNQ board username')
+ string(name: 'PYNQ_PASSWORD', defaultValue: 'xilinx', description: 'PYNQ board password')
+ string(name: 'PYNQ_TARGET_DIR', defaultValue: '/home/xilinx/finn', description: 'PYNQ board target deployment directory')
+ string(name: 'NUM_DEFAULT_WORKERS', defaultValue: '1', description: 'Number of cores for parallel transformations')
+ string(name: 'DOCKER_CMD', defaultValue: """python setup.py test""", description: 'Command to run')
+ }
+ environment {
+ DOCKER_TAG='finn_ci:$BUILD_ID'
+ DOCKER_INST_NAME='finn_ci_$BUILD_ID'
+ BUILD_PATH='/tmp/finn_ci_$BUILD_ID'
+ }
+ stages {
+ stage("Clone") {
+ steps {
+ git branch: "${params.FINN_CI_BRANCH}", url: 'https://github.com/Xilinx/finn.git'
+ }
+ }
+ stage('Build') {
+ steps {
+ sh """
+ docker build -t $DOCKER_TAG -f docker/Dockerfile.finn_ci \
+ --build-arg BUILD_PATH=$BUILD_PATH \
+ --build-arg FINN_CI_BRANCH=${params.FINN_CI_BRANCH} \
+ docker/
+ """
+ }
+ }
+ stage('Test') {
+ steps {
+ sh """
+ docker run --name $DOCKER_INST_NAME \
+ --hostname $DOCKER_INST_NAME \
+ -v ${params.VIVADO_PATH}:${params.VIVADO_PATH}:ro \
+ -e NUM_DEFAULT_WORKERS=${params.NUM_DEFAULT_WORKERS} \
+ -e FINN_INST_NAME=$DOCKER_INST_NAME \
+ -e VIVADO_PATH=${params.VIVADO_PATH} \
+ -e PYNQ_BOARD=${params.PYNQ_BOARD} \
+ -e PYNQ_IP=${params.PYNQ_IP} \
+ -e PYNQ_USERNAME=${params.PYNQ_USERNAME} \
+ -e PYNQ_PASSWORD=${params.PYNQ_PASSWORD} \
+ -e PYNQ_TARGET_DIR=${params.PYNQ_TARGET_DIR} \
+ $DOCKER_TAG ${params.DOCKER_CMD}
+ """
+ }
+ }
+ }
+}
diff --git a/docker/finn_entrypoint.sh b/docker/finn_entrypoint.sh
new file mode 100644
index 0000000000000000000000000000000000000000..035bba3b53d85a8457eff1e7c1a23e0efff60caa
--- /dev/null
+++ b/docker/finn_entrypoint.sh
@@ -0,0 +1,53 @@
+#!/bin/bash
+
+export XILINX_VIVADO=$VIVADO_PATH
+export SHELL=/bin/bash
+export FINN_ROOT=/workspace/finn
+
+GREEN='\033[0;32m'
+NC='\033[0m' # No Color
+
+gecho () {
+ echo -e "${GREEN}$1${NC}"
+}
+
+# checkout the correct dependency repo commits
+# the repos themselves are cloned in the Dockerfile
+BREVITAS_COMMIT=215cf44c76d562339fca368c8c3afee3110033e8
+BREVITAS_EXAMPLES_COMMIT=2059f96bd576bf71f32c757e7f92617a70190c90
+CNPY_COMMIT=4e8810b1a8637695171ed346ce68f6984e585ef4
+HLSLIB_COMMIT=6b88db826bb023937506913a23d964775a7606af
+PYVERILATOR_COMMIT=fb1afefa5b207acf6fec28f8abb72a862f2ca1d2
+PYNQSHELL_COMMIT=0c82a61b0ec1a07fa275a14146233824ded7a13d
+
+
+gecho "Setting up known-good commit versions for FINN dependencies"
+# Brevitas
+gecho "brevitas @ $BREVITAS_COMMIT"
+git -C /workspace/brevitas pull --quiet
+git -C /workspace/brevitas checkout $BREVITAS_COMMIT --quiet
+# Brevitas examples
+gecho "brevitas_cnv_lfc @ $BREVITAS_EXAMPLES_COMMIT"
+git -C /workspace/brevitas_cnv_lfc pull --quiet
+git -C /workspace/brevitas_cnv_lfc checkout $BREVITAS_EXAMPLES_COMMIT --quiet
+# CNPY
+gecho "cnpy @ $CNPY_COMMIT"
+git -C /workspace/cnpy pull --quiet
+git -C /workspace/cnpy checkout $CNPY_COMMIT --quiet
+# FINN hlslib
+gecho "finn-hlslib @ $HLSLIB_COMMIT"
+git -C /workspace/finn-hlslib pull --quiet
+git -C /workspace/finn-hlslib checkout $HLSLIB_COMMIT --quiet
+# PyVerilator
+gecho "PyVerilator @ $PYVERILATOR_COMMIT"
+git -C /workspace/pyverilator pull --quiet
+git -C /workspace/pyverilator checkout $PYVERILATOR_COMMIT --quiet
+# PYNQ-HelloWorld
+gecho "PYNQ shell @ $PYNQSHELL_COMMIT"
+git -C /workspace/PYNQ-HelloWorld pull --quiet
+git -C /workspace/PYNQ-HelloWorld checkout $PYNQSHELL_COMMIT --quiet
+
+# source Vivado env.vars
+source $VIVADO_PATH/settings64.sh
+
+exec "$@"
diff --git a/docker/launch-jenkins.sh b/docker/launch-jenkins.sh
new file mode 100755
index 0000000000000000000000000000000000000000..64dc1ec73f68e621cdd737595983b6b9a217f6fe
--- /dev/null
+++ b/docker/launch-jenkins.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+# defaults, can be overriden by environment variables
+# user to run Jenkins as -- see NOTE below regarding Docker access permissions
+: ${JENKINS_USER=jenkins}
+# port for Jenkins on host machine
+: ${JENKINS_PORT=8080}
+# make Jenkins config persistent by mounting into this folder
+: ${JENKINS_HOME=$(pwd)/jenkins_home}
+
+mkdir -p $JENKINS_HOME
+
+# build a Jenkins Docker image that also has the Docker CLI installed
+docker build -t finn_jenkins -f Dockerfile.jenkins .
+
+# launch Docker container mounted to local Docker socket
+# NOTE: we allow customizing the user (e.g. as root) to work around permission
+# issues, may not al
+docker run -u $JENKINS_USER -p $JENKINS_PORT:8080 -v /var/run/docker.sock:/var/run/docker.sock -v $JENKINS_HOME:/var/jenkins_home finn_jenkins
diff --git a/docs/finn/end_to_end_flow.rst b/docs/finn/end_to_end_flow.rst
index 1936aad186a96edbc6fe33dbccbe0c06826fab5f..fd6960a2f94774ab783cf1cff220ac604d9fbe92 100644
--- a/docs/finn/end_to_end_flow.rst
+++ b/docs/finn/end_to_end_flow.rst
@@ -11,7 +11,7 @@ As you can see in the picture, FINN has a high modularity and has the property t
:scale: 50%
:align: center
-The cylinder-like fields show the state of the network representation in the respective step. The rectangular fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into five blocks, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (pink block), followed by the preparation of the network (grey block) for the Vivado HLS and Vivado IPI (yellow block). There is also a section for testing and verification in software (green block) and the hardware generation and deployment on the PYNQ board (red block).
+The white fields show the state of the network representation in the respective step. The colored fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into five sections, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (green section), followed by the preparation of the network (blue section) for the Vivado HLS and Vivado IPI (orange section). There is also a section for testing and verification in software (red section) and the hardware generation and deployment on the PYNQ board (yellow section).
This example flow is covered in the `end2end_example <https://github.com/Xilinx/finn/tree/master/notebooks/end2end_example>`_ Jupyter notebooks.
For a more detailed overview about the different flow sections, please have a look at the corresponding pages:
diff --git a/docs/finn/example_networks.rst b/docs/finn/example_networks.rst
index e8b29a5fb862f6ebe917327a8f6c96edbf529b96..e4193668b4c77136c3acc70275260bc4e99de4e8 100644
--- a/docs/finn/example_networks.rst
+++ b/docs/finn/example_networks.rst
@@ -15,22 +15,22 @@ The rows in the table are different steps of the FINN end-to-end flow.
If a particular network is supported for a particular step in the current FINN
version, this is indicated by an x mark in the table.
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| FINN step | Basic test | TFC-w1a1 | TFC-w1a2 | CNV-w1a1 | CNV-w1a2 | CNV-w2a2 |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Export/Import | x | x | x | x | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Streamlining | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Convert to HLS layers | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Stitched IP | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| Hardware test | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| npysim | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| rtlsim node-by-node | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
-| rtlsim stitched IP | x | x | x | | | |
-+-----------------------+------------+----------+----------+----------+----------+----------+
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| FINN step | Basic test | TFC-w1a1 | TFC-w1a2 | TFC-w2a2 | CNV-w1a1 | CNV-w1a2 | CNV-w2a2 |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Export/Import | x | x | x | x | x | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Streamlining | x | x | x | x | x | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Convert to HLS layers | x | x | x | x | x | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Stitched IP | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| Hardware test | x | x | x | | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| npysim | x | x | x | x | x | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| rtlsim node-by-node | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
+| rtlsim stitched IP | x | x | x | x | | | |
++-----------------------+------------+----------+----------+----------+----------+----------+----------+
diff --git a/docs/finn/img/brevitas-export.png b/docs/finn/img/brevitas-export.png
index 94c05ebc85e7893f4dcecfc14f3d3d7a230c86a2..5c57353d717a78b641fc8e912c32635bd87b8ea5 100755
Binary files a/docs/finn/img/brevitas-export.png and b/docs/finn/img/brevitas-export.png differ
diff --git a/docs/finn/img/nw-prep.png b/docs/finn/img/nw-prep.png
index 8b31b14bdfd5c6f042aabde9c4f5fcbc5f513fd5..bed56ebc6d8b904df6b29e10c39a31e2c389cd0d 100755
Binary files a/docs/finn/img/nw-prep.png and b/docs/finn/img/nw-prep.png differ
diff --git a/docs/finn/img/pynq-deploy.png b/docs/finn/img/pynq-deploy.png
index ba8e889c040545ffdb0daf0a6cc01a2eef423db8..13fe30d9a7f8ed38cbbddf5ca3a6c8bdfdd4cb6b 100755
Binary files a/docs/finn/img/pynq-deploy.png and b/docs/finn/img/pynq-deploy.png differ
diff --git a/docs/finn/img/verification.png b/docs/finn/img/verification.png
index 71645fef72496258544641bb09e7b529656b8812..e95a4d98e3b6c5a46ad6d4c2749679831b740044 100755
Binary files a/docs/finn/img/verification.png and b/docs/finn/img/verification.png differ
diff --git a/docs/finn/img/vivado-synth.png b/docs/finn/img/vivado-synth.png
index b585910692f225ca8c4717ad0bab623534be0b4c..102f123c6354921d9a542b687a37d4682e5015e7 100755
Binary files a/docs/finn/img/vivado-synth.png and b/docs/finn/img/vivado-synth.png differ
diff --git a/docs/finn/source_code/finn.analysis.fpgadataflow.rst b/docs/finn/source_code/finn.analysis.fpgadataflow.rst
index e31723ca3802e1ba523131ddff8078662c06d54b..9c1b0dd99a324929f5c8dd182f7208c27baa5ba8 100644
--- a/docs/finn/source_code/finn.analysis.fpgadataflow.rst
+++ b/docs/finn/source_code/finn.analysis.fpgadataflow.rst
@@ -1,4 +1,3 @@
-***********************
Analysis - fpgadataflow
***********************
diff --git a/docs/finn/source_code/finn.analysis.rst b/docs/finn/source_code/finn.analysis.rst
index dbfeea2a9658957b2525016c387b7bc6aeb77608..9ce1b99990ed2facc430eaf318bb0480f7fba5e0 100644
--- a/docs/finn/source_code/finn.analysis.rst
+++ b/docs/finn/source_code/finn.analysis.rst
@@ -31,4 +31,3 @@ finn.analysis.verify\_custom\_nodes
:undoc-members:
:show-inheritance:
-
diff --git a/docs/finn/source_code/finn.core.rst b/docs/finn/source_code/finn.core.rst
index 78b461ee69efb6cac59eb4e9c1dbd5abc521191d..f9d59fc0f68a37761f4c7fa8b25f5ee016092a0a 100644
--- a/docs/finn/source_code/finn.core.rst
+++ b/docs/finn/source_code/finn.core.rst
@@ -54,4 +54,3 @@ finn.core.rtlsim\_exec
:members:
:undoc-members:
:show-inheritance:
-
diff --git a/docs/finn/source_code/finn.custom_op.fpgadataflow.rst b/docs/finn/source_code/finn.custom_op.fpgadataflow.rst
index f8c6274e40126a12f072b9c46c9e5748747f8121..7e9ebcbec1ebb958faa5b2cf1cdb87c02b17011b 100644
--- a/docs/finn/source_code/finn.custom_op.fpgadataflow.rst
+++ b/docs/finn/source_code/finn.custom_op.fpgadataflow.rst
@@ -13,7 +13,6 @@ Base Class
:undoc-members:
:show-inheritance:
-
finn.custom\_op.fpgadataflow.convolutioninputgenerator
------------------------------------------------------
@@ -22,6 +21,14 @@ finn.custom\_op.fpgadataflow.convolutioninputgenerator
:undoc-members:
:show-inheritance:
+finn.custom\_op.fpgadataflow.streamingdatawidthconverter\_batch
+---------------------------------------------------------------
+
+.. automodule:: finn.custom_op.fpgadataflow.streamingdatawidthconverter_batch
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
finn.custom\_op.fpgadataflow.streamingfclayer\_batch
----------------------------------------------------
diff --git a/docs/finn/source_code/finn.custom_op.rst b/docs/finn/source_code/finn.custom_op.rst
index e0a2c77213be8bd5eca4dce67d48c6b5950be9ba..cb436b1c1303020deeed1ca2f6dc2eb2f8678287 100644
--- a/docs/finn/source_code/finn.custom_op.rst
+++ b/docs/finn/source_code/finn.custom_op.rst
@@ -21,6 +21,23 @@ Base Class
:undoc-members:
:show-inheritance:
+
+finn.custom\_op.im2col
+----------------------
+
+.. automodule:: finn.custom_op.im2col
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
+finn.custom\_op.maxpoolnhwc
+---------------------------
+
+.. automodule:: finn.custom_op.maxpoolnhwc
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
finn.custom\_op.multithreshold
------------------------------
@@ -53,3 +70,4 @@ finn.custom\_op.xnorpopcount
:undoc-members:
:show-inheritance:
+
diff --git a/docs/finn/source_code/finn.rst b/docs/finn/source_code/finn.rst
index 1197c50a035b77ec24f51f9e95f6208db162db8e..6f6b591e1e6a4b7b3900b834c8f5ff2765644f52 100644
--- a/docs/finn/source_code/finn.rst
+++ b/docs/finn/source_code/finn.rst
@@ -14,3 +14,4 @@ Modules
finn.custom_op
finn.transformation
finn.util
+
diff --git a/docs/finn/source_code/finn.transformation.fpgadataflow.rst b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
index ba850d8fd3834ca86769925ddcf9cc958cdb4980..e80ddbdd05595ab3ca1e6a81da95f96e92f5452a 100644
--- a/docs/finn/source_code/finn.transformation.fpgadataflow.rst
+++ b/docs/finn/source_code/finn.transformation.fpgadataflow.rst
@@ -69,6 +69,14 @@ finn.transformation.fpgadataflow.hlssynth\_ipgen
:undoc-members:
:show-inheritance:
+finn.transformation.fpgadataflow.insert\_dwc
+--------------------------------------------
+
+.. automodule:: finn.transformation.fpgadataflow.insert_dwc
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
finn.transformation.fpgadataflow.insert\_tlastmarker
----------------------------------------------------
@@ -132,3 +140,4 @@ finn.transformation.fpgadataflow.templates
:members:
:undoc-members:
:show-inheritance:
+
diff --git a/docs/finn/source_code/finn.transformation.rst b/docs/finn/source_code/finn.transformation.rst
index c944cb478303719bfd3392567b2b07f65c40edd0..480c8030245ae5bc0add11ff629095b2d46ff225 100644
--- a/docs/finn/source_code/finn.transformation.rst
+++ b/docs/finn/source_code/finn.transformation.rst
@@ -32,6 +32,14 @@ finn.transformation.bipolar\_to\_xnor
:undoc-members:
:show-inheritance:
+finn.transformation.double\_to\_single\_float
+---------------------------------------------
+
+.. automodule:: finn.transformation.double_to_single_float
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
finn.transformation.fold\_constants
-----------------------------------
@@ -63,3 +71,12 @@ finn.transformation.infer\_shapes
:members:
:undoc-members:
:show-inheritance:
+
+finn.transformation.lower\_convs\_to\_matmul
+--------------------------------------------
+
+.. automodule:: finn.transformation.lower_convs_to_matmul
+ :members:
+ :undoc-members:
+ :show-inheritance:
+
diff --git a/docs/finn/source_code/finn.util.rst b/docs/finn/source_code/finn.util.rst
index 5a86918195cd41dfc83e7faeb7923c5703f4fe42..7bcfde705f35a0deb9bb82d2d24831f718802070 100644
--- a/docs/finn/source_code/finn.util.rst
+++ b/docs/finn/source_code/finn.util.rst
@@ -44,3 +44,4 @@ finn.util.test
:members:
:undoc-members:
:show-inheritance:
+
diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6b728c0555a4889b8e76d5759233d1109a3002bd
--- /dev/null
+++ b/finn-rtllib/memstream/component.xml
@@ -0,0 +1,1082 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>memstream</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>m_axis_0</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_0_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_0_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_0_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_1</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_1_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_1_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_1_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_2</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_2_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_2_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_2_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_3</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_3_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_3_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_3_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_4</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_4_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_4_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_4_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>m_axis_5</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_5_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_5_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m_axis_5_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>aresetn</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>aclk</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis_0:m_axis_1:m_axis_2:m_axis_3:m_axis_4:m_axis_5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>Verilog</spirit:language>
+ <spirit:modelName>memstream</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>ba6d3300</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>Verilog</spirit:language>
+ <spirit:modelName>memstream</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>54f61a0e</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>92c3ebfc</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>aclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
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diff --git a/finn-rtllib/memstream/hdl/Q_srl.v b/finn-rtllib/memstream/hdl/Q_srl.v
new file mode 100644
index 0000000000000000000000000000000000000000..6c619c51ceb4a99a077fc61c52ce81763cfd27f5
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/Q_srl.v
@@ -0,0 +1,325 @@
+// original source:
+// https://github.com/nachiket/tdfc/blob/master/verilog/queues/Q_srl_oreg3_prefull_SIMPLE.v
+
+
+// Copyright (c) 1999 The Regents of the University of California
+// Copyright (c) 2010 The Regents of the University of Pennsylvania
+// Copyright (c) 2011 Department of Electrical and Electronic Engineering, Imperial College London
+// Copyright (c) 2020 Xilinx
+//
+// Permission to use, copy, modify, and distribute this software and
+// its documentation for any purpose, without fee, and without a
+// written agreement is hereby granted, provided that the above copyright
+// notice and this paragraph and the following two paragraphs appear in
+// all copies.
+//
+// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+// DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING
+// LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF
+// SUCH DAMAGE.
+//
+// THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON
+// AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+//
+
+// Q_srl_oreg3_prefull_SIMPLE.v
+//
+// - In-page queue with parameterizable depth, bit width
+// - Stream I/O is triple (data, valid, back-pressure),
+// with EOS concatenated into the data
+// - Flow control for input & output is combinationally decoupled
+// - 2 <= depth <= 256
+// * (depth >= 2) is required to decouple I/O flow control,
+// where empty => no produce, full => no consume,
+// and depth 1 would ping-pong between the two at half rate
+// * (depth <= 256) can be modified
+// by changing ''synthesis loop_limit X'' below
+// and changing ''addrwidth'' or its log computation
+// - 1 <= width
+// - Queue storage is in SRL16E, up to depth 16 per LUT per bit-slice,
+// plus output register (for fast output)
+// - Queue addressing is done by ''addr'' up-down counter
+// - Queue fullness is checked by comparator (addr==depth)
+// - Queue fullness is pre-computed for next cycle
+// - Queue input back-pressure is pre-computed for next cycle
+// - Queue output valid (state!=state__empty) is pre-computed for next cycle
+// (necessary since SRL data output reg requires non-boolean state)
+// - FSM has 3 states (empty, one, more)
+// - When empty, continue to emit most recently emitted value (for debugging)
+//
+// - Queue slots used = / (state==state_empty) ? 0
+// | (state==state_one) ? 1
+// \ (state==state_more) ? addr+2
+// - Queue slots used <= depth
+// - Queue slots remaining = depth - used
+// = / (state==state_empty) ? depth
+// | (state==state_one) ? depth-1
+// \ (state==state_more) ? depth-2-addr
+//
+// - Synplify 7.1 / 8.0
+// - Eylon Caspi, 9/11/03, 8/18/04, 3/29/05
+
+
+`ifdef Q_srl
+`else
+`define Q_srl
+
+
+module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count);
+
+ parameter depth = 16; // - greatest #items in queue (2 <= depth <= 256)
+ parameter width = 16; // - width of data (i_d, o_d)
+
+ `define LOG2 ( (((depth)) ==0) ? 0 /* - depth==0 LOG2=0 */ \
+ : (((depth-1)>>0)==0) ? 0 /* - depth<=1 LOG2=0 */ \
+ : (((depth-1)>>1)==0) ? 1 /* - depth<=2 LOG2=1 */ \
+ : (((depth-1)>>2)==0) ? 2 /* - depth<=4 LOG2=2 */ \
+ : (((depth-1)>>3)==0) ? 3 /* - depth<=8 LOG2=3 */ \
+ : (((depth-1)>>4)==0) ? 4 /* - depth<=16 LOG2=4 */ \
+ : (((depth-1)>>5)==0) ? 5 /* - depth<=32 LOG2=5 */ \
+ : (((depth-1)>>6)==0) ? 6 /* - depth<=64 LOG2=6 */ \
+ : (((depth-1)>>7)==0) ? 7 /* - depth<=128 LOG2=7 */ \
+ : 8) /* - depth<=256 LOG2=8 */
+
+// parameter addrwidth = LOG2; // - width of queue addr
+
+ parameter addrwidth =
+ ( (((depth)) ==0) ? 0 // - depth==0 LOG2=0
+ : (((depth-1)>>0)==0) ? 0 // - depth<=1 LOG2=0
+ : (((depth-1)>>1)==0) ? 1 // - depth<=2 LOG2=1
+ : (((depth-1)>>2)==0) ? 2 // - depth<=4 LOG2=2
+ : (((depth-1)>>3)==0) ? 3 // - depth<=8 LOG2=3
+ : (((depth-1)>>4)==0) ? 4 // - depth<=16 LOG2=4
+ : (((depth-1)>>5)==0) ? 5 // - depth<=32 LOG2=5
+ : (((depth-1)>>6)==0) ? 6 // - depth<=64 LOG2=6
+ : (((depth-1)>>7)==0) ? 7 // - depth<=128 LOG2=7
+ : 8) // - depth<=256 LOG2=8
+ ;
+
+ input clock;
+ input reset;
+
+ input [width-1:0] i_d; // - input stream data (concat data + eos)
+ input i_v; // - input stream valid
+ output i_r; // - input stream ready
+ wire i_b; // - input stream back-pressure
+
+ output [width-1:0] o_d; // - output stream data (concat data + eos)
+ output o_v; // - output stream valid
+ input o_r; // - output stream ready
+ wire o_b; // - output stream back-pressure
+
+ output [addrwidth:0] count; // - output number of elems in queue
+
+ reg [addrwidth-1:0] addr, addr_, a_; // - SRL16 address
+ // for data output
+ reg shift_en_; // - SRL16 shift enable
+ reg [width-1:0] srl [depth-2:0]; // - SRL16 memory
+ reg shift_en_o_; // - SRLO shift enable
+ reg [width-1:0] srlo_, srlo // - SRLO output reg
+ /* synthesis syn_allow_retiming=0 */ ;
+
+ parameter state_empty = 2'd0; // - state empty : o_v=0 o_d=UNDEFINED
+ parameter state_one = 2'd1; // - state one : o_v=1 o_d=srlo
+ parameter state_more = 2'd2; // - state more : o_v=1 o_d=srlo
+ // #items in srl = addr+2
+
+ reg [1:0] state, state_; // - state register
+
+ wire addr_full_; // - true iff addr==depth-2 on NEXT cycle
+ reg addr_full; // - true iff addr==depth-2
+ wire addr_zero_; // - true iff addr==0
+ wire o_v_reg_; // - true iff state_empty on NEXT cycle
+ reg o_v_reg // - true iff state_empty
+ /* synthesis syn_allow_retiming=0 */ ;
+ wire i_b_reg_; // - true iff !full on NEXT cycle
+ reg i_b_reg // - true iff !full
+ /* synthesis syn_allow_retiming=0 */ ;
+
+ assign addr_full_ = (state_==state_more) && (addr_==depth-2);
+ // - queue full
+ assign addr_zero_ = (addr==0); // - queue contains 2 (or 1,0)
+ assign o_v_reg_ = (state_!=state_empty); // - output valid if non-empty
+ assign i_b_reg_ = addr_full_; // - input bp if full
+ assign o_d = srlo; // - output data from queue
+ assign o_v = o_v_reg; // - output valid if non-empty
+ assign i_b = i_b_reg; // - input bp if full
+
+ assign i_r = !i_b;
+ assign o_b = !o_r;
+
+ assign count = (state==state_more ? addr+2 : (state==state_one ? 1 : 0));
+
+ // - ''always'' block with both FFs and SRL16 does not work,
+ // since FFs need reset but SRL16 does not
+
+ always @(posedge clock) begin // - seq always: FFs
+ if (reset) begin
+ state <= state_empty;
+ addr <= 0;
+ addr_full <= 0;
+ o_v_reg <= 0;
+ i_b_reg <= 1;
+ end
+ else begin
+ state <= state_;
+ addr <= addr_;
+ addr_full <= addr_full_;
+ o_v_reg <= o_v_reg_;
+ i_b_reg <= i_b_reg_;
+ end
+ end // always @ (posedge clock)
+
+ always @(posedge clock) begin // - seq always: srlo
+ // - infer enabled output reg at end of shift chain
+ // - input first element from i_d, all subsequent elements from SRL16
+ if (reset) begin
+ srlo <= 0;
+ end
+ else begin
+ if (shift_en_o_) begin
+ srlo <= srlo_;
+ end
+ end
+ end // always @ (posedge clock)
+
+ always @(posedge clock) begin // - seq always: srl
+ // - infer enabled SRL16E from shifting srl array
+ // - no reset capability; srl[] contents undefined on reset
+ if (shift_en_) begin
+ // synthesis loop_limit 256
+ for (a_=depth-2; a_>0; a_=a_-1) begin
+ srl[a_] = srl[a_-1];
+ end
+ srl[0] <= i_d;
+ end
+ end // always @ (posedge clock or negedge reset)
+
+ always @* begin // - combi always
+ srlo_ <= 'bx;
+ shift_en_o_ <= 1'bx;
+ shift_en_ <= 1'bx;
+ addr_ <= 'bx;
+ state_ <= 2'bx;
+ case (state)
+
+ state_empty: begin // - (empty, will not produce)
+ if (i_v) begin // - empty & i_v => consume
+ srlo_ <= i_d;
+ shift_en_o_ <= 1;
+ shift_en_ <= 1'bx;
+ addr_ <= 0;
+ state_ <= state_one;
+ end
+ else begin // - empty & !i_v => idle
+ srlo_ <= 'bx;
+ shift_en_o_ <= 0;
+ shift_en_ <= 1'bx;
+ addr_ <= 0;
+ state_ <= state_empty;
+ end
+ end
+
+ state_one: begin // - (contains one)
+ if (i_v && o_b) begin // - one & i_v & o_b => consume
+ srlo_ <= 'bx;
+ shift_en_o_ <= 0;
+ shift_en_ <= 1;
+ addr_ <= 0;
+ state_ <= state_more;
+ end
+ else if (i_v && !o_b) begin // - one & i_v & !o_b => cons+prod
+ srlo_ <= i_d;
+ shift_en_o_ <= 1;
+ shift_en_ <= 1;
+ addr_ <= 0;
+ state_ <= state_one;
+ end
+ else if (!i_v && o_b) begin // - one & !i_v & o_b => idle
+ srlo_ <= 'bx;
+ shift_en_o_ <= 0;
+ shift_en_ <= 1'bx;
+ addr_ <= 0;
+ state_ <= state_one;
+ end
+ else if (!i_v && !o_b) begin // - one & !i_v & !o_b => produce
+ srlo_ <= 'bx;
+ shift_en_o_ <= 0;
+ shift_en_ <= 1'bx;
+ addr_ <= 0;
+ state_ <= state_empty;
+ end
+ end // case: state_one
+
+ state_more: begin // - (contains more than one)
+ if (addr_full || (depth==2)) begin
+ // - (full, will not consume)
+ // - (full here if depth==2)
+ if (o_b) begin // - full & o_b => idle
+ srlo_ <= 'bx;
+ shift_en_o_ <= 0;
+ shift_en_ <= 0;
+ addr_ <= addr;
+ state_ <= state_more;
+ end
+ else begin // - full & !o_b => produce
+ srlo_ <= srl[addr];
+ shift_en_o_ <= 1;
+ shift_en_ <= 0;
+// addr_ <= addr-1;
+// state_ <= state_more;
+ addr_ <= addr_zero_ ? 0 : addr-1;
+ state_ <= addr_zero_ ? state_one : state_more;
+ end
+ end
+ else begin // - (mid: neither empty nor full)
+ if (i_v && o_b) begin // - mid & i_v & o_b => consume
+ srlo_ <= 'bx;
+ shift_en_o_ <= 0;
+ shift_en_ <= 1;
+ addr_ <= addr+1;
+ state_ <= state_more;
+ end
+ else if (i_v && !o_b) begin // - mid & i_v & !o_b => cons+prod
+ srlo_ <= srl[addr];
+ shift_en_o_ <= 1;
+ shift_en_ <= 1;
+ addr_ <= addr;
+ state_ <= state_more;
+ end
+ else if (!i_v && o_b) begin // - mid & !i_v & o_b => idle
+ srlo_ <= 'bx;
+ shift_en_o_ <= 0;
+ shift_en_ <= 0;
+ addr_ <= addr;
+ state_ <= state_more;
+ end
+ else if (!i_v && !o_b) begin // - mid & !i_v & !o_b => produce
+ srlo_ <= srl[addr];
+ shift_en_o_ <= 1;
+ shift_en_ <= 0;
+ addr_ <= addr_zero_ ? 0 : addr-1;
+ state_ <= addr_zero_ ? state_one : state_more;
+ end
+ end // else: !if(addr_full)
+ end // case: state_more
+
+ default: begin
+ srlo_ <= 'bx;
+ shift_en_o_ <= 1'bx;
+ shift_en_ <= 1'bx;
+ addr_ <= 'bx;
+ state_ <= 2'bx;
+ end // case: default
+
+ endcase // case(state)
+ end // always @ *
+
+endmodule // Q_srl
+
+
+`endif // `ifdef Q_srl
diff --git a/finn-rtllib/memstream/hdl/memstream.v b/finn-rtllib/memstream/hdl/memstream.v
new file mode 100644
index 0000000000000000000000000000000000000000..28acb301a583f7437c580744bae7bdc4aef76337
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/memstream.v
@@ -0,0 +1,467 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module memstream
+#(
+//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
+ parameter CONFIG_EN = 1,
+ parameter NSTREAMS = 6,//1 up to 6
+
+ parameter MEM_DEPTH = 13824,
+ parameter MEM_WIDTH = 32,
+ parameter MEM_INIT = "./",
+ parameter RAM_STYLE = "auto",
+
+ //widths per stream
+ parameter STRM0_WIDTH = 32,
+ parameter STRM1_WIDTH = 32,
+ parameter STRM2_WIDTH = 32,
+ parameter STRM3_WIDTH = 32,
+ parameter STRM4_WIDTH = 32,
+ parameter STRM5_WIDTH = 32,
+
+ //depths per stream
+ parameter STRM0_DEPTH = 2304,
+ parameter STRM1_DEPTH = 2304,
+ parameter STRM2_DEPTH = 2304,
+ parameter STRM3_DEPTH = 2304,
+ parameter STRM4_DEPTH = 2304,
+ parameter STRM5_DEPTH = 2304,
+
+ //offsets for each stream
+ parameter STRM0_OFFSET = 0,
+ parameter STRM1_OFFSET = 2304,
+ parameter STRM2_OFFSET = 4608,
+ parameter STRM3_OFFSET = 6912,
+ parameter STRM4_OFFSET = 9216,
+ parameter STRM5_OFFSET = 11520
+)
+
+(
+ input aclk,
+ input aresetn,
+
+ //optional configuration interface compatible with ap_memory
+ input [31:0] config_address,
+ input config_ce,
+ input config_we,
+ input [31:0] config_d0,
+ output [31:0] config_q0,
+
+ //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
+ input m_axis_0_afull,
+ input m_axis_0_tready,
+ output m_axis_0_tvalid,
+ output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,
+
+ input m_axis_1_afull,
+ input m_axis_1_tready,
+ output m_axis_1_tvalid,
+ output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata,
+
+ input m_axis_2_afull,
+ input m_axis_2_tready,
+ output m_axis_2_tvalid,
+ output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata,
+
+ input m_axis_3_afull,
+ input m_axis_3_tready,
+ output m_axis_3_tvalid,
+ output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata,
+
+ input m_axis_4_afull,
+ input m_axis_4_tready,
+ output m_axis_4_tvalid,
+ output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata,
+
+ input m_axis_5_afull,
+ input m_axis_5_tready,
+ output m_axis_5_tvalid,
+ output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata
+
+
+);
+
+//calculate number of RAMB18 blocks we need depth-wise
+localparam NMEMBLOCKS = (MEM_DEPTH+1023) / 1024; //ceil(MEM_DEPTH/1024)
+
+//calculate width of address for each block
+localparam BLOCKADRWIDTH = NMEMBLOCKS > 1 ? 10 : $clog2(MEM_DEPTH);
+
+//determine whether a stream needs to multiplex between memory blocks
+localparam STRM0_MUX = ((STRM0_OFFSET/1024) != ((STRM0_OFFSET+STRM0_DEPTH)/1024));
+localparam STRM1_MUX = ((STRM1_OFFSET/1024) != ((STRM1_OFFSET+STRM1_DEPTH)/1024));
+localparam STRM2_MUX = ((STRM2_OFFSET/1024) != ((STRM2_OFFSET+STRM2_DEPTH)/1024));
+localparam STRM3_MUX = ((STRM3_OFFSET/1024) != ((STRM3_OFFSET+STRM3_DEPTH)/1024));
+localparam STRM4_MUX = ((STRM4_OFFSET/1024) != ((STRM4_OFFSET+STRM4_DEPTH)/1024));
+localparam STRM5_MUX = ((STRM5_OFFSET/1024) != ((STRM5_OFFSET+STRM5_DEPTH)/1024));
+
+//determine what the base block of each stream is
+localparam STRM0_BLOCK = (STRM0_OFFSET/1024);
+localparam STRM1_BLOCK = (STRM1_OFFSET/1024);
+localparam STRM2_BLOCK = (STRM2_OFFSET/1024);
+localparam STRM3_BLOCK = (STRM3_OFFSET/1024);
+localparam STRM4_BLOCK = (STRM4_OFFSET/1024);
+localparam STRM5_BLOCK = (STRM5_OFFSET/1024);
+
+//determine what the end block of each stream is
+localparam STRM0_END_BLOCK = ((STRM0_OFFSET+STRM0_DEPTH-1)/1024);
+localparam STRM1_END_BLOCK = ((STRM1_OFFSET+STRM1_DEPTH-1)/1024);
+localparam STRM2_END_BLOCK = ((STRM2_OFFSET+STRM2_DEPTH-1)/1024);
+localparam STRM3_END_BLOCK = ((STRM3_OFFSET+STRM3_DEPTH-1)/1024);
+localparam STRM4_END_BLOCK = ((STRM4_OFFSET+STRM4_DEPTH-1)/1024);
+localparam STRM5_END_BLOCK = ((STRM5_OFFSET+STRM5_DEPTH-1)/1024);
+
+//determine the number of blocks spanned by each stream
+localparam STRM0_NBLOCKS = STRM0_END_BLOCK - STRM0_BLOCK + 1;
+localparam STRM1_NBLOCKS = STRM1_END_BLOCK - STRM1_BLOCK + 1;
+localparam STRM2_NBLOCKS = STRM2_END_BLOCK - STRM2_BLOCK + 1;
+localparam STRM3_NBLOCKS = STRM3_END_BLOCK - STRM3_BLOCK + 1;
+localparam STRM4_NBLOCKS = STRM4_END_BLOCK - STRM4_BLOCK + 1;
+localparam STRM5_NBLOCKS = STRM5_END_BLOCK - STRM5_BLOCK + 1;
+
+//TODO: check that memory width is equal to the widest stream
+//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?)
+initial begin
+ if((NSTREAMS < 1) | (NSTREAMS > 6)) begin
+ $display("Invalid setting for NSTREAMS, please set in range [1,6]");
+ $finish();
+ end
+end
+
+//invert reset
+wire rst;
+assign rst = ~aresetn;
+
+//WARNING: pipeline depth is larger than the number of streams per port so we have in-flight writes that may see not-ready when they get executed
+//solution: use prog-full to make sure we have an equal number of free slots in the stream to the read pipeline depth
+
+reg [$clog2(MEM_DEPTH)-1:0] strm0_addr = STRM0_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm1_addr = STRM1_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm2_addr = STRM2_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm3_addr = STRM3_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm4_addr = STRM4_OFFSET;
+reg [$clog2(MEM_DEPTH)-1:0] strm5_addr = STRM5_OFFSET;
+
+reg strm0_incr_en;
+reg strm1_incr_en;
+reg strm2_incr_en;
+reg strm3_incr_en;
+reg strm4_incr_en;
+reg strm5_incr_en;
+
+wire strm0_rst;
+wire strm1_rst;
+wire strm2_rst;
+wire strm3_rst;
+wire strm4_rst;
+wire strm5_rst;
+
+reg strm0_ready;
+reg strm1_ready;
+reg strm2_ready;
+reg strm3_ready;
+reg strm4_ready;
+reg strm5_ready;
+
+//arbiter: work on one stream at a time
+//multiplex each port between (up to) half of the streams
+reg [1:0] current_stream_porta = 0;
+reg [1:0] current_stream_portb = 0;
+
+always @(posedge aclk) begin
+ if(rst)
+ current_stream_porta <= 0;
+ else case(current_stream_porta)
+ 0: current_stream_porta <= strm2_ready ? 1 : strm4_ready ? 2 : 0;
+ 1: current_stream_porta <= strm4_ready ? 2 : strm0_ready ? 0 : 1;
+ 2: current_stream_porta <= strm0_ready ? 0 : strm2_ready ? 1 : 2;
+ endcase
+ if(rst)
+ current_stream_portb <= 0;
+ else case(current_stream_portb)
+ 0: current_stream_portb <= strm3_ready ? 1 : strm5_ready ? 2 : 0;
+ 1: current_stream_portb <= strm5_ready ? 2 : strm1_ready ? 0 : 1;
+ 2: current_stream_portb <= strm1_ready ? 0 : strm3_ready ? 1 : 2;
+ endcase
+end
+
+always @(posedge aclk) begin
+ if(rst) begin
+ strm0_incr_en <= 0;
+ strm1_incr_en <= 0;
+ strm2_incr_en <= 0;
+ strm3_incr_en <= 0;
+ strm4_incr_en <= 0;
+ strm5_incr_en <= 0;
+ end else begin
+ strm0_incr_en <= (current_stream_porta == 0) & strm0_ready;
+ strm1_incr_en <= (current_stream_portb == 0) & strm1_ready;
+ strm2_incr_en <= (current_stream_porta == 1) & strm2_ready;
+ strm3_incr_en <= (current_stream_portb == 1) & strm3_ready;
+ strm4_incr_en <= (current_stream_porta == 2) & strm4_ready;
+ strm5_incr_en <= (current_stream_portb == 2) & strm5_ready;
+ end
+end
+
+assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));
+assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
+assign strm2_rst = strm2_incr_en & (strm2_addr == (STRM2_OFFSET + STRM2_DEPTH-1));
+assign strm3_rst = strm3_incr_en & (strm3_addr == (STRM3_OFFSET + STRM3_DEPTH-1));
+assign strm4_rst = strm4_incr_en & (strm4_addr == (STRM4_OFFSET + STRM4_DEPTH-1));
+assign strm5_rst = strm5_incr_en & (strm5_addr == (STRM5_OFFSET + STRM5_DEPTH-1));
+
+always @(posedge aclk) begin
+ strm0_ready <= ~m_axis_0_afull;
+ strm1_ready <= ~m_axis_1_afull & (NSTREAMS >= 2);
+ strm2_ready <= ~m_axis_2_afull & (NSTREAMS >= 3);
+ strm3_ready <= ~m_axis_3_afull & (NSTREAMS >= 4);
+ strm4_ready <= ~m_axis_4_afull & (NSTREAMS >= 5);
+ strm5_ready <= ~m_axis_5_afull & (NSTREAMS >= 6);
+end
+
+//one address counter per stream; more LUTs but keeps routing short and local
+always @(posedge aclk) begin
+ if(strm0_rst | rst)
+ strm0_addr <= STRM0_OFFSET;
+ else if(strm0_incr_en)
+ strm0_addr <= strm0_addr + 1;
+ if(strm1_rst | rst)
+ strm1_addr <= STRM1_OFFSET;
+ else if(strm1_incr_en)
+ strm1_addr <= strm1_addr + 1;
+ if(strm2_rst | rst)
+ strm2_addr <= STRM2_OFFSET;
+ else if(strm2_incr_en)
+ strm2_addr <= strm2_addr + 1;
+ if(strm3_rst | rst)
+ strm3_addr <= STRM3_OFFSET;
+ else if(strm3_incr_en)
+ strm3_addr <= strm3_addr + 1;
+ if(strm4_rst | rst)
+ strm4_addr <= STRM4_OFFSET;
+ else if(strm4_incr_en)
+ strm4_addr <= strm4_addr + 1;
+ if(strm5_rst | rst)
+ strm5_addr <= STRM5_OFFSET;
+ else if(strm5_incr_en)
+ strm5_addr <= strm5_addr + 1;
+end
+
+reg [$clog2(MEM_DEPTH)-1:0] addra;
+wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqa;
+
+reg [$clog2(MEM_DEPTH)-1:0] addrb;
+wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqb;
+
+wire [NMEMBLOCKS-1:0] we;
+
+reg [1:0] addr_select_porta;
+reg [1:0] addr_select_portb;
+
+//multiplex addresses of various streams into address ports of memory
+always @(posedge aclk) begin
+ addr_select_porta <= current_stream_porta;
+ case(addr_select_porta)
+ 0: addra <= strm0_addr;
+ 1: addra <= strm2_addr;
+ 2: addra <= strm4_addr;
+ endcase
+ addr_select_portb <= current_stream_portb;
+ case(addr_select_portb)
+ 0: addrb <= strm1_addr;
+ 1: addrb <= strm3_addr;
+ 2: addrb <= strm5_addr;
+ endcase
+end
+
+genvar g;
+generate for(g=0; g<NMEMBLOCKS; g=g+1) begin: blockports
+
+assign we[g] = (CONFIG_EN == 1) & config_ce & config_we & (config_address[31:BLOCKADRWIDTH] == g);
+
+ramb18_wf_dualport
+#(
+ .ID(g),
+ .DWIDTH(MEM_WIDTH),
+ .AWIDTH(BLOCKADRWIDTH),
+ .MEM_INIT(MEM_INIT),
+ .RAM_STYLE(RAM_STYLE)
+)
+ram
+(
+ .clk(aclk),
+
+ .wea(we[g]),
+ .addra(we[g] ? config_address[BLOCKADRWIDTH-1:0] : addra[BLOCKADRWIDTH-1:0]),
+ .wdataa(config_d0),
+ .rdqa(rdqa[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH]),
+
+ .web(1'b0),
+ .addrb(addrb[BLOCKADRWIDTH-1:0]),
+ .wdatab('d0),
+ .rdqb(rdqb[(g+1)*MEM_WIDTH-1:g*MEM_WIDTH])
+);
+
+end
+endgenerate
+
+integer i;
+
+generate if(NMEMBLOCKS > 1) begin: multiblock
+
+wire [MEM_WIDTH-1:0] rdqmux[5:0];
+
+reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblocka[2:0];
+reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblockb[2:0];
+
+always @(posedge aclk) begin
+ rdblocka[0] <= addra[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
+ rdblockb[0] <= addrb[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH];
+ for(i=0; i<2; i=i+1) begin
+ rdblocka[i+1] <= rdblocka[i];
+ rdblockb[i+1] <= rdblockb[i];
+ end
+end
+
+if(NSTREAMS >= 1) begin: en_strm0
+ if(STRM0_MUX == 1) begin: mux0
+ mux #(STRM0_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM0_BLOCK+STRM0_NBLOCKS)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH],rdqmux[0],rdblocka[1] - STRM0_BLOCK);
+ end else begin: nomux0
+ assign rdqmux[0] = rdqa[(STRM0_BLOCK+1)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_0_tdata = rdqmux[0][STRM0_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 2) begin: en_strm1
+ if(STRM1_MUX == 1) begin: mux1
+ mux #(STRM1_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM1_BLOCK+STRM1_NBLOCKS)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH],rdqmux[1],rdblockb[1] - STRM1_BLOCK);
+ end else begin: nomux1
+ assign rdqmux[1] = rdqb[(STRM1_BLOCK+1)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_1_tdata = rdqmux[1][STRM1_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 3) begin: en_strm2
+ if(STRM2_MUX == 1) begin: mux2
+ mux #(STRM2_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM2_BLOCK+STRM2_NBLOCKS)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH],rdqmux[2],rdblocka[1] - STRM2_BLOCK);
+ end else begin: nomux2
+ assign rdqmux[2] = rdqa[(STRM2_BLOCK+1)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_2_tdata = rdqmux[2][STRM2_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 4) begin: en_strm3
+ if(STRM3_MUX == 1) begin: mux3
+ mux #(STRM3_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM3_BLOCK+STRM3_NBLOCKS)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH],rdqmux[3],rdblockb[1] - STRM3_BLOCK);
+ end else begin: nomux3
+ assign rdqmux[3] = rdqb[(STRM3_BLOCK+1)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_3_tdata = rdqmux[3][STRM3_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 5) begin: en_strm4
+ if(STRM4_MUX == 1) begin: mux4
+ mux #(STRM4_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM4_BLOCK+STRM4_NBLOCKS)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH],rdqmux[4],rdblocka[1] - STRM4_BLOCK);
+ end else begin: nomux4
+ assign rdqmux[4] = rdqa[(STRM4_BLOCK+1)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_4_tdata = rdqmux[4][STRM4_WIDTH-1:0];
+end
+
+if(NSTREAMS >= 6) begin: en_strm5
+ if(STRM5_MUX == 1) begin: mux5
+ mux #(STRM5_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM5_BLOCK+STRM5_NBLOCKS)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH],rdqmux[5],rdblockb[1] - STRM5_BLOCK);
+ end else begin: nomux5
+ assign rdqmux[5] = rdqb[(STRM5_BLOCK+1)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH];
+ end
+ assign m_axis_5_tdata = rdqmux[5][STRM5_WIDTH-1:0];
+end
+
+end else begin: singleblock
+
+if(NSTREAMS >= 1) begin: en_strm0_direct
+ assign m_axis_0_tdata = rdqa[STRM0_WIDTH-1:0];
+end
+if(NSTREAMS >= 2) begin: en_strm1_direct
+ assign m_axis_1_tdata = rdqb[STRM1_WIDTH-1:0];
+end
+if(NSTREAMS >= 3) begin: en_strm2_direct
+ assign m_axis_2_tdata = rdqa[STRM2_WIDTH-1:0];
+end
+if(NSTREAMS >= 4) begin: en_strm3_direct
+ assign m_axis_3_tdata = rdqb[STRM3_WIDTH-1:0];
+end
+if(NSTREAMS >= 5) begin: en_strm4_direct
+ assign m_axis_4_tdata = rdqa[STRM4_WIDTH-1:0];
+end
+if(NSTREAMS >= 6) begin: en_strm5_direct
+ assign m_axis_5_tdata = rdqb[STRM5_WIDTH-1:0];
+end
+
+end
+endgenerate
+
+//output to AXI Streams
+reg tvalid_pipe0[2:0];
+reg tvalid_pipe1[2:0];
+reg tvalid_pipe2[2:0];
+reg tvalid_pipe3[2:0];
+reg tvalid_pipe4[2:0];
+reg tvalid_pipe5[2:0];
+
+assign m_axis_0_tvalid = tvalid_pipe0[2];
+assign m_axis_1_tvalid = tvalid_pipe1[2];
+assign m_axis_2_tvalid = tvalid_pipe2[2];
+assign m_axis_3_tvalid = tvalid_pipe3[2];
+assign m_axis_4_tvalid = tvalid_pipe4[2];
+assign m_axis_5_tvalid = tvalid_pipe5[2];
+
+
+always @(posedge aclk) begin
+ tvalid_pipe0[0] <= strm0_incr_en;
+ tvalid_pipe1[0] <= strm1_incr_en;
+ tvalid_pipe2[0] <= strm2_incr_en;
+ tvalid_pipe3[0] <= strm3_incr_en;
+ tvalid_pipe4[0] <= strm4_incr_en;
+ tvalid_pipe5[0] <= strm5_incr_en;
+ for(i=0; i<2; i=i+1) begin: srl
+ tvalid_pipe0[i+1] <= tvalid_pipe0[i];
+ tvalid_pipe1[i+1] <= tvalid_pipe1[i];
+ tvalid_pipe2[i+1] <= tvalid_pipe2[i];
+ tvalid_pipe3[i+1] <= tvalid_pipe3[i];
+ tvalid_pipe4[i+1] <= tvalid_pipe4[i];
+ tvalid_pipe5[i+1] <= tvalid_pipe5[i];
+ end
+end
+
+assign config_q0 = 0;
+
+endmodule
diff --git a/finn-rtllib/memstream/hdl/mux.v b/finn-rtllib/memstream/hdl/mux.v
new file mode 100644
index 0000000000000000000000000000000000000000..c5b89aeb4e7eb7b2858d062c18b693d9bd685fb2
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/mux.v
@@ -0,0 +1,44 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module mux
+#(
+ parameter NINPUTS = 1,
+ parameter WIDTH = 16
+)
+(
+ input [NINPUTS*WIDTH-1:0] in,
+ output [WIDTH-1:0] out,
+ input [$clog2(NINPUTS)-1:0] sel
+);
+
+assign out = in >> (sel*WIDTH);
+
+endmodule
\ No newline at end of file
diff --git a/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v b/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v
new file mode 100644
index 0000000000000000000000000000000000000000..4219d0f1c74bddff690b0d0cb21ce6a448c01c97
--- /dev/null
+++ b/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v
@@ -0,0 +1,100 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module ramb18_wf_dualport
+#(
+ parameter ID = 0,
+ parameter DWIDTH = 18,
+ parameter AWIDTH = 10,
+ parameter MEM_INIT = "",
+ parameter RAM_STYLE = "auto"
+)
+(
+ input clk,
+
+ input wea,
+ input [AWIDTH-1:0] addra,
+ input [DWIDTH-1:0] wdataa,
+ output reg [DWIDTH-1:0] rdqa,
+
+ input web,
+ input [AWIDTH-1:0] addrb,
+ input [DWIDTH-1:0] wdatab,
+ output reg [DWIDTH-1:0] rdqb
+);
+
+(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+reg [DWIDTH-1:0] rdataa;
+reg [DWIDTH-1:0] rdatab;
+
+`ifdef SYNTHESIS
+reg [7:0] idx = ID;
+`else
+reg [15:0] idx;
+`endif
+
+//initialize memory
+initial begin
+ //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT
+ //ID can go up to 99
+ if (ID < 0 && ID > 99) begin
+ $display("ID out of range [0-99]");
+ $finish();
+ end
+ //MEM_INIT path must be terminated by /
+ `ifdef SYNTHESIS
+ if (ID < 10)
+ $readmemh({MEM_INIT,"memblock_",idx+8'd48,".dat"}, mem, 0, 1023);
+ else
+ $readmemh({MEM_INIT,"memblock_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, 1023);
+ `else
+ $sformat(idx,"%0d",ID);
+ if (ID < 10)
+ $readmemh({MEM_INIT,"memblock_",idx[7:0],".dat"}, mem, 0, 1023);
+ else
+ $readmemh({MEM_INIT,"memblock_",idx,".dat"}, mem, 0, 1023);
+ `endif
+end
+
+//memory ports, with output pipeline register
+always @(posedge clk) begin
+ if(wea)
+ mem[addra] <= wdataa;
+ rdataa <= mem[addra];
+ rdqa <= rdataa;
+end
+always @(posedge clk) begin
+ if(web)
+ mem[addrb] <= wdatab;
+ rdatab <= mem[addrb];
+ rdqb <= rdatab;
+end
+
+endmodule
diff --git a/finn-rtllib/memstream/sim/gen_memblocks.sh b/finn-rtllib/memstream/sim/gen_memblocks.sh
new file mode 100644
index 0000000000000000000000000000000000000000..05962f7be8fe4afd7790640cf4d280600dcf43d1
--- /dev/null
+++ b/finn-rtllib/memstream/sim/gen_memblocks.sh
@@ -0,0 +1,39 @@
+#!/bin/bash
+
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+NLINES=`cat $1 | wc -l`
+NBLOCKS=$(( ($NLINES + 1023) / 1024 ))
+rm memblock_*.dat
+
+for (( i=0; i<$NBLOCKS; i++ ))
+do
+ START=$(( 1 + $i * 1024 ))
+ tail -n +$START $1 | head -n 1024 >> memblock_$i.dat
+done
\ No newline at end of file
diff --git a/finn-rtllib/memstream/sim/golden.dat b/finn-rtllib/memstream/sim/golden.dat
new file mode 100644
index 0000000000000000000000000000000000000000..1466271bcab961f742e242aea4241a4ffad02828
--- /dev/null
+++ b/finn-rtllib/memstream/sim/golden.dat
@@ -0,0 +1,9216 @@
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diff --git a/finn-rtllib/memstream/sim/tb_memstream.v b/finn-rtllib/memstream/sim/tb_memstream.v
new file mode 100644
index 0000000000000000000000000000000000000000..d63fa30046d7c5f2c50f509174b4937374e70c13
--- /dev/null
+++ b/finn-rtllib/memstream/sim/tb_memstream.v
@@ -0,0 +1,369 @@
+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+`timescale 1ns/10ps
+
+module tb_memstream;
+
+//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths
+parameter CONFIG_EN = 1;
+parameter NSTREAMS = 4;//1 up to 6
+
+parameter MEM_DEPTH = 9216;
+parameter MEM_WIDTH = 32;
+parameter MEM_INIT = "./";
+parameter MEM_CHECK = "golden.dat";
+
+//widths per stream
+parameter STRM0_WIDTH = 32;
+parameter STRM1_WIDTH = 32;
+parameter STRM2_WIDTH = 32;
+parameter STRM3_WIDTH = 32;
+parameter STRM4_WIDTH = 1;
+parameter STRM5_WIDTH = 1;
+
+//depths per stream
+parameter STRM0_DEPTH = 2304;
+parameter STRM1_DEPTH = 2304;
+parameter STRM2_DEPTH = 2304;
+parameter STRM3_DEPTH = 2304;
+parameter STRM4_DEPTH = 1;
+parameter STRM5_DEPTH = 1;
+
+//offsets for each stream
+parameter STRM0_OFFSET = 0;
+parameter STRM1_OFFSET = 2304;
+parameter STRM2_OFFSET = 4608;
+parameter STRM3_OFFSET = 6912;
+parameter STRM4_OFFSET = 0;
+parameter STRM5_OFFSET = 0;
+
+
+reg clk;
+reg rst;
+
+reg [31:0] config_address = 0;
+reg config_ce = 0;
+reg config_we = 0;
+reg [31:0] config_d0 = 0;
+wire [31:0] config_q0;
+
+//multiple wire AXI Streams
+reg m_axis_0_afull;
+reg m_axis_0_tready;
+wire m_axis_0_tvalid;
+wire [STRM0_WIDTH-1:0] m_axis_0_tdata;
+
+reg m_axis_1_afull;
+reg m_axis_1_tready;
+wire m_axis_1_tvalid;
+wire [STRM1_WIDTH-1:0] m_axis_1_tdata;
+
+reg m_axis_2_afull;
+reg m_axis_2_tready;
+wire m_axis_2_tvalid;
+wire [STRM2_WIDTH-1:0] m_axis_2_tdata;
+
+reg m_axis_3_afull;
+reg m_axis_3_tready;
+wire m_axis_3_tvalid;
+wire [STRM3_WIDTH-1:0] m_axis_3_tdata;
+
+reg m_axis_4_afull;
+reg m_axis_4_tready;
+wire m_axis_4_tvalid;
+wire [STRM4_WIDTH-1:0] m_axis_4_tdata;
+
+reg m_axis_5_afull;
+reg m_axis_5_tready;
+wire m_axis_5_tvalid;
+wire [STRM5_WIDTH-1:0] m_axis_5_tdata;
+
+reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0];
+integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5;
+integer done = 0;
+reg [5:0] rng;
+
+//clock
+initial begin
+ clk = 0;
+ forever #5 clk = ~clk;
+end
+
+initial begin
+ rst = 1;
+ config_ce = 0;
+ m_axis_0_afull = 0;
+ m_axis_1_afull = 0;
+ m_axis_2_afull = 0;
+ m_axis_3_afull = 0;
+ m_axis_4_afull = 0;
+ m_axis_5_afull = 0;
+ m_axis_0_tready = 1;
+ m_axis_1_tready = 1;
+ m_axis_2_tready = 1;
+ m_axis_3_tready = 1;
+ m_axis_4_tready = 1;
+ m_axis_5_tready = 1;
+ repeat(100) @(negedge clk);
+ rst = 0;
+ #100
+ fork
+ begin
+ $display("Starting to generate random AFULL");
+ while(~done) begin
+ rng = $random;
+ m_axis_0_afull = rng[0];
+ m_axis_1_afull = rng[1];
+ m_axis_2_afull = rng[2];
+ m_axis_3_afull = rng[3];
+ m_axis_4_afull = rng[4];
+ m_axis_5_afull = rng[5];
+ @(negedge clk);
+ end
+ end
+ join
+end
+
+
+//DUT
+memstream
+#(
+ CONFIG_EN,
+ NSTREAMS,
+ MEM_DEPTH,
+ MEM_WIDTH,
+ MEM_INIT,
+
+ //widths per stream
+ STRM0_WIDTH,
+ STRM1_WIDTH,
+ STRM2_WIDTH,
+ STRM3_WIDTH,
+ STRM4_WIDTH,
+ STRM5_WIDTH,
+
+ //depths per stream
+ STRM0_DEPTH,
+ STRM1_DEPTH,
+ STRM2_DEPTH,
+ STRM3_DEPTH,
+ STRM4_DEPTH,
+ STRM5_DEPTH,
+
+ //offsets for each stream
+ STRM0_OFFSET,
+ STRM1_OFFSET,
+ STRM2_OFFSET,
+ STRM3_OFFSET,
+ STRM4_OFFSET,
+ STRM5_OFFSET
+)
+dut
+(
+ clk,
+ ~rst,
+
+ //optional AXI-Lite interface
+ config_address,
+ config_ce,
+ config_we,
+ config_d0,
+ config_q0,
+
+ //multiple output AXI Streams
+ m_axis_0_afull,
+ m_axis_0_tready,
+ m_axis_0_tvalid,
+ m_axis_0_tdata,
+
+ m_axis_1_afull,
+ m_axis_1_tready,
+ m_axis_1_tvalid,
+ m_axis_1_tdata,
+
+ m_axis_2_afull,
+ m_axis_2_tready,
+ m_axis_2_tvalid,
+ m_axis_2_tdata,
+
+ m_axis_3_afull,
+ m_axis_3_tready,
+ m_axis_3_tvalid,
+ m_axis_3_tdata,
+
+ m_axis_4_afull,
+ m_axis_4_tready,
+ m_axis_4_tvalid,
+ m_axis_4_tdata,
+
+ m_axis_5_afull,
+ m_axis_5_tready,
+ m_axis_5_tvalid,
+ m_axis_5_tdata
+
+
+);
+
+//stream checkers
+initial begin
+ ptr0 = STRM0_OFFSET;
+ ptr1 = STRM1_OFFSET;
+ ptr2 = STRM2_OFFSET;
+ ptr3 = STRM3_OFFSET;
+ ptr4 = STRM4_OFFSET;
+ ptr5 = STRM5_OFFSET;
+ fork
+ //check stream 0
+ begin
+ $display("Starting stream 0 checker");
+ while(~done & (NSTREAMS > 0)) begin
+ @(negedge clk);
+ if(m_axis_0_tvalid) begin
+ if(m_axis_0_tdata != golden[ptr0]) begin
+ $display("Mismatch on stream 0");
+ $stop();
+ end
+ //increment pointer
+ ptr0 = ptr0 + 1;
+ //rewind pointer if it's reached end
+ if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH))
+ ptr0 = STRM0_OFFSET;
+ end
+ end
+ end
+ //check stream 1
+ begin
+ $display("Starting stream 1 checker");
+ while(~done & (NSTREAMS > 1)) begin
+ @(negedge clk);
+ if(m_axis_1_tvalid) begin
+ if(m_axis_1_tdata != golden[ptr1]) begin
+ $display("Mismatch on stream 1");
+ $stop();
+ end
+ //increment pointer
+ ptr1 = ptr1 + 1;
+ //rewind pointer if it's reached end
+ if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH))
+ ptr1 = STRM1_OFFSET;
+ end
+ end
+ end
+
+ //check stream 2
+ begin
+ $display("Starting stream 2 checker");
+ while(~done & (NSTREAMS > 2)) begin
+ @(negedge clk);
+ if(m_axis_2_tvalid) begin
+ if(m_axis_2_tdata != golden[ptr2]) begin
+ $display("Mismatch on stream 2");
+ $stop();
+ end
+ //increment pointer
+ ptr2 = ptr2 + 1;
+ //rewind pointer if it's reached end
+ if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH))
+ ptr2 = STRM2_OFFSET;
+ end
+ end
+ end
+ //check stream 3
+ begin
+ $display("Starting stream 3 checker");
+ while(~done & (NSTREAMS > 3)) begin
+ @(negedge clk);
+ if(m_axis_3_tvalid) begin
+ if(m_axis_3_tdata != golden[ptr3]) begin
+ $display("Mismatch on stream 3");
+ $stop();
+ end
+ //increment pointer
+ ptr3 = ptr3 + 1;
+ //rewind pointer if it's reached end
+ if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH))
+ ptr3 = STRM3_OFFSET;
+ end
+ end
+ end
+ //check stream 4
+ begin
+ $display("Starting stream 4 checker");
+ while(~done & (NSTREAMS > 4)) begin
+ @(negedge clk);
+ if(m_axis_4_tvalid) begin
+ if(m_axis_4_tdata != golden[ptr4]) begin
+ $display("Mismatch on stream 4");
+ $stop();
+ end
+ //increment pointer
+ ptr4 = ptr4 + 1;
+ //rewind pointer if it's reached end
+ if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH))
+ ptr4 = STRM4_OFFSET;
+ end
+ end
+ end
+ //check stream 5
+ begin
+ $display("Starting stream 5 checker");
+ while(~done & (NSTREAMS > 5)) begin
+ @(negedge clk);
+ if(m_axis_5_tvalid) begin
+ if(m_axis_5_tdata != golden[ptr5]) begin
+ $display("Mismatch on stream 5");
+ $stop();
+ end
+ //increment pointer
+ ptr5 = ptr5 + 1;
+ //rewind pointer if it's reached end
+ if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH))
+ ptr5 = STRM5_OFFSET;
+ end
+ end
+ end
+ join
+end
+
+initial begin
+ done = 0;
+ $readmemh(MEM_CHECK,golden);
+// $dumpfile("wave.vcd");
+// $dumpvars(0,tb_memstream);
+ @(negedge rst);
+ #10000000
+ $display("Test done!");
+ done = 1;
+ #1000
+ $finish();
+end
+
+endmodule
diff --git a/finn-rtllib/memstream/sim/test.sh b/finn-rtllib/memstream/sim/test.sh
new file mode 100644
index 0000000000000000000000000000000000000000..24767edf4ade1c6867e0c7d906e7a45bbcb987a2
--- /dev/null
+++ b/finn-rtllib/memstream/sim/test.sh
@@ -0,0 +1,34 @@
+#!/bin/bash
+
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+./gen_memblocks.sh golden.dat
+iverilog ../hdl/*.v *v -o sim
+./sim
+
diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e5cbb670da94612e8de73f48cfa4562f89e124d1
--- /dev/null
+++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl
@@ -0,0 +1,383 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "CONFIG_EN" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "MEM_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "MEM_INIT" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "MEM_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "NSTREAMS" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM0_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM0_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM0_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM1_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM1_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM1_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM2_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM2_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM2_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM3_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM3_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM3_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM4_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM4_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM4_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM5_DEPTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM5_OFFSET" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "STRM5_WIDTH" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
+ # Procedure called to update CONFIG_EN when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } {
+ # Procedure called to validate CONFIG_EN
+ return true
+}
+
+proc update_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
+ # Procedure called to update MEM_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } {
+ # Procedure called to validate MEM_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
+ # Procedure called to update MEM_INIT when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } {
+ # Procedure called to validate MEM_INIT
+ return true
+}
+
+proc update_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
+ # Procedure called to update MEM_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } {
+ # Procedure called to validate MEM_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
+ # Procedure called to update NSTREAMS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } {
+ # Procedure called to validate NSTREAMS
+ return true
+}
+
+proc update_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
+ # Procedure called to update STRM0_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } {
+ # Procedure called to validate STRM0_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
+ # Procedure called to update STRM0_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } {
+ # Procedure called to validate STRM0_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
+ # Procedure called to update STRM0_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } {
+ # Procedure called to validate STRM0_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
+ # Procedure called to update STRM1_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } {
+ # Procedure called to validate STRM1_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
+ # Procedure called to update STRM1_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } {
+ # Procedure called to validate STRM1_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
+ # Procedure called to update STRM1_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } {
+ # Procedure called to validate STRM1_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
+ # Procedure called to update STRM2_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } {
+ # Procedure called to validate STRM2_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
+ # Procedure called to update STRM2_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } {
+ # Procedure called to validate STRM2_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
+ # Procedure called to update STRM2_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } {
+ # Procedure called to validate STRM2_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
+ # Procedure called to update STRM3_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } {
+ # Procedure called to validate STRM3_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
+ # Procedure called to update STRM3_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } {
+ # Procedure called to validate STRM3_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
+ # Procedure called to update STRM3_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } {
+ # Procedure called to validate STRM3_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
+ # Procedure called to update STRM4_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } {
+ # Procedure called to validate STRM4_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
+ # Procedure called to update STRM4_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } {
+ # Procedure called to validate STRM4_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
+ # Procedure called to update STRM4_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } {
+ # Procedure called to validate STRM4_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
+ # Procedure called to update STRM5_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } {
+ # Procedure called to validate STRM5_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
+ # Procedure called to update STRM5_OFFSET when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } {
+ # Procedure called to validate STRM5_OFFSET
+ return true
+}
+
+proc update_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
+ # Procedure called to update STRM5_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } {
+ # Procedure called to validate STRM5_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.CONFIG_EN { MODELPARAM_VALUE.CONFIG_EN PARAM_VALUE.CONFIG_EN } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.CONFIG_EN}] ${MODELPARAM_VALUE.CONFIG_EN}
+}
+
+proc update_MODELPARAM_VALUE.NSTREAMS { MODELPARAM_VALUE.NSTREAMS PARAM_VALUE.NSTREAMS } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.NSTREAMS}] ${MODELPARAM_VALUE.NSTREAMS}
+}
+
+proc update_MODELPARAM_VALUE.MEM_DEPTH { MODELPARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.MEM_DEPTH}] ${MODELPARAM_VALUE.MEM_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.MEM_WIDTH { MODELPARAM_VALUE.MEM_WIDTH PARAM_VALUE.MEM_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.MEM_WIDTH}] ${MODELPARAM_VALUE.MEM_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.MEM_INIT { MODELPARAM_VALUE.MEM_INIT PARAM_VALUE.MEM_INIT } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.MEM_INIT}] ${MODELPARAM_VALUE.MEM_INIT}
+}
+
+proc update_MODELPARAM_VALUE.STRM0_WIDTH { MODELPARAM_VALUE.STRM0_WIDTH PARAM_VALUE.STRM0_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM0_WIDTH}] ${MODELPARAM_VALUE.STRM0_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM1_WIDTH { MODELPARAM_VALUE.STRM1_WIDTH PARAM_VALUE.STRM1_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM1_WIDTH}] ${MODELPARAM_VALUE.STRM1_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM2_WIDTH { MODELPARAM_VALUE.STRM2_WIDTH PARAM_VALUE.STRM2_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM2_WIDTH}] ${MODELPARAM_VALUE.STRM2_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM3_WIDTH { MODELPARAM_VALUE.STRM3_WIDTH PARAM_VALUE.STRM3_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM3_WIDTH}] ${MODELPARAM_VALUE.STRM3_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM4_WIDTH { MODELPARAM_VALUE.STRM4_WIDTH PARAM_VALUE.STRM4_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM4_WIDTH}] ${MODELPARAM_VALUE.STRM4_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM5_WIDTH { MODELPARAM_VALUE.STRM5_WIDTH PARAM_VALUE.STRM5_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM5_WIDTH}] ${MODELPARAM_VALUE.STRM5_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM0_DEPTH { MODELPARAM_VALUE.STRM0_DEPTH PARAM_VALUE.STRM0_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM0_DEPTH}] ${MODELPARAM_VALUE.STRM0_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM1_DEPTH { MODELPARAM_VALUE.STRM1_DEPTH PARAM_VALUE.STRM1_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM1_DEPTH}] ${MODELPARAM_VALUE.STRM1_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM2_DEPTH { MODELPARAM_VALUE.STRM2_DEPTH PARAM_VALUE.STRM2_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM2_DEPTH}] ${MODELPARAM_VALUE.STRM2_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM3_DEPTH { MODELPARAM_VALUE.STRM3_DEPTH PARAM_VALUE.STRM3_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM3_DEPTH}] ${MODELPARAM_VALUE.STRM3_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM4_DEPTH { MODELPARAM_VALUE.STRM4_DEPTH PARAM_VALUE.STRM4_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM4_DEPTH}] ${MODELPARAM_VALUE.STRM4_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM5_DEPTH { MODELPARAM_VALUE.STRM5_DEPTH PARAM_VALUE.STRM5_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM5_DEPTH}] ${MODELPARAM_VALUE.STRM5_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.STRM0_OFFSET { MODELPARAM_VALUE.STRM0_OFFSET PARAM_VALUE.STRM0_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM0_OFFSET}] ${MODELPARAM_VALUE.STRM0_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM1_OFFSET { MODELPARAM_VALUE.STRM1_OFFSET PARAM_VALUE.STRM1_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM1_OFFSET}] ${MODELPARAM_VALUE.STRM1_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM2_OFFSET { MODELPARAM_VALUE.STRM2_OFFSET PARAM_VALUE.STRM2_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM2_OFFSET}] ${MODELPARAM_VALUE.STRM2_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM3_OFFSET { MODELPARAM_VALUE.STRM3_OFFSET PARAM_VALUE.STRM3_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM3_OFFSET}] ${MODELPARAM_VALUE.STRM3_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM4_OFFSET { MODELPARAM_VALUE.STRM4_OFFSET PARAM_VALUE.STRM4_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM4_OFFSET}] ${MODELPARAM_VALUE.STRM4_OFFSET}
+}
+
+proc update_MODELPARAM_VALUE.STRM5_OFFSET { MODELPARAM_VALUE.STRM5_OFFSET PARAM_VALUE.STRM5_OFFSET } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.STRM5_OFFSET}] ${MODELPARAM_VALUE.STRM5_OFFSET}
+}
+
diff --git a/notebooks/end2end_example/finn-design-flow-example.svg b/notebooks/end2end_example/finn-design-flow-example.svg
index 7d391fd9fe0b05634f422fab10aff7064b6f6fb8..ca2b82bedb84f4cb9a36ccfef2ad9848b5d5b131 100755
--- a/notebooks/end2end_example/finn-design-flow-example.svg
+++ b/notebooks/end2end_example/finn-design-flow-example.svg
@@ -1 +1 @@
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\ No newline at end of file
diff --git a/notebooks/end2end_example/tfc_end2end_example.ipynb b/notebooks/end2end_example/tfc_end2end_example.ipynb
index 6fad8193c10a8ac8d2857f6c89b93f292ebb0a9c..a0e905c83eab7a52f70bfb45923b9b59d1c8cea6 100644
--- a/notebooks/end2end_example/tfc_end2end_example.ipynb
+++ b/notebooks/end2end_example/tfc_end2end_example.ipynb
@@ -33,8 +33,8 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "The cylinder-like fields show the state of the network representation in the respective step. The rectangular fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into 5 blocks, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (purple block), followed by the preparation of the network (grey block) for the Vivado HLS synthesis and Vivado IPI stitching (yellow block), and finally building a PYNQ overlay bitfile and testing it on a PYNQ board (pink block).\n",
- "There is an additional section for functional verification (green block), which we will not cover in this notebook.\n",
+ "The white fields show the state of the network representation in the respective step. The colored fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into 5 sections represented by a different color, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (green section), followed by the preparation of the network (blue section) for the Vivado HLS synthesis and Vivado IPI stitching (orange section), and finally building a PYNQ overlay bitfile and testing it on a PYNQ board (yellow section).\n",
+ "There is an additional section for functional verification (red section) on the left side of the diagram, which we will not cover in this notebook. For details please take a look in the verification notebook which you can find [here](tfc_end2end_verification.ipynb)\n",
"\n",
"\n",
"This Jupyter notebook is organized based on the sections described above. We will use the following helper functions, `showSrc` to show source code of FINN library calls and `showInNetron` to show the ONNX model at the current transformation step. The Netron displays are interactive, but they only work when running the notebook actively and not on GitHub (i.e. if you are viewing this on GitHub you'll only see blank squares)."
@@ -42,7 +42,7 @@
},
{
"cell_type": "code",
- "execution_count": 5,
+ "execution_count": 1,
"metadata": {},
"outputs": [],
"source": [
@@ -69,18 +69,8 @@
"-------------\n",
"1. [Brevitas export](#brev_exp)\n",
"2. [Network preparation](#nw_prep)\n",
- " * Basic transformations\n",
- " * Streamlining\n",
- " * Conversion to HLS layers\n",
- " * Folding\n",
- "3. [Vivado HLS and Vivado IPI](#vivado)\n",
- " * HLS IP per layer\n",
- " * Creation of stitched design\n",
- "4. [Synthesize, Deploy and Test on PYNQ](#hw_test)\n",
- " * PYNQ shell project\n",
- " * Synthesis, place and route\n",
- " * Driver generation\n",
- " * Deployment and remote execution"
+ "3. [Vivado HLS and IPI](#vivado)\n",
+ "4. [PYNQ hardware generation and deployment](#hw_test)"
]
},
{
@@ -95,9 +85,18 @@
},
{
"cell_type": "code",
- "execution_count": 6,
+ "execution_count": 2,
"metadata": {},
- "outputs": [],
+ "outputs": [
+ {
+ "name": "stderr",
+ "output_type": "stream",
+ "text": [
+ "/workspace/brevitas_cnv_lfc/training_scripts/models/TFC.py:85: TracerWarning: torch.tensor results are registered as constants in the trace. You can safely ignore this warning if you use this function to create tensors out of constant variables that would be the same every time you call this function. In any other case, this might cause the trace to be incorrect.\n",
+ " x = 2.0 * x - torch.tensor([1.0]).to(self.device)\n"
+ ]
+ }
+ ],
"source": [
"import onnx\n",
"from finn.util.test import get_test_model_trained\n",
@@ -117,15 +116,13 @@
},
{
"cell_type": "code",
- "execution_count": 7,
+ "execution_count": 3,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
- "\n",
- "Stopping http://0.0.0.0:8081\n",
"Serving '/workspace/finn/tfc_w1_a1.onnx' at http://0.0.0.0:8081\n"
]
},
@@ -143,10 +140,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f186ccfbe10>"
+ "<IPython.lib.display.IFrame at 0x7f4310b476a0>"
]
},
- "execution_count": 7,
+ "execution_count": 3,
"metadata": {},
"output_type": "execute_result"
}
@@ -164,7 +161,7 @@
},
{
"cell_type": "code",
- "execution_count": 8,
+ "execution_count": 4,
"metadata": {},
"outputs": [],
"source": [
@@ -176,7 +173,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "Now the model is prepared and could be simulated using Python. How this works is described in subsection [Simulation using Python](#simpy) in the section about *Simulation & Emulation flows for functional verification*.\n",
+ "Now the model is prepared and could be simulated using Python. How this works is described in subsection [Simulation using Python](#simpy) in the section about *Simulation & Emulation Flows*.\n",
"\n",
"The model can now also be processed in different ways. The principle of FINN are analysis and transformation passes, which can be applied to the model. An analysis pass extracts specific information about the model and returns it to the user in the form of a dictionary. A transformation pass changes the model and returns the changed model back to the FINN flow.\n",
"\n",
@@ -249,7 +246,7 @@
},
{
"cell_type": "code",
- "execution_count": 9,
+ "execution_count": 5,
"metadata": {},
"outputs": [],
"source": [
@@ -276,7 +273,7 @@
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": 6,
"metadata": {},
"outputs": [
{
@@ -302,10 +299,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f186e386240>"
+ "<IPython.lib.display.IFrame at 0x7f43177c2a20>"
]
},
- "execution_count": 10,
+ "execution_count": 6,
"metadata": {},
"output_type": "execute_result"
}
@@ -326,7 +323,7 @@
},
{
"cell_type": "code",
- "execution_count": 11,
+ "execution_count": 7,
"metadata": {},
"outputs": [
{
@@ -339,11 +336,14 @@
" def apply(self, model):\n",
" streamline_transformations = [\n",
" ConvertSubToAdd(),\n",
+ " ConvertDivToMul(),\n",
" BatchNormToAffine(),\n",
" ConvertSignToThres(),\n",
" MoveAddPastMul(),\n",
" MoveScalarAddPastMatMul(),\n",
+ " MoveScalarAddPastConv(),\n",
" MoveScalarMulPastMatMul(),\n",
+ " MoveScalarMulPastConv(),\n",
" MoveAddPastMul(),\n",
" CollapseRepeatedAdd(),\n",
" CollapseRepeatedMul(),\n",
@@ -351,6 +351,7 @@
" FactorOutMulSignMagnitude(),\n",
" AbsorbMulIntoMultiThreshold(),\n",
" Absorb1BitMulIntoMatMul(),\n",
+ " Absorb1BitMulIntoConv(),\n",
" RoundAndClipThresholds(),\n",
" ]\n",
" for trn in streamline_transformations:\n",
@@ -379,7 +380,7 @@
},
{
"cell_type": "code",
- "execution_count": 12,
+ "execution_count": 8,
"metadata": {},
"outputs": [
{
@@ -405,10 +406,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f186cd470b8>"
+ "<IPython.lib.display.IFrame at 0x7f431826d860>"
]
},
- "execution_count": 12,
+ "execution_count": 8,
"metadata": {},
"output_type": "execute_result"
}
@@ -433,7 +434,7 @@
},
{
"cell_type": "code",
- "execution_count": 13,
+ "execution_count": 9,
"metadata": {},
"outputs": [
{
@@ -459,10 +460,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f17f04bbc18>"
+ "<IPython.lib.display.IFrame at 0x7f42977e39b0>"
]
},
- "execution_count": 13,
+ "execution_count": 9,
"metadata": {},
"output_type": "execute_result"
}
@@ -500,7 +501,7 @@
},
{
"cell_type": "code",
- "execution_count": 14,
+ "execution_count": 10,
"metadata": {
"scrolled": false
},
@@ -528,10 +529,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f1868061eb8>"
+ "<IPython.lib.display.IFrame at 0x7f43177c73c8>"
]
},
- "execution_count": 14,
+ "execution_count": 10,
"metadata": {},
"output_type": "execute_result"
}
@@ -562,7 +563,7 @@
},
{
"cell_type": "code",
- "execution_count": 15,
+ "execution_count": 11,
"metadata": {},
"outputs": [
{
@@ -588,10 +589,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f186cc55e48>"
+ "<IPython.lib.display.IFrame at 0x7f43177c2f60>"
]
},
- "execution_count": 15,
+ "execution_count": 11,
"metadata": {},
"output_type": "execute_result"
}
@@ -614,7 +615,7 @@
},
{
"cell_type": "code",
- "execution_count": 16,
+ "execution_count": 12,
"metadata": {},
"outputs": [
{
@@ -623,7 +624,7 @@
"text": [
"\n",
"Stopping http://0.0.0.0:8081\n",
- "Serving '/tmp/finn_maltanar/dataflow_partition_h1c4i5gn/df_model.onnx' at http://0.0.0.0:8081\n"
+ "Serving '/tmp/finn_jakobap/dataflow_partition_sqcfkplo/df_model.onnx' at http://0.0.0.0:8081\n"
]
},
{
@@ -640,10 +641,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f17f04c70f0>"
+ "<IPython.lib.display.IFrame at 0x7f42977d4978>"
]
},
- "execution_count": 16,
+ "execution_count": 12,
"metadata": {},
"output_type": "execute_result"
}
@@ -664,7 +665,7 @@
},
{
"cell_type": "code",
- "execution_count": 17,
+ "execution_count": 13,
"metadata": {},
"outputs": [],
"source": [
@@ -684,7 +685,7 @@
},
{
"cell_type": "code",
- "execution_count": 18,
+ "execution_count": 14,
"metadata": {},
"outputs": [
{
@@ -718,7 +719,7 @@
},
{
"cell_type": "code",
- "execution_count": 19,
+ "execution_count": 15,
"metadata": {},
"outputs": [
{
@@ -742,19 +743,28 @@
" 'outputDataType': ('s', True, ''),\n",
" 'binaryXnorMode': ('i', False, 0),\n",
" 'noActivation': ('i', False, 0),\n",
- " 'inFIFODepth': ('i', False, 0),\n",
- " 'outFIFODepth': ('i', False, 0),\n",
+ " 'numInputVectors': ('ints', False, [1]),\n",
+ " 'mem_mode': ('s', False, 'const'),\n",
+ " 'ram_style': ('s', False, 'auto'),\n",
" 'backend': ('s', True, 'fpgadataflow'),\n",
" 'code_gen_dir_npysim': ('s', False, ''),\n",
" 'code_gen_dir_ipgen': ('s', False, ''),\n",
" 'executable_path': ('s', False, ''),\n",
" 'ipgen_path': ('s', False, ''),\n",
+ " 'ip_path': ('s', False, ''),\n",
+ " 'ip_vlnv': ('s', False, ''),\n",
" 'exec_mode': ('s', False, ''),\n",
" 'sim_cycles': ('i', False, 0),\n",
- " 'rtlsim_trace': ('s', False, '')}"
+ " 'rtlsim_trace': ('s', False, ''),\n",
+ " 'res_estimate': ('s', False, ''),\n",
+ " 'res_hls': ('s', False, ''),\n",
+ " 'res_synth': ('s', False, ''),\n",
+ " 'rtlsim_so': ('s', False, ''),\n",
+ " 'inFIFODepth': ('i', False, 2),\n",
+ " 'outFIFODepth': ('i', False, 2)}"
]
},
- "execution_count": 19,
+ "execution_count": 15,
"metadata": {},
"output_type": "execute_result"
}
@@ -780,7 +790,7 @@
},
{
"cell_type": "code",
- "execution_count": 20,
+ "execution_count": 16,
"metadata": {},
"outputs": [],
"source": [
@@ -792,29 +802,49 @@
"fc0w.set_nodeattr(\"PE\", 16)\n",
"fc0w.set_nodeattr(\"outFIFODepth\", 4)\n",
"\n",
+ "fc1w.set_nodeattr(\"inFIFODepth\", 4)\n",
"fc1w.set_nodeattr(\"SIMD\", 16)\n",
"fc1w.set_nodeattr(\"PE\", 16)\n",
"fc1w.set_nodeattr(\"outFIFODepth\", 4)\n",
"\n",
+ "fc2w.set_nodeattr(\"inFIFODepth\", 4)\n",
"fc2w.set_nodeattr(\"SIMD\", 16)\n",
"fc2w.set_nodeattr(\"PE\", 16)\n",
"fc2w.set_nodeattr(\"outFIFODepth\", 4)\n",
"\n",
+ "fc3w.set_nodeattr(\"inFIFODepth\", 4)\n",
"fc3w.set_nodeattr(\"SIMD\", 16)\n",
"fc3w.set_nodeattr(\"PE\", 10)\n",
- "fc3w.set_nodeattr(\"outFIFODepth\", 50)"
+ "fc3w.set_nodeattr(\"outFIFODepth\", 50)\n"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
- "Finally, we will run the `InsertTLastMarker` transformation to get a `TLastMarker` node at the output of this graph, which is necessary to run the DMA engines correctly. "
+ "After setting the FIFO node attributes, we can insert FIFO nodes inbetween the fpgadataflow nodes and in the beginning and end of the graph. This can be done using the transformation `InsertFIFO`."
]
},
{
"cell_type": "code",
- "execution_count": 21,
+ "execution_count": 17,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO\n",
+ "model = model.transform(InsertFIFO())"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Finally, we will run the `InsertTLastMarker` transformation to get a `TLastMarker` node at the output of this graph, which is necessary to run the DMA engines correctly. Using netron we can observe that now the nodes contain the set folding, inbetween the nodes are FIFOs inserted and the last node is the `TLastMarker` node we insert in the following."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 18,
"metadata": {},
"outputs": [
{
@@ -840,10 +870,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f1868061d30>"
+ "<IPython.lib.display.IFrame at 0x7f43177c7518>"
]
},
- "execution_count": 21,
+ "execution_count": 17,
"metadata": {},
"output_type": "execute_result"
}
@@ -866,7 +896,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "## 3. Vivado HLS and Vivado IPI <a id='vivado'></a>\n",
+ "## 3. Vivado HLS and IPI <a id='vivado'></a>\n",
"* [Generating HLS Code](#hls_per_layer)\n",
"* [Synthesizing HLS to IP Blocks](#hls_synth)\n",
"* [IP Stitching](#ip_stitching)\n",
@@ -876,14 +906,14 @@
},
{
"cell_type": "code",
- "execution_count": 22,
+ "execution_count": 19,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
- "dict_keys(['Ultra96', 'Pynq-Z1'])\n"
+ "dict_keys(['Ultra96', 'Pynq-Z1', 'Pynq-Z2', 'ZCU104'])\n"
]
}
],
@@ -895,14 +925,14 @@
},
{
"cell_type": "code",
- "execution_count": 23,
+ "execution_count": 20,
"metadata": {},
"outputs": [],
"source": [
"# change this if you have a different PYNQ board, see list above\n",
- "pynq_board = \"Ultra96\"\n",
+ "pynq_board = \"Pynq-Z1\"\n",
"fpga_part = pynq_part_map[pynq_board]\n",
- "target_clk_ns = 5"
+ "target_clk_ns = 10"
]
},
{
@@ -926,7 +956,7 @@
},
{
"cell_type": "code",
- "execution_count": 24,
+ "execution_count": 21,
"metadata": {},
"outputs": [],
"source": [
@@ -948,7 +978,7 @@
},
{
"cell_type": "code",
- "execution_count": 25,
+ "execution_count": 22,
"metadata": {},
"outputs": [],
"source": [
@@ -967,7 +997,7 @@
},
{
"cell_type": "code",
- "execution_count": 26,
+ "execution_count": 23,
"metadata": {},
"outputs": [
{
@@ -993,10 +1023,10 @@
" "
],
"text/plain": [
- "<IPython.lib.display.IFrame at 0x7f17f04c9470>"
+ "<IPython.lib.display.IFrame at 0x7f42977edf60>"
]
},
- "execution_count": 26,
+ "execution_count": 23,
"metadata": {},
"output_type": "execute_result"
}
@@ -1018,17 +1048,14 @@
},
{
"cell_type": "code",
- "execution_count": 27,
+ "execution_count": 24,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
- "hls_syn_StreamingFCLayer_Batch_0.tcl thresh.h\r\n",
- "ipgen.sh\t\t\t top_StreamingFCLayer_Batch_0.cpp\r\n",
- "params.h\t\t\t vivado_hls.log\r\n",
- "project_StreamingFCLayer_Batch_0\r\n"
+ "project_StreamingFIFO_0\r\n"
]
}
],
@@ -1047,7 +1074,7 @@
},
{
"cell_type": "code",
- "execution_count": 28,
+ "execution_count": 25,
"metadata": {},
"outputs": [
{
@@ -1055,8 +1082,8 @@
"output_type": "stream",
"text": [
"#!/bin/bash \r\n",
- "cd /tmp/finn_maltanar/code_gen_ipgen_StreamingFCLayer_Batch_5f0hmok_\r\n",
- "vivado_hls /tmp/finn_maltanar/code_gen_ipgen_StreamingFCLayer_Batch_5f0hmok_/hls_syn_StreamingFCLayer_Batch_0.tcl\r\n",
+ "cd /tmp/finn_jakobap/code_gen_ipgen_StreamingFCLayer_Batch_0_pfp8r_i6\r\n",
+ "vivado_hls /tmp/finn_jakobap/code_gen_ipgen_StreamingFCLayer_Batch_0_pfp8r_i6/hls_syn_StreamingFCLayer_Batch_0.tcl\r\n",
"cd /workspace/finn\r\n"
]
}
@@ -1077,7 +1104,7 @@
},
{
"cell_type": "code",
- "execution_count": 29,
+ "execution_count": 26,
"metadata": {},
"outputs": [
{
@@ -1087,9 +1114,9 @@
"\r\n",
"set config_proj_name project_StreamingFCLayer_Batch_0\r\n",
"puts \"HLS project: $config_proj_name\"\r\n",
- "set config_hwsrcdir \"/tmp/finn_maltanar/code_gen_ipgen_StreamingFCLayer_Batch_5f0hmok_\"\r\n",
+ "set config_hwsrcdir \"/tmp/finn_jakobap/code_gen_ipgen_StreamingFCLayer_Batch_0_pfp8r_i6\"\r\n",
"puts \"HW source dir: $config_hwsrcdir\"\r\n",
- "set config_proj_part \"xczu3eg-sbva484-1-e\"\r\n",
+ "set config_proj_part \"xc7z020clg400-1\"\r\n",
"\r\n",
"set config_bnnlibdir \"/workspace/finn-hlslib\"\r\n",
"\r\n",
@@ -1138,7 +1165,7 @@
},
{
"cell_type": "code",
- "execution_count": 30,
+ "execution_count": 27,
"metadata": {},
"outputs": [],
"source": [
@@ -1158,22 +1185,22 @@
},
{
"cell_type": "code",
- "execution_count": 31,
+ "execution_count": 28,
"metadata": {},
"outputs": [
{
"data": {
"text/plain": [
"[key: \"vivado_stitch_proj\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j\"\n",
", key: \"vivado_stitch_vlnv\"\n",
"value: \"xilinx_finn:finn:finn_design:1.0\"\n",
", key: \"wrapper_filename\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
"]"
]
},
- "execution_count": 31,
+ "execution_count": 28,
"metadata": {},
"output_type": "execute_result"
}
@@ -1184,16 +1211,16 @@
},
{
"cell_type": "code",
- "execution_count": 32,
+ "execution_count": 29,
"metadata": {},
"outputs": [
{
"data": {
"text/plain": [
- "'/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo'"
+ "'/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j'"
]
},
- "execution_count": 32,
+ "execution_count": 29,
"metadata": {},
"output_type": "execute_result"
}
@@ -1218,7 +1245,7 @@
},
{
"cell_type": "code",
- "execution_count": 33,
+ "execution_count": 30,
"metadata": {},
"outputs": [],
"source": [
@@ -1236,7 +1263,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "## 4. Synthesize, Deploy and Test on PYNQ <a id='hw_test'></a>\n",
+ "## 4. PYNQ hardware generation and deployment <a id='hw_test'></a>\n",
"\n",
"* [Inserting the IP into a PYNQ Overlay Shell](#pynq_shell)\n",
"* [Synthesis, place and route](#synth_pl_ro)\n",
@@ -1258,7 +1285,7 @@
},
{
"cell_type": "code",
- "execution_count": 34,
+ "execution_count": 31,
"metadata": {
"scrolled": true
},
@@ -1267,17 +1294,19 @@
"data": {
"text/plain": [
"[key: \"vivado_stitch_proj\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j\"\n",
", key: \"vivado_stitch_vlnv\"\n",
"value: \"xilinx_finn:finn:finn_design:1.0\"\n",
", key: \"wrapper_filename\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
", key: \"vivado_pynq_proj\"\n",
- "value: \"/tmp/finn_maltanar/vivado_pynq_proj_hq9mfroo\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j\"\n",
+ ", key: \"vivado_synth_rpt\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j/synth_report.xml\"\n",
"]"
]
},
- "execution_count": 34,
+ "execution_count": 31,
"metadata": {},
"output_type": "execute_result"
}
@@ -1291,7 +1320,7 @@
},
{
"cell_type": "code",
- "execution_count": 35,
+ "execution_count": 32,
"metadata": {},
"outputs": [
{
@@ -1317,7 +1346,7 @@
},
{
"cell_type": "code",
- "execution_count": 36,
+ "execution_count": 33,
"metadata": {},
"outputs": [],
"source": [
@@ -1340,26 +1369,30 @@
},
{
"cell_type": "code",
- "execution_count": 37,
- "metadata": {},
+ "execution_count": 34,
+ "metadata": {
+ "scrolled": true
+ },
"outputs": [
{
"data": {
"text/plain": [
"[key: \"vivado_stitch_proj\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j\"\n",
", key: \"vivado_stitch_vlnv\"\n",
"value: \"xilinx_finn:finn:finn_design:1.0\"\n",
", key: \"wrapper_filename\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
", key: \"vivado_pynq_proj\"\n",
- "value: \"/tmp/finn_maltanar/vivado_pynq_proj_hq9mfroo\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j\"\n",
+ ", key: \"vivado_synth_rpt\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j/synth_report.xml\"\n",
", key: \"vivado_pynq_bitfile\"\n",
- "value: \"/tmp/finn_maltanar/vivado_pynq_proj_hq9mfroo/resizer.bit\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j/resizer.bit\"\n",
"]"
]
},
- "execution_count": 37,
+ "execution_count": 34,
"metadata": {},
"output_type": "execute_result"
}
@@ -1373,7 +1406,7 @@
},
{
"cell_type": "code",
- "execution_count": 38,
+ "execution_count": 35,
"metadata": {},
"outputs": [],
"source": [
@@ -1391,7 +1424,7 @@
},
{
"cell_type": "code",
- "execution_count": 39,
+ "execution_count": 36,
"metadata": {},
"outputs": [],
"source": [
@@ -1409,74 +1442,131 @@
},
{
"cell_type": "code",
- "execution_count": 40,
+ "execution_count": 44,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
+ "\r\n",
+ "import argparse\r\n",
"\r\n",
"from pynq import Overlay\r\n",
"import numpy as np\r\n",
"from pynq import allocate\r\n",
+ "import time\r\n",
"from finn.util.data_packing import (\r\n",
" finnpy_to_packed_bytearray,\r\n",
" packed_bytearray_to_finnpy\r\n",
")\r\n",
"from finn.core.datatype import DataType\r\n",
"\r\n",
- "bitfile_path = \"resizer.bit\"\r\n",
- "ol = Overlay(bitfile_path)\r\n",
- "dma=ol.axi_dma_0\r\n",
+ "def load_input(N):\r\n",
+ " ishape_normal = (N, 784)\r\n",
+ " # load desired input .npy file\r\n",
+ " ibuf_normal = np.load(\"input.npy\")\r\n",
+ " # ensure that shape is as expected\r\n",
+ " assert ibuf_normal.shape == ishape_normal\r\n",
+ " return ibuf_normal\r\n",
"\r\n",
- "# declare input/output types and shapes for the accelerator\r\n",
- "# input FINN DataType\r\n",
- "idt = DataType.BINARY\r\n",
- "# normal, folded and packed input shapes\r\n",
- "ishape_normal = (1, 784)\r\n",
- "ishape_folded = (1, 49, 16)\r\n",
- "ishape_packed = (1, 49, 2)\r\n",
- "# output FINN DataType\r\n",
- "odt = DataType.UINT32\r\n",
- "# normal, folded and packed output shapes\r\n",
- "oshape_normal = (1, 10)\r\n",
- "oshape_folded = (1, 1, 10)\r\n",
- "oshape_packed = (1, 1, 40)\r\n",
+ "def pack_input(ibuf_normal, N):\r\n",
+ " # input FINN DataType\r\n",
+ " idt = DataType.BINARY\r\n",
+ " ishape_folded = (N, 49, 16)\r\n",
+ " # convert to folded form\r\n",
+ " ibuf_folded = ibuf_normal.reshape(ishape_folded)\r\n",
+ " # pack the input buffer, reversing both SIMD dim and endianness\r\n",
+ " ibuf_packed = finnpy_to_packed_bytearray(\r\n",
+ " ibuf_folded, idt, reverse_endian=True, reverse_inner=True\r\n",
+ " )\r\n",
+ " return ibuf_packed\r\n",
"\r\n",
- "# load desired input .npy file\r\n",
- "ibuf_normal = np.load(\"input.npy\")\r\n",
- "# ensure that shape is as expected\r\n",
- "assert ibuf_normal.shape == ishape_normal\r\n",
- "# convert to folded form\r\n",
- "ibuf_folded = ibuf_normal.reshape(ishape_folded)\r\n",
+ "def unpack_output(obuf_packed, N):\r\n",
+ " # output FINN DataType\r\n",
+ " odt = DataType.UINT32\r\n",
+ " oshape_folded = (N, 1, 10)\r\n",
+ " # unpack the packed output buffer from accelerator\r\n",
+ " obuf_folded = packed_bytearray_to_finnpy(\r\n",
+ " obuf_packed, odt, oshape_folded, reverse_endian=True, reverse_inner=True\r\n",
+ " )\r\n",
+ " return obuf_folded\r\n",
"\r\n",
- "# pack the input buffer, reversing both SIMD dim and endianness\r\n",
- "ibuf_packed = finnpy_to_packed_bytearray(\r\n",
- " ibuf_folded, idt, reverse_endian=True, reverse_inner=True\r\n",
- ")\r\n",
- "# allocate a PYNQ buffer for the packed input buffer\r\n",
- "ibuf_packed_device = allocate(shape=ishape_packed, dtype=np.uint8)\r\n",
- "# copy the packed data into the PYNQ buffer\r\n",
- "# TODO optimization: pack directly into the PYNQ buffer?\r\n",
- "np.copyto(ibuf_packed_device, ibuf_packed)\r\n",
+ "def save_output(obuf_folded, N):\r\n",
+ " # convert to normal reshape and save\r\n",
+ " oshape_normal = (N, 10)\r\n",
+ " obuf_normal = obuf_folded.reshape(oshape_normal)\r\n",
+ " np.save(\"output.npy\", obuf_normal)\r\n",
"\r\n",
- "# allocate a PYNQ buffer for the returned packed output buffer\r\n",
- "obuf_packed = allocate(shape=oshape_packed, dtype=np.uint8)\r\n",
+ "if __name__ == \"__main__\":\r\n",
+ " parser = argparse.ArgumentParser(description='Please select functional verification (\"remote_pynq\") or throughput test (\"throughput_test\")')\r\n",
+ " parser.add_argument('exec_mode', help='metadata prop exec_mode as string')\r\n",
+ " args = parser.parse_args()\r\n",
+ " exec_mode = args.exec_mode\r\n",
"\r\n",
- "# set up the DMA and wait until all transfers complete\r\n",
- "dma.sendchannel.transfer(ibuf_packed_device)\r\n",
- "dma.recvchannel.transfer(obuf_packed)\r\n",
- "dma.sendchannel.wait()\r\n",
- "dma.recvchannel.wait()\r\n",
+ " bitfile_path = \"resizer.bit\"\r\n",
+ " ol = Overlay(bitfile_path)\r\n",
+ " dma=ol.axi_dma_0\r\n",
+ " ctrl_regs=ol.resize_accel_0\r\n",
+ " # AXI lite register offset for number of iterations\r\n",
+ " # used by TLastMarker to signal end of transmission for AXI CDMA\r\n",
+ " REG_OFFSET_NUM_ITERS = 0x10\r\n",
"\r\n",
- "# unpack the packed output buffer from accelerator\r\n",
- "obuf_folded = packed_bytearray_to_finnpy(\r\n",
- " obuf_packed, odt, oshape_folded, reverse_endian=True, reverse_inner=True\r\n",
- ")\r\n",
- "# convert to normal reshape and save\r\n",
- "obuf_normal = obuf_folded.reshape(oshape_normal)\r\n",
- "np.save(\"output.npy\", obuf_normal)\r\n"
+ " # number of samples for inference\r\n",
+ " if exec_mode == \"remote_pynq\":\r\n",
+ " N = 1\r\n",
+ " elif exec_mode == \"throughput_test\":\r\n",
+ " res={}\r\n",
+ " N = 1000\r\n",
+ " else:\r\n",
+ " raise Exception(\"Exec mode has to be set to remote_pynq or throughput_test\")\r\n",
+ "\r\n",
+ " # declare input/output types and shapes for the accelerator\r\n",
+ " ishape_packed = (N, 49, 2)\r\n",
+ " oshape_packed = (N, 1, 40)\r\n",
+ " \r\n",
+ " if exec_mode == \"remote_pynq\":\r\n",
+ " ibuf_normal = load_input(N)\r\n",
+ " ibuf_packed = pack_input(ibuf_normal, N)\r\n",
+ " elif exec_mode == \"throughput_test\":\r\n",
+ " ibuf_packed = np.asarray(np.random.uniform(low=0, high=1, size=tuple(ishape_packed)), dtype=np.uint8)\r\n",
+ "\r\n",
+ " # set up TLastMarker with correct num. samples\r\n",
+ " ctrl_regs.write(REG_OFFSET_NUM_ITERS, N)\r\n",
+ "\r\n",
+ " # allocate a PYNQ buffer for the packed input buffer\r\n",
+ " ibuf_packed_device = allocate(shape=ishape_packed, dtype=np.uint8)\r\n",
+ " # copy the packed data into the PYNQ buffer\r\n",
+ " # TODO optimization: pack directly into the PYNQ buffer?\r\n",
+ " np.copyto(ibuf_packed_device, ibuf_packed)\r\n",
+ "\r\n",
+ " # allocate a PYNQ buffer for the returned packed output buffer\r\n",
+ " obuf_packed = allocate(shape=oshape_packed, dtype=np.uint8)\r\n",
+ "\r\n",
+ " if exec_mode == \"throughput_test\":\r\n",
+ " # measure runtime of network\r\n",
+ " start = time.time()\r\n",
+ "\r\n",
+ " # set up the DMA and wait until all transfers complete\r\n",
+ " dma.sendchannel.transfer(ibuf_packed_device)\r\n",
+ " dma.recvchannel.transfer(obuf_packed)\r\n",
+ " dma.sendchannel.wait()\r\n",
+ " dma.recvchannel.wait()\r\n",
+ "\r\n",
+ "\r\n",
+ " if exec_mode == \"throughput_test\":\r\n",
+ " end = time.time()\r\n",
+ " runtime = end - start\r\n",
+ " res[\"runtime[ms]\"] = runtime*1000\r\n",
+ " res[\"throughput[images/s]\"] = N / runtime\r\n",
+ " file = open(\"nw_metrics.txt\", \"w\")\r\n",
+ " file.write(str(res))\r\n",
+ " file.close()\r\n",
+ "\r\n",
+ " else:\r\n",
+ " obuf_folded = unpack_output(obuf_packed, N)\r\n",
+ " save_output(obuf_folded, N)\r\n",
+ "\r\n"
]
}
],
@@ -1503,16 +1593,17 @@
},
{
"cell_type": "code",
- "execution_count": 41,
+ "execution_count": 57,
"metadata": {},
"outputs": [],
"source": [
"from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ\n",
- "ip = \"192.168.3.1\"\n",
+ "ip = \"51.37.26.64\"\n",
+ "port = \"23\"\n",
"username = \"xilinx\"\n",
- "password = \"xilinx\"\n",
+ "password = \"x1l1nx_f1nn\"\n",
"target_dir = \"/home/xilinx/finn_tfc_end2end_example\"\n",
- "model = model.transform(DeployToPYNQ(ip, username, password, target_dir))\n",
+ "model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))\n",
"model.save(build_dir + \"/tfc_w1_a1_pynq_deploy.onnx\")"
]
},
@@ -1525,42 +1616,46 @@
},
{
"cell_type": "code",
- "execution_count": 42,
+ "execution_count": 58,
"metadata": {},
"outputs": [
{
"data": {
"text/plain": [
"[key: \"vivado_stitch_proj\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j\"\n",
", key: \"vivado_stitch_vlnv\"\n",
"value: \"xilinx_finn:finn:finn_design:1.0\"\n",
", key: \"wrapper_filename\"\n",
- "value: \"/tmp/finn_maltanar/vivado_stitch_proj_oo2lpoeo/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_stitch_proj_tqp4ib4j/finn_vivado_stitch_proj.srcs/sources_1/bd/finn_design/hdl/finn_design_wrapper.v\"\n",
", key: \"vivado_pynq_proj\"\n",
- "value: \"/tmp/finn_maltanar/vivado_pynq_proj_hq9mfroo\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j\"\n",
+ ", key: \"vivado_synth_rpt\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j/synth_report.xml\"\n",
", key: \"vivado_pynq_bitfile\"\n",
- "value: \"/tmp/finn_maltanar/vivado_pynq_proj_hq9mfroo/resizer.bit\"\n",
+ "value: \"/tmp/finn_jakobap/vivado_pynq_proj_gkwfg31j/resizer.bit\"\n",
", key: \"pynq_driver_dir\"\n",
- "value: \"/tmp/finn_maltanar/pynq_driver_25t8u9sd\"\n",
+ "value: \"/tmp/finn_jakobap/pynq_driver_1r1_0kz6\"\n",
", key: \"pynq_ip\"\n",
- "value: \"192.168.3.1\"\n",
+ "value: \"51.37.26.64\"\n",
+ ", key: \"pynq_port\"\n",
+ "value: \"23\"\n",
", key: \"pynq_username\"\n",
"value: \"xilinx\"\n",
", key: \"pynq_password\"\n",
- "value: \"xilinx\"\n",
+ "value: \"x1l1nx_f1nn\"\n",
", key: \"pynq_target_dir\"\n",
"value: \"/home/xilinx/finn_tfc_end2end_example\"\n",
", key: \"pynq_deployment_dir\"\n",
- "value: \"/tmp/finn_maltanar/pynq_deployment_mpyziv7h\"\n",
+ "value: \"/tmp/finn_jakobap/pynq_deployment_kvurnk0c\"\n",
", key: \"pynq_deploy_dir\"\n",
- "value: \"/tmp/finn_maltanar/pynq_deployment_mpyziv7h\"\n",
+ "value: \"/tmp/finn_jakobap/pynq_deployment_kvurnk0c\"\n",
", key: \"exec_mode\"\n",
"value: \"remote_pynq\"\n",
"]"
]
},
- "execution_count": 42,
+ "execution_count": 58,
"metadata": {},
"output_type": "execute_result"
}
@@ -1571,34 +1666,23 @@
},
{
"cell_type": "code",
- "execution_count": 43,
+ "execution_count": 59,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
- "/home/xilinx/finn_tfc_end2end_example/pynq_deployment_1oyo7x66:\r\n",
- "total 5820\r\n",
- "-rw-r--r-- 1 xilinx xilinx 1934 Feb 13 13:36 driver.py\r\n",
- "drwxr-xr-x 4 xilinx xilinx 4096 Feb 13 13:36 finn\r\n",
- "-rw-r--r-- 1 xilinx xilinx 3264 Feb 13 14:24 input.npy\r\n",
- "-rw-r--r-- 1 root root 120 Feb 13 14:24 output.npy\r\n",
- "-rw-r--r-- 1 xilinx xilinx 5568787 Feb 13 13:36 resizer.bit\r\n",
- "-rw-r--r-- 1 xilinx xilinx 368173 Feb 13 13:36 resizer.hwh\r\n",
- "-rw-r--r-- 1 root root 32 Feb 13 14:24 sds_trace_data.dat\r\n",
- "\r\n",
- "/home/xilinx/finn_tfc_end2end_example/pynq_deployment_mpyziv7h:\r\n",
- "total 5808\r\n",
- "-rw-r--r-- 1 xilinx xilinx 1934 Feb 28 16:09 driver.py\r\n",
- "drwxr-xr-x 4 xilinx xilinx 4096 Feb 28 16:09 finn\r\n",
- "-rw-r--r-- 1 xilinx xilinx 5568787 Feb 28 16:09 resizer.bit\r\n",
- "-rw-r--r-- 1 xilinx xilinx 368173 Feb 28 16:09 resizer.hwh\r\n"
+ "total 4284\r\n",
+ "-rw-r--r-- 1 xilinx xilinx 3861 Apr 27 12:36 driver.py\r\n",
+ "drwxr-xr-x 4 xilinx xilinx 4096 Apr 27 12:37 finn\r\n",
+ "-rw-r--r-- 1 xilinx xilinx 4045675 Apr 27 12:36 resizer.bit\r\n",
+ "-rw-r--r-- 1 xilinx xilinx 329531 Apr 27 12:36 resizer.hwh\r\n"
]
}
],
"source": [
- "! sshpass -p {password} ssh {username}@{ip} 'ls -l {target_dir}/*'"
+ "! sshpass -p {password} ssh {username}@{ip} -p {port} 'ls -l {target_dir}/*'"
]
},
{
@@ -1610,16 +1694,16 @@
},
{
"cell_type": "code",
- "execution_count": 44,
+ "execution_count": 60,
"metadata": {},
"outputs": [
{
"data": {
"text/plain": [
- "<matplotlib.image.AxesImage at 0x7f17e0a82e10>"
+ "<matplotlib.image.AxesImage at 0x7f4277550ef0>"
]
},
- "execution_count": 44,
+ "execution_count": 60,
"metadata": {},
"output_type": "execute_result"
}
@@ -1643,7 +1727,7 @@
},
{
"cell_type": "code",
- "execution_count": 45,
+ "execution_count": 61,
"metadata": {},
"outputs": [],
"source": [
@@ -1663,7 +1747,7 @@
},
{
"cell_type": "code",
- "execution_count": 48,
+ "execution_count": 62,
"metadata": {},
"outputs": [],
"source": [
@@ -1685,7 +1769,7 @@
},
{
"cell_type": "code",
- "execution_count": 49,
+ "execution_count": 63,
"metadata": {},
"outputs": [
{
@@ -1694,13 +1778,13 @@
"<BarContainer object of 10 artists>"
]
},
- "execution_count": 49,
+ "execution_count": 63,
"metadata": {},
"output_type": "execute_result"
},
{
"data": {
- "image/png": "iVBORw0KGgoAAAANSUhEUgAAAXQAAAD4CAYAAAD8Zh1EAAAABHNCSVQICAgIfAhkiAAAAAlwSFlzAAALEgAACxIB0t1+/AAAADh0RVh0U29mdHdhcmUAbWF0cGxvdGxpYiB2ZXJzaW9uMy4xLjMsIGh0dHA6Ly9tYXRwbG90bGliLm9yZy+AADFEAAAMoUlEQVR4nO3cf6jd913H8edryercD1sxV9AkLgEzNQyl5dJVC1pshbSV5A9FGqjoKMs/y6yuKJlKHfWfzcn8gXUa5xzO2azWIcFGI7iKILbkdp11SYxcstrcrNK7rtYfQ7Pg2z/uiZzd3ptzkp57T/u+zwcEzvf7/XC+75ObPDn3e36kqpAkvfa9btoDSJImw6BLUhMGXZKaMOiS1IRBl6QmNk/rxFu2bKkdO3ZM6/SS9Jr05JNPfqmqZlY6NrWg79ixg7m5uWmdXpJek5L8y2rHvOQiSU0YdElqwqBLUhMjg57kY0meT/L5VY4nyW8mmU/ydJIbJj+mJGmUcZ6hfxzYc5njtwO7Bn8OAB955WNJkq7UyKBX1d8CX77Mkn3AH9aSx4HrknzLpAaUJI1nEtfQtwLnhrYXBvteJsmBJHNJ5hYXFydwaknSJev6omhVHa6q2aqanZlZ8X3xkqSrNImgnwe2D21vG+yTJK2jSXxS9ChwMMkR4B3AS1X13ATuV8vsOPTomp/jmQ/cuebnkLQ2RgY9yUPALcCWJAvALwGvB6iq3wGOAXcA88BXgHeu1bCSpNWNDHpV7R9xvIB3T2wiSdJV8ZOiktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1MRYQU+yJ8mZJPNJDq1w/NuSPJbkqSRPJ7lj8qNKki5nZNCTbAIeBG4HdgP7k+xetuwXgYer6nrgLuC3Jz2oJOnyxnmGfiMwX1Vnq+oCcATYt2xNAd8wuH0t8MXJjShJGsc4Qd8KnBvaXhjsG/Z+4O4kC8Ax4D0r3VGSA0nmkswtLi5exbiSpNVM6kXR/cDHq2obcAfwiSQvu++qOlxVs1U1OzMzM6FTS5JgvKCfB7YPbW8b7Bt2D/AwQFX9PfAGYMskBpQkjWecoJ8AdiXZmeQall70PLpszbPArQBJvouloHtNRZLW0cigV9VF4CBwHDjN0rtZTiZ5IMnewbL7gHcl+QfgIeAnq6rWamhJ0sttHmdRVR1j6cXO4X33D90+Bdw82dEkSVfCT4pKUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSE2MFPcmeJGeSzCc5tMqaH0tyKsnJJH882TElSaNsHrUgySbgQeCHgAXgRJKjVXVqaM0u4H3AzVX1YpJvXquBJUkrG+cZ+o3AfFWdraoLwBFg37I17wIerKoXAarq+cmOKUkaZZygbwXODW0vDPYNexvwtiR/l+TxJHtWuqMkB5LMJZlbXFy8uoklSSua1Iuim4FdwC3AfuD3kly3fFFVHa6q2aqanZmZmdCpJUkwXtDPA9uHtrcN9g1bAI5W1Ver6gvAP7MUeEnSOhkn6CeAXUl2JrkGuAs4umzNn7H07JwkW1i6BHN2gnNKkkYYGfSquggcBI4Dp4GHq+pkkgeS7B0sOw68kOQU8Bjws1X1wloNLUl6uZFvWwSoqmPAsWX77h+6XcB7B38kSVPgJ0UlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpibGCnmRPkjNJ5pMcusy6H0lSSWYnN6IkaRwjg55kE/AgcDuwG9ifZPcK694C3As8MekhJUmjjfMM/UZgvqrOVtUF4Aiwb4V1vwx8EPjvCc4nSRrTOEHfCpwb2l4Y7Pt/SW4AtlfVo5e7oyQHkswlmVtcXLziYSVJq3vFL4omeR3wYeC+UWur6nBVzVbV7MzMzCs9tSRpyDhBPw9sH9reNth3yVuAtwN/k+QZ4CbgqC+MStL6GifoJ4BdSXYmuQa4Czh66WBVvVRVW6pqR1XtAB4H9lbV3JpMLEla0cigV9VF4CBwHDgNPFxVJ5M8kGTvWg8oSRrP5nEWVdUx4NiyffevsvaWVz6WJOlK+UlRSWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJamKsoCfZk+RMkvkkh1Y4/t4kp5I8neSvk7x18qNKki5nZNCTbAIeBG4HdgP7k+xetuwpYLaqvht4BPiVSQ8qSbq8cZ6h3wjMV9XZqroAHAH2DS+oqseq6iuDzceBbZMdU5I0yjhB3wqcG9peGOxbzT3AX6x0IMmBJHNJ5hYXF8efUpI00kRfFE1yNzALfGil41V1uKpmq2p2ZmZmkqeWpA1v8xhrzgPbh7a3DfZ9jSS3Ab8A/EBV/c9kxpMkjWucZ+gngF1Jdia5BrgLODq8IMn1wO8Ce6vq+cmPKUkaZWTQq+oicBA4DpwGHq6qk0keSLJ3sOxDwJuBP0nyuSRHV7k7SdIaGeeSC1V1DDi2bN/9Q7dvm/BckqQr5CdFJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqYmxgp5kT5IzSeaTHFrh+Ncl+dTg+BNJdkx6UEnS5Y0MepJNwIPA7cBuYH+S3cuW3QO8WFXfDvwa8MFJDypJurzNY6y5EZivqrMASY4A+4BTQ2v2Ae8f3H4E+K0kqaqa4Kyaoh2HHl3zczzzgTvX/ByvNWv99+7feS/jBH0rcG5oewF4x2prqupikpeAbwK+NLwoyQHgwGDzP5OcuZqhr9KW5fNsEFf0uDPF360mfG5/3mOY5s97wjbSz/utqx0YJ+gTU1WHgcPrec5LksxV1ew0zj1NPu6Nxce9sY3zouh5YPvQ9rbBvhXXJNkMXAu8MIkBJUnjGSfoJ4BdSXYmuQa4Czi6bM1R4CcGt38U+IzXzyVpfY285DK4Jn4QOA5sAj5WVSeTPADMVdVR4PeBTySZB77MUvRfbaZyqedVwMe9sfi4N7D4RFqSevCTopLUhEGXpCbaB33U1xZ0lGR7kseSnEpyMsm9055pPSXZlOSpJH8+7VnWU5LrkjyS5J+SnE7yvdOeaT0k+ZnBv/PPJ3koyRumPdO0tA76mF9b0NFF4L6q2g3cBLx7gzzuS+4FTk97iCn4DeAvq+o7ge9hA/wdJNkK/BQwW1VvZ+mNG6/GN2Wsi9ZBZ+hrC6rqAnDpawtaq6rnquqzg9v/wdJ/7K3TnWp9JNkG3Al8dNqzrKck1wLfz9I7zqiqC1X1b9Odat1sBr5+8BmYNwJfnPI8U9M96Ct9bcGGCNslg2++vB54YrqTrJtfB34O+N9pD7LOdgKLwB8MLjd9NMmbpj3UWquq88CvAs8CzwEvVdVfTXeq6eke9A0tyZuBPwV+uqr+fdrzrLUkPww8X1VPTnuWKdgM3AB8pKquB/4LaP+aUZJvZOm37p3AtwJvSnL3dKeanu5BH+drC1pK8nqWYv7Jqvr0tOdZJzcDe5M8w9LltR9M8kfTHWndLAALVXXpN7FHWAp8d7cBX6iqxar6KvBp4PumPNPUdA/6OF9b0E6SsHQt9XRVfXja86yXqnpfVW2rqh0s/aw/U1Ub4tlaVf0rcC7Jdwx23crXfsV1V88CNyV54+Df/a1sgBeDV7Ou37a43lb72oIpj7UebgZ+HPjHJJ8b7Pv5qjo2xZm09t4DfHLw5OUs8M4pz7PmquqJJI8An2Xp3V1PsYG/BsCP/ktSE90vuUjShmHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUxP8BwjHuoBhu1y0AAAAASUVORK5CYII=\n",
+ "image/png": "iVBORw0KGgoAAAANSUhEUgAAAXQAAAD4CAYAAAD8Zh1EAAAABHNCSVQICAgIfAhkiAAAAAlwSFlzAAALEgAACxIB0t1+/AAAADh0RVh0U29mdHdhcmUAbWF0cGxvdGxpYiB2ZXJzaW9uMy4xLjMsIGh0dHA6Ly9tYXRwbG90bGliLm9yZy+AADFEAAAMp0lEQVR4nO3cf6zdd13H8eeL1qoMgia7f2jbcRttMA2iI9cyJUHDZtJlpjVhJl0CYQbSmFCZQqKdmv1R/4Fhpv7RGJoxQxQsOPnj4qrVCP7hHyy9+xGgq43XOtdWDHeAYDRaGt7+0VNyvLvt/XY79572fZ+PZMn5fr+f3O/7bN0z336/95xUFZKkm9+rpj2AJGkyDLokNWHQJakJgy5JTRh0SWpi87ROfOutt9bs7Oy0Ti9JN6WnnnrqxaqaWenY1II+OzvLwsLCtE4vSTelJP96tWPecpGkJgy6JDVh0CWpCYMuSU0MCnqSPUnOJFlMcmiF4/cnWUry7Oif905+VEnStaz6Wy5JNgFHgJ8HzgMnk8xX1XPLln6qqg6uwYySpAGGXKHvBhar6mxVXQSOAfvWdixJ0vUaEvStwLmx7fOjfcu9I8kXkzyeZPtKPyjJgSQLSRaWlpZexriSpKuZ1EPRzwKzVfUm4G+Bj6+0qKqOVtVcVc3NzKz4QSdJ0ss05JOiF4DxK+5to33fVVVfG9t8FHj4lY+m5WYPPbHm53j+Q/es+TkkrY0hV+gngZ1JdiTZAuwH5scXJPmhsc29wOnJjShJGmLVK/SqupTkIHAC2AQ8VlWnkhwGFqpqHnh/kr3AJeDrwP1rOLMkaQWDvpyrqo4Dx5fte2js9YPAg5MdTZJ0PfykqCQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgYFPcmeJGeSLCY5dI1170hSSeYmN6IkaYhVg55kE3AEuBvYBdyXZNcK614LPAA8OekhJUmrG3KFvhtYrKqzVXUROAbsW2Hd7wIfBv5ngvNJkgYaEvStwLmx7fOjfd+V5M3A9qp6YoKzSZKuwyt+KJrkVcAjwAcHrD2QZCHJwtLS0is9tSRpzJCgXwC2j21vG+274rXAG4G/T/I8cAcwv9KD0ao6WlVzVTU3MzPz8qeWJL3EkKCfBHYm2ZFkC7AfmL9ysKq+WVW3VtVsVc0CXwD2VtXCmkwsSVrRqkGvqkvAQeAEcBr4dFWdSnI4yd61HlCSNMzmIYuq6jhwfNm+h66y9ude+ViSpOvlJ0UlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpiUFBT7InyZkki0kOrXD8V5J8KcmzSf4hya7JjypJupZVg55kE3AEuBvYBdy3QrA/WVU/XlU/CTwMPDLxSSVJ1zTkCn03sFhVZ6vqInAM2De+oKq+NbZ5C1CTG1GSNMTmAWu2AufGts8Db1m+KMn7gA8AW4C3r/SDkhwADgDcdttt1zurJOkaJvZQtKqOVNWPAL8J/M5V1hytqrmqmpuZmZnUqSVJDAv6BWD72Pa20b6rOQb84isZSpJ0/YYE/SSwM8mOJFuA/cD8+IIkO8c27wH+aXIjSpKGWPUeelVdSnIQOAFsAh6rqlNJDgMLVTUPHExyF/Bt4BvAu9dyaEnSSw15KEpVHQeOL9v30NjrByY8lyTpOvlJUUlqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWpiUNCT7ElyJslikkMrHP9AkueSfDHJ3yV5/eRHlSRdy6pBT7IJOALcDewC7kuya9myZ4C5qnoT8Djw8KQHlSRd25Ar9N3AYlWdraqLwDFg3/iCqvp8Vf33aPMLwLbJjilJWs2QoG8Fzo1tnx/tu5r3AH+10oEkB5IsJFlYWloaPqUkaVUTfSia5J3AHPCRlY5X1dGqmququZmZmUmeWpI2vM0D1lwAto9tbxvt+3+S3AX8NvCzVfW/kxlPkjTUkCv0k8DOJDuSbAH2A/PjC5LcDnwU2FtVX538mJKk1awa9Kq6BBwETgCngU9X1akkh5PsHS37CPAa4M+TPJtk/io/TpK0RobccqGqjgPHl+17aOz1XROeS5J0nfykqCQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNWHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUhEGXpCYMuiQ1YdAlqQmDLklNGHRJasKgS1ITBl2SmjDoktSEQZekJgy6JDUxKOhJ9iQ5k2QxyaEVjr8tydNJLiW5d/JjSpJWs2rQk2wCjgB3A7uA+5LsWrbsBeB+4JOTHlCSNMzmAWt2A4tVdRYgyTFgH/DclQVV9fzo2HfWYEZJ0gBDbrlsBc6NbZ8f7btuSQ4kWUiysLS09HJ+hCTpKtb1oWhVHa2quaqam5mZWc9TS1J7Q4J+Adg+tr1ttE+SdAMZEvSTwM4kO5JsAfYD82s7liTpeq0a9Kq6BBwETgCngU9X1akkh5PsBUjyU0nOA78EfDTJqbUcWpL0UkN+y4WqOg4cX7bvobHXJ7l8K0aSNCV+UlSSmjDoktSEQZekJgy6JDUx6KGoJK2n2UNPrPk5nv/QPWt+jvVm0DWI/4NJNz5vuUhSEzflFbpXi5L0Ul6hS1ITBl2SmjDoktTETXkPXdLa81nVzceg66aw1nExLOrAWy6S1IRBl6QmvOUi3cC81aTrYdClVRhV3Sy85SJJTRh0SWrCoEtSE95Dv05+2ELSjcqgS9KYm/mizVsuktSEQZekJgy6JDVh0CWpCYMuSU0YdElqwqBLUhMGXZKaMOiS1IRBl6QmDLokNTEo6En2JDmTZDHJoRWOf2+ST42OP5lkdtKDSpKubdWgJ9kEHAHuBnYB9yXZtWzZe4BvVNWPAr8PfHjSg0qSrm3IFfpuYLGqzlbVReAYsG/Zmn3Ax0evHwfuTJLJjSlJWk2q6toLknuBPVX13tH2u4C3VNXBsTVfHq05P9r+59GaF5f9rAPAgdHmG4Azk3ojA9wKvLjqqn583xuL77u/11fVzEoH1vX70KvqKHB0Pc95RZKFqpqbxrmnyfe9sfi+N7Yht1wuANvHtreN9q24Jslm4HXA1yYxoCRpmCFBPwnsTLIjyRZgPzC/bM088O7R63uBz9Vq93IkSRO16i2XqrqU5CBwAtgEPFZVp5IcBhaqah74GPAnSRaBr3M5+jeaqdzquQH4vjcW3/cGtupDUUnSzcFPikpSEwZdkppoH/TVvragoyTbk3w+yXNJTiV5YNozrackm5I8k+Qvpz3LekryA0keT/KPSU4n+elpz7Qekvz66M/5l5P8WZLvm/ZM09I66AO/tqCjS8AHq2oXcAfwvg3yvq94ADg97SGm4A+Bv66qHwN+gg3w7yDJVuD9wFxVvZHLv7hxI/5SxrpoHXSGfW1BO1X1lap6evT6P7n8P/bW6U61PpJsA+4BHp32LOspyeuAt3H5N86oqotV9R/TnWrdbAa+f/QZmFcD/zbleaame9C3AufGts+zQcJ2xeibL28HnpzuJOvmD4DfAL4z7UHW2Q5gCfjj0e2mR5PcMu2h1lpVXQB+D3gB+Arwzar6m+lONT3dg76hJXkN8BfAr1XVt6Y9z1pL8gvAV6vqqWnPMgWbgTcDf1RVtwP/BbR/ZpTkB7n8t+4dwA8DtyR553Snmp7uQR/ytQUtJfkeLsf8E1X1mWnPs07eCuxN8jyXb6+9PcmfTnekdXMeOF9VV/4m9jiXA9/dXcC/VNVSVX0b+AzwM1OeaWq6B33I1xa0M/rq4o8Bp6vqkWnPs16q6sGq2lZVs1z+b/25qtoQV2tV9e/AuSRvGO26E3huiiOtlxeAO5K8evTn/k42wMPgq1nXb1tcb1f72oIpj7Ue3gq8C/hSkmdH+36rqo5PcSatvV8FPjG6eDkL/PKU51lzVfVkkseBp7n8213PsIG/BsCP/ktSE91vuUjShmHQJakJgy5JTRh0SWrCoEtSEwZdkpow6JLUxP8B9uoCk0KMtNwAAAAASUVORK5CYII=\n",
"text/plain": [
"<Figure size 432x288 with 1 Axes>"
]
@@ -1730,6 +1814,37 @@
"We see that the network correctly predicts this as a digit 2 with high probability. This concludes our tutorial on how to take a simple fully-connected BNN all the way down to hardware with FINN, and execute it remotely on a PYNQ board."
]
},
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Throughput Test on PYNQ Board <a id='throughput'></a>\n",
+ "In addition to the functional verification, FINN also offers the possibility to measure the network performance directly on the PYNQ board. This can be done using the core function `throughput_test`. In the next section we import the function and execute it.\n",
+ "First we extract the `remote_exec_model` again and pass it to the function. The function returns the metrics of the network as dictionary."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 66,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "Network metrics: \n",
+ "{'runtime[ms]': 3.5953521728515625, 'throughput[images/s]': 278136.8700265252}\n"
+ ]
+ }
+ ],
+ "source": [
+ "from finn.core.throughput_test import throughput_test\n",
+ "\n",
+ "child_model = ModelWrapper(getCustomOp(sdp_node).get_nodeattr(\"model\"))\n",
+ "res = throughput_test(child_model)\n",
+ "print(\"Network metrics: \\n\" + str(res))"
+ ]
+ },
{
"cell_type": "code",
"execution_count": null,
diff --git a/notebooks/end2end_example/tfc_end2end_verification.ipynb b/notebooks/end2end_example/tfc_end2end_verification.ipynb
index 6eab7220f20fc78b17cfb0745e69e60ead16b3a0..f03add2da37f1c7d0b33824fb0d1b9d19ba8f7fa 100644
--- a/notebooks/end2end_example/tfc_end2end_verification.ipynb
+++ b/notebooks/end2end_example/tfc_end2end_verification.ipynb
@@ -9,14 +9,14 @@
"\n",
"**Important: This notebook depends on the tfc_end2end_example notebook, because we are using models that are available at intermediate steps in the end-to-end flow. So please make sure the needed .onnx files are generated to run this notebook.**\n",
"\n",
- "In this notebook, we will show how to take the intermediate results of the end-to-end tfc example and verify their functionality with different methods. In the following picture you can see the block in the end-to-end flow about the *Simulation & Emulation flows for functional verification*. Besides the methods in this notebook, there is another one that is covered in the Jupyter notebook [tfc_end2end_example](tfc_end2end_example.ipynb): remote execution. The remote execution allows functional verification directly on the PYNQ board, for details please have a look at the mentioned Jupyter notebook."
+ "In this notebook, we will show how to take the intermediate results of the end-to-end tfc example and verify their functionality with different methods. In the following picture you can see the block in the end-to-end flow about the *Simulation & Emulation Flows*. Besides the methods in this notebook, there is another one that is covered in the Jupyter notebook [tfc_end2end_example](tfc_end2end_example.ipynb): remote execution. The remote execution allows functional verification directly on the PYNQ board, for details please have a look at the mentioned Jupyter notebook."
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
- ""
+ "<img src=\"verification.png\" alt=\"Drawing\" style=\"width: 500px;\"/>"
]
},
{
@@ -396,7 +396,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
- "### Emulation of model layer-by-layer\n",
+ "### Emulation of model node-by-node\n",
"\n",
"The child model is loaded and the `exec_mode` for each node is set. Then it is saved in a new .onnx file so that the changed model can be referenced in the parent model."
]
diff --git a/notebooks/end2end_example/verification.png b/notebooks/end2end_example/verification.png
index 71645fef72496258544641bb09e7b529656b8812..e95a4d98e3b6c5a46ad6d4c2749679831b740044 100755
Binary files a/notebooks/end2end_example/verification.png and b/notebooks/end2end_example/verification.png differ
diff --git a/run-docker.sh b/run-docker.sh
index a0a60731d98550c289439df6b3617b66acd58a56..018bd9aa8c39666a1b9c0ef7f426587f265769f7 100755
--- a/run-docker.sh
+++ b/run-docker.sh
@@ -44,10 +44,10 @@ DOCKER_PASSWD="finn"
# generate a random number per-run to allow multiple
# containers from the same user
DOCKER_RND=$(shuf -i0-32768 -n1)
-DOCKER_TAG="finn_${DOCKER_UNAME}"
+DOCKER_TAG="finn_dev_${DOCKER_UNAME}"
# uncomment to run multiple instances with different names
# DOCKER_INST_NAME="finn_${DOCKER_UNAME}_${DOCKER_RND}"
-DOCKER_INST_NAME="finn_${DOCKER_UNAME}"
+DOCKER_INST_NAME="finn_dev_${DOCKER_UNAME}"
# ensure Docker tag and inst. name are all lowercase
DOCKER_TAG=$(echo "$DOCKER_TAG" | tr '[:upper:]' '[:lower:]')
DOCKER_INST_NAME=$(echo "$DOCKER_INST_NAME" | tr '[:upper:]' '[:lower:]')
@@ -59,6 +59,7 @@ DOCKER_INST_NAME=$(echo "$DOCKER_INST_NAME" | tr '[:upper:]' '[:lower:]')
: ${PYNQ_PASSWORD="xilinx"}
: ${PYNQ_BOARD="Pynq-Z1"}
: ${PYNQ_TARGET_DIR="/home/xilinx/$DOCKER_INST_NAME"}
+: ${NUM_DEFAULT_WORKERS=1}
# Absolute path to this script, e.g. /home/user/bin/foo.sh
SCRIPT=$(readlink -f "$0")
@@ -69,7 +70,6 @@ BUILD_LOCAL=/tmp/$DOCKER_INST_NAME
VIVADO_HLS_LOCAL=$VIVADO_PATH
VIVADO_IP_CACHE=$BUILD_LOCAL/vivado_ip_cache
-
# ensure build dir exists locally
mkdir -p $BUILD_LOCAL
mkdir -p $VIVADO_IP_CACHE
@@ -87,14 +87,14 @@ if [ "$1" = "test" ]; then
DOCKER_CMD="python setup.py test"
elif [ "$1" = "notebook" ]; then
echo "Running Jupyter notebook server"
- DOCKER_CMD="source ~/.bashrc; jupyter notebook --ip=0.0.0.0 --port $JUPYTER_PORT notebooks"
+ DOCKER_CMD="jupyter notebook --ip=0.0.0.0 --port $JUPYTER_PORT notebooks"
else
echo "Running container only"
DOCKER_CMD="bash"
fi
# Build the FINN Docker image
-docker build --tag=$DOCKER_TAG \
+docker build -f docker/Dockerfile.finn_dev --tag=$DOCKER_TAG \
--build-arg GID=$DOCKER_GID \
--build-arg GNAME=$DOCKER_GNAME \
--build-arg UNAME=$DOCKER_UNAME \
@@ -120,6 +120,7 @@ docker run -t --rm --name $DOCKER_INST_NAME -it \
-e PYNQ_USERNAME=$PYNQ_USERNAME \
-e PYNQ_PASSWORD=$PYNQ_PASSWORD \
-e PYNQ_TARGET_DIR=$PYNQ_TARGET_DIR \
+-e NUM_DEFAULT_WORKERS=$NUM_DEFAULT_WORKERS \
-p $JUPYTER_PORT:$JUPYTER_PORT \
-p $NETRON_PORT:$NETRON_PORT \
-$DOCKER_TAG bash -c "$DOCKER_CMD"
+$DOCKER_TAG $DOCKER_CMD
diff --git a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
index 0334c316b80a5c0628d00b75eb40776436cb8434..78fc2ccfc92f9b7ca3ae6beafe7d24bdbfada2bc 100644
--- a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
+++ b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py
@@ -25,53 +25,53 @@
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+import warnings
import os
import xml.etree.ElementTree as ET
import finn.custom_op.registry as registry
-import finn.util.basic as util
+from finn.util.fpgadataflow import is_fpgadataflow_node
def hls_synth_res_estimation(model):
- """Extracts the results from the vivado synthesis.
+ """Extracts the FPGA resource results from the Vivado HLS synthesis estimates.
- Returns {node name : resource estimation}."""
+ Returns {node name : resources_dict}."""
res_dict = {}
for node in model.graph.node:
- if node.domain == "finn":
- backend_attribute = util.get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- op_type = node.op_type
- inst = registry.custom_op[op_type](node)
- code_gen_dir = inst.get_nodeattr("code_gen_dir_ipgen")
- if code_gen_dir == "":
- raise Exception(
- """Please run "CodeGen_ipgen" transformation and
- "HLSSynth_IPGen" first to generate the report files"""
- )
+ if is_fpgadataflow_node(node) is True:
+ # init values to zero
+ res_dict[node.name] = dict()
+ res_dict[node.name]["BRAM_18K"] = 0
+ res_dict[node.name]["FF"] = 0
+ res_dict[node.name]["LUT"] = 0
+ res_dict[node.name]["DSP48E"] = 0
+ res_dict[node.name]["URAM"] = 0
+ op_type = node.op_type
+ inst = registry.custom_op[op_type](node)
+ code_gen_dir = inst.get_nodeattr("code_gen_dir_ipgen")
+ if code_gen_dir == "":
+ warnings.warn(
+ """Could not find report files, values will be set to zero
+ for this node. Please run "CodeGen_ipgen" transformation and
+ "HLSSynth_IPGen" first to generate the report files"""
+ )
+ else:
+ xmlfile = "{}/project_{}/sol1/syn/report/{}_csynth.xml".format(
+ code_gen_dir, node.name, node.name
+ )
+
+ if os.path.isfile(xmlfile):
+ tree = ET.parse(xmlfile)
+ root = tree.getroot()
+ for item in root.findall("AreaEstimates/Resources"):
+ for child in item:
+ res_dict[node.name][child.tag] = child.text
else:
- xmlfile = "{}/project_{}/sol1/syn/report/{}_csynth.xml".format(
- code_gen_dir, node.name, node.name
+ warnings.warn(
+ """Could not find report files, values will be set to zero
+ for this node. Please run "CodeGen_ipgen" transformation and
+ "HLSSynth_IPGen" first to generate the report files"""
)
-
- if os.path.isfile(xmlfile):
- res_dict[node.name] = []
- tree = ET.parse(xmlfile)
- root = tree.getroot()
- for item in root.findall("AreaEstimates/Resources"):
- for child in item:
- res_dict[node.name].append(
- ["{} : {}".format(child.tag, child.text)]
- )
- else:
- raise Exception(
- """Please run "HLSSynth_IPGen" first
- to generate the report files"""
- )
-
return res_dict
diff --git a/src/finn/analysis/fpgadataflow/post_synth_res.py b/src/finn/analysis/fpgadataflow/post_synth_res.py
new file mode 100644
index 0000000000000000000000000000000000000000..508c34aaed50f2935f4915cdcea29a3e92641b3c
--- /dev/null
+++ b/src/finn/analysis/fpgadataflow/post_synth_res.py
@@ -0,0 +1,80 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import xml.etree.ElementTree as ET
+
+from finn.transformation.move_reshape import _is_fpgadataflow_node
+
+
+def post_synth_res(model):
+ """Extracts the FPGA resource results from the Vivado synthesis.
+
+ Returns {node name : resources_dict}."""
+
+ res_dict = {}
+ synth_report_filename = model.get_metadata_prop("vivado_synth_rpt")
+ if os.path.isfile(synth_report_filename):
+ tree = ET.parse(synth_report_filename)
+ root = tree.getroot()
+ all_cells = root.findall(".//tablecell")
+ # strip all whitespace from table cell contents
+ for cell in all_cells:
+ cell.attrib["contents"] = cell.attrib["contents"].strip()
+ else:
+ raise Exception("Please run synthesis first")
+
+ for node in model.graph.node:
+ if _is_fpgadataflow_node(node):
+ row = root.findall(".//*[@contents='%s']/.." % node.name)
+ if row != []:
+ node_dict = {}
+ row = row[0].getchildren()
+ """ Expected XML structure:
+<tablerow class="" suppressoutput="0" wordwrap="0">
+ <tableheader class="" contents="Instance" halign="3" width="-1"/>
+ <tableheader class="" contents="Module" halign="3" width="-1"/>
+ <tableheader class="" contents="Total LUTs" halign="3" width="-1"/>
+ <tableheader class="" contents="Logic LUTs" halign="3" width="-1"/>
+ <tableheader class="" contents="LUTRAMs" halign="3" width="-1"/>
+ <tableheader class="" contents="SRLs" halign="3" width="-1"/>
+ <tableheader class="" contents="FFs" halign="3" width="-1"/>
+ <tableheader class="" contents="RAMB36" halign="3" width="-1"/>
+ <tableheader class="" contents="RAMB18" halign="3" width="-1"/>
+ <tableheader class="" contents="DSP48 Blocks" halign="3" width="-1"/>
+</tablerow>
+ """
+ node_dict["LUT"] = int(row[2].attrib["contents"])
+ node_dict["SRL"] = int(row[5].attrib["contents"])
+ node_dict["FF"] = int(row[6].attrib["contents"])
+ node_dict["BRAM_36K"] = int(row[7].attrib["contents"])
+ node_dict["BRAM_18K"] = int(row[8].attrib["contents"])
+ node_dict["DSP48"] = int(row[9].attrib["contents"])
+ res_dict[node.name] = node_dict
+
+ return res_dict
diff --git a/src/finn/analysis/fpgadataflow/res_estimation.py b/src/finn/analysis/fpgadataflow/res_estimation.py
index 3585868906fb2c66aef045f49f0da919f933d012..c190059eceb0cc111477c84f843f4a9f9bf2f393 100644
--- a/src/finn/analysis/fpgadataflow/res_estimation.py
+++ b/src/finn/analysis/fpgadataflow/res_estimation.py
@@ -27,7 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import finn.custom_op.registry as registry
-import finn.util.basic as util
+from finn.util.fpgadataflow import is_fpgadataflow_node
def res_estimation(model):
@@ -37,14 +37,9 @@ def res_estimation(model):
res_dict = {}
for node in model.graph.node:
- if node.domain == "finn":
- backend_attribute = util.get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- op_type = node.op_type
- inst = registry.custom_op[op_type](node)
- res_dict[node.name] = inst.node_res_estimation()
+ if is_fpgadataflow_node(node) is True:
+ op_type = node.op_type
+ inst = registry.custom_op[op_type](node)
+ res_dict[node.name] = inst.node_res_estimation()
return res_dict
diff --git a/src/finn/core/modelwrapper.py b/src/finn/core/modelwrapper.py
index 6813aa06fc86c40fa8c77fee405fd5e66c812c48..e99a6ef4cd40d6323d77354d3c9b4be341d7649c 100644
--- a/src/finn/core/modelwrapper.py
+++ b/src/finn/core/modelwrapper.py
@@ -253,14 +253,30 @@ class ModelWrapper:
return None
def find_producer(self, tensor_name):
- """Finds and returns the node that produces the tensor with given name.
- Currently only works for linear graphs."""
- all_outputs = [x.output[0] for x in self._model_proto.graph.node]
- try:
- producer_ind = all_outputs.index(tensor_name)
- return self._model_proto.graph.node[producer_ind]
- except ValueError:
- return None
+ """Finds and returns the node that produces the tensor with given name."""
+ ret = None
+ for x in self._model_proto.graph.node:
+ if tensor_name in x.output:
+ ret = x
+ return ret
+
+ def find_upstream(self, tensor_name, finder_fxn):
+ """Follow the producer chain upstream, calling finder_fxn on each upstream
+ node until it returns True or there are no nodes left. Returns the list
+ of nodes visited, or None if finder_fxn did not return True."""
+ visit_list = []
+ current_tensor = tensor_name
+ while True:
+ current_producer = self.find_producer(current_tensor)
+ if current_producer is None:
+ return []
+ else:
+ found = finder_fxn(current_producer)
+ visit_list.append(current_producer)
+ if found:
+ return visit_list
+ else:
+ current_tensor = current_producer.input[0]
def find_consumer(self, tensor_name):
"""Finds and returns the node that consumes the tensor with given name.
@@ -355,3 +371,15 @@ class ModelWrapper:
self.model.metadata_props.append(metadata_prop)
else:
metadata_prop.value = value
+
+ def get_nodes_by_op_type(self, op_type):
+ """Returns a list of nodes with specified op_type."""
+ return list(filter(lambda x: x.op_type == op_type, self.graph.node))
+
+ def get_finn_nodes(self):
+ """Returns a list of nodes where domain == 'finn'."""
+ return list(filter(lambda x: x.domain == "finn", self.graph.node))
+
+ def get_non_finn_nodes(self):
+ """Returns a list of nodes where domain != 'finn'."""
+ return list(filter(lambda x: x.domain != "finn", self.graph.node))
diff --git a/src/finn/core/onnx_exec.py b/src/finn/core/onnx_exec.py
index 0f47a9104e3d2ef3ee06ef908e302344d78e0b17..172ba25b223fd087df134add460a42d0a9935e0e 100644
--- a/src/finn/core/onnx_exec.py
+++ b/src/finn/core/onnx_exec.py
@@ -61,6 +61,10 @@ def execute_node(node, context, graph):
# onnxruntime unfortunately does not implement run_node as defined by ONNX,
# it can only execute entire models -- so we create a model which solely
# consists of our current node.
+ # note: ensure that the same ValueInfo does not appear both in
+ # graph.value_info as well as graph.output or graph.input
+ # nodes with multiple outputs that are a mix of value_info and
+ # input/outputs may get them reordered below
node_inputs = list(filter(lambda x: x.name in node.input, graph.input))
node_inputs += list(
filter(lambda x: x.name in node.input, graph.value_info)
@@ -84,17 +88,25 @@ def execute_node(node, context, graph):
output_list = sess.run(None, input_dict)
for output_ind in range(len(node.output)):
+ # get the name of the target buffer from node.output
outp = node.output[output_ind]
- if output_list[output_ind].shape != context[outp].shape:
+
+ # retrieve the index of that name in node_outputs
+ for i in range(len(node_outputs)):
+ if outp == node_outputs[i].name:
+ list_ind = i
+
+ # use that index to index output_list
+ if output_list[list_ind].shape != context[outp].shape:
raise Exception(
"""Output shapes disagree after node execution:
found %s vs expected %s"""
% (
- str(output_list[output_ind].shape.shape),
+ str(output_list[list_ind].shape.shape),
str(context[outp].shape),
)
)
- context[outp] = output_list[output_ind]
+ context[outp] = output_list[list_ind]
def execute_onnx(model, input_dict, return_full_exec_context=False):
diff --git a/src/finn/core/remote_exec.py b/src/finn/core/remote_exec.py
index 190bb857ad6e5448d49a6b742adc888f2bca79d2..e97eb19a101e83f9d9603637e131b2ec9b7d16a4 100644
--- a/src/finn/core/remote_exec.py
+++ b/src/finn/core/remote_exec.py
@@ -38,17 +38,21 @@ def remote_exec(model, execution_context):
input values."""
# TODO fix for multi input-output
pynq_ip = model.get_metadata_prop("pynq_ip")
+ pynq_port = int(model.get_metadata_prop("pynq_port"))
pynq_username = model.get_metadata_prop("pynq_username")
pynq_password = model.get_metadata_prop("pynq_password")
pynq_target_dir = model.get_metadata_prop("pynq_target_dir")
deployment_dir = model.get_metadata_prop("pynq_deploy_dir")
inp = execution_context[model.graph.input[0].name]
+ # make copy of array before saving it
+ inp = inp.copy()
np.save(os.path.join(deployment_dir, "input.npy"), inp)
# extracting last folder of absolute path (deployment_dir)
deployment_folder = os.path.basename(os.path.normpath(deployment_dir))
# copy input to PYNQ board
- cmd = "sshpass -p {} scp -r {}/input.npy {}@{}:{}/{}".format(
+ cmd = "sshpass -p {} scp -P{} -r {}/input.npy {}@{}:{}/{}".format(
pynq_password,
+ pynq_port,
deployment_dir,
pynq_username,
pynq_ip,
@@ -58,17 +62,25 @@ def remote_exec(model, execution_context):
bash_command = ["/bin/bash", "-c", cmd]
process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
process_compile.communicate()
-
cmd = (
- "sshpass -p {} ssh {}@{} "
- '"cd {}/{}; echo "xilinx" | sudo -S python3.6 driver.py"'
- ).format(pynq_password, pynq_username, pynq_ip, pynq_target_dir, deployment_folder)
+ "sshpass -p {} ssh {}@{} -p {} "
+ '"cd {}/{}; echo "{}" | '
+ 'sudo -S python3.6 driver.py remote_pynq 1 resizer.bit input.npy output.npy"'
+ ).format(
+ pynq_password,
+ pynq_username,
+ pynq_ip,
+ pynq_port,
+ pynq_target_dir,
+ deployment_folder,
+ pynq_password,
+ )
bash_command = ["/bin/bash", "-c", cmd]
process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
process_compile.communicate()
-
- cmd = "sshpass -p {} scp {}@{}:{}/{}/output.npy {}".format(
+ cmd = "sshpass -p {} scp -P{} {}@{}:{}/{}/output.npy {}".format(
pynq_password,
+ pynq_port,
pynq_username,
pynq_ip,
pynq_target_dir,
diff --git a/src/finn/core/rtlsim_exec.py b/src/finn/core/rtlsim_exec.py
index 0841fedebcd473a488b2e62db4dc763f283789e1..af84a75e299d666c059df54211be42b691f5ccf2 100644
--- a/src/finn/core/rtlsim_exec.py
+++ b/src/finn/core/rtlsim_exec.py
@@ -35,11 +35,18 @@ from finn.util.fpgadataflow import (
pyverilate_stitched_ip,
)
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
+
def rtlsim_exec(model, execution_context):
"""Use PyVerilator to execute given model with stitched IP. The execution
context contains the input values."""
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
# ensure stitched ip project already exists
assert os.path.isfile(
model.get_metadata_prop("wrapper_filename")
@@ -74,7 +81,12 @@ def rtlsim_exec(model, execution_context):
packed_input = npy_to_rtlsim_input(i_tensor, i_dt, i_stream_w)
num_out_values = last_node.get_number_output_values()
# prepare pyverilator model
- sim = pyverilate_stitched_ip(model)
+ rtlsim_so = model.get_metadata_prop("rtlsim_so")
+ if (rtlsim_so is None) or (not os.path.isfile(rtlsim_so)):
+ sim = pyverilate_stitched_ip(model)
+ model.set_metadata_prop("rtlsim_so", sim.lib._name)
+ else:
+ sim = PyVerilator(rtlsim_so)
_reset_rtlsim(sim)
_toggle_clk(sim)
ret = _run_rtlsim(sim, packed_input, num_out_values, trace_file)
diff --git a/src/finn/core/throughput_test.py b/src/finn/core/throughput_test.py
new file mode 100644
index 0000000000000000000000000000000000000000..fc929237bf6c985997e49cc3f74c7d492d79839a
--- /dev/null
+++ b/src/finn/core/throughput_test.py
@@ -0,0 +1,81 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import subprocess
+
+
+def throughput_test(model):
+ """Runs the throughput test for the given model remotely on the pynq board.
+ The metadata properties related to the pynq board have to be set.
+ Returns a dictionary with results of the throughput test"""
+
+ pynq_ip = model.get_metadata_prop("pynq_ip")
+ pynq_port = int(model.get_metadata_prop("pynq_port"))
+ pynq_username = model.get_metadata_prop("pynq_username")
+ pynq_password = model.get_metadata_prop("pynq_password")
+ pynq_target_dir = model.get_metadata_prop("pynq_target_dir")
+ deployment_dir = model.get_metadata_prop("pynq_deploy_dir")
+ # extracting last folder of absolute path (deployment_dir)
+ deployment_folder = os.path.basename(os.path.normpath(deployment_dir))
+
+ cmd = (
+ "sshpass -p {} ssh {}@{} -p {} "
+ '"cd {}/{}; echo "{}" | '
+ "sudo -S python3.6 driver.py throughput_test 1000 "
+ 'resizer.bit input.npy output.npy"'
+ ).format(
+ pynq_password,
+ pynq_username,
+ pynq_ip,
+ pynq_port,
+ pynq_target_dir,
+ deployment_folder,
+ pynq_password,
+ )
+ bash_command = ["/bin/bash", "-c", cmd]
+ process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
+ process_compile.communicate()
+
+ cmd = "sshpass -p {} scp -P{} {}@{}:{}/{}/nw_metrics.txt {}".format(
+ pynq_password,
+ pynq_port,
+ pynq_username,
+ pynq_ip,
+ pynq_target_dir,
+ deployment_folder,
+ deployment_dir,
+ )
+ bash_command = ["/bin/bash", "-c", cmd]
+ process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
+ process_compile.communicate()
+
+ with open("{}/nw_metrics.txt".format(deployment_dir), "r") as file:
+ res = eval(file.read())
+
+ return res
diff --git a/src/finn/custom_op/__init__.py b/src/finn/custom_op/__init__.py
index 39de40f1e2024b1bb5dea0b20f39587151539da5..ab6e03bee65b8bf5c4041dd8021b1a561e7673d2 100644
--- a/src/finn/custom_op/__init__.py
+++ b/src/finn/custom_op/__init__.py
@@ -94,7 +94,7 @@ class CustomOp(ABC):
pass
@abstractmethod
- def make_shape_compatible_op(self):
+ def make_shape_compatible_op(self, model):
"""Returns a standard ONNX op which is compatible with this CustomOp
for performing shape inference."""
pass
diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py
index 7f13b43d57d9fe2f6de5e5ed9bb52214611f1098..8430a56bc2688627f82da6ae92140f5cff82cb60 100644
--- a/src/finn/custom_op/fpgadataflow/__init__.py
+++ b/src/finn/custom_op/fpgadataflow/__init__.py
@@ -31,13 +31,23 @@ import numpy as np
import os
import subprocess
from finn.custom_op import CustomOp
-from finn.util.basic import CppBuilder
+from finn.util.basic import (
+ CppBuilder,
+ make_build_dir,
+ roundup_to_integer_multiple,
+ get_rtlsim_trace_depth,
+)
from finn.util.fpgadataflow import (
IPGenBuilder,
pyverilate_get_liveness_threshold_cycles,
)
from . import templates
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
+
class HLSCustomOp(CustomOp):
"""HLSCustomOp class all custom ops that correspond to a finn-hlslib
@@ -68,18 +78,84 @@ class HLSCustomOp(CustomOp):
"code_gen_dir_ipgen": ("s", False, ""),
"executable_path": ("s", False, ""),
"ipgen_path": ("s", False, ""),
+ "ip_path": ("s", False, ""),
+ "ip_vlnv": ("s", False, ""),
"exec_mode": ("s", False, ""),
"sim_cycles": ("i", False, 0),
"rtlsim_trace": ("s", False, ""),
+ "res_estimate": ("s", False, ""),
+ "res_hls": ("s", False, ""),
+ "res_synth": ("s", False, ""),
+ "rtlsim_so": ("s", False, ""),
+ # input and output FIFO depths
+ "inFIFODepth": ("i", False, 2),
+ "outFIFODepth": ("i", False, 2),
}
+ def get_verilog_top_module_name(self):
+ "Return the Verilog top module name for this node."
+
+ node = self.onnx_node
+ prefixed_top_name = "%s_%s" % (node.name, node.name)
+ return prefixed_top_name
+
+ def get_verilog_top_filename(self):
+ "Return the Verilog top module filename for this node."
+
+ verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
+ self.get_nodeattr("code_gen_dir_ipgen"),
+ self.onnx_node.name,
+ self.get_verilog_top_module_name(),
+ )
+ return verilog_file
+
+ def prepare_rtlsim(self):
+ """Creates a Verilator emulation library for the RTL code generated
+ for this node, sets the rtlsim_so attribute to its path and returns
+ a PyVerilator wrapper around it."""
+
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
+ # ensure that code is generated
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ assert (
+ code_gen_dir != ""
+ ), """Node attribute "code_gen_dir_ipgen" is
+ not set. Please run HLSSynth_IPGen first."""
+ verilog_file = self.get_verilog_top_filename()
+ assert os.path.isfile(verilog_file), "Cannot find top-level Verilog file."
+ # build the Verilator emu library
+ sim = PyVerilator.build(
+ verilog_file,
+ build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"),
+ verilog_path=[
+ "{}/project_{}/sol1/impl/verilog/".format(
+ code_gen_dir, self.onnx_node.name
+ )
+ ],
+ trace_depth=get_rtlsim_trace_depth(),
+ )
+ # save generated lib filename in attribute
+ self.set_nodeattr("rtlsim_so", sim.lib._name)
+ return sim
+
+ def get_rtlsim(self):
+ """Return a PyVerilator wrapper for the Verilator emulation library
+ for this node."""
+
+ rtlsim_so = self.get_nodeattr("rtlsim_so")
+ assert os.path.isfile(rtlsim_so), "Cannot find rtlsim library."
+ # create PyVerilator wrapper
+ sim = PyVerilator(rtlsim_so)
+ return sim
+
def node_res_estimation(self):
"""Returns summarized resource estimation of BRAMs and LUTs
- of the node."""
- resources = []
- resources.append("BRAMs: " + str(self.bram_estimation()))
- resources.append("LUTs: " + str(self.lut_estimation()))
- return resources
+ of the node as a dictionary."""
+ ret = dict()
+ ret["BRAM_18K"] = self.bram_estimation()
+ ret["LUT"] = self.lut_estimation()
+ return ret
def bram_estimation(self):
"""Function for BRAM resource estimation, is member function of
@@ -97,6 +173,7 @@ class HLSCustomOp(CustomOp):
# generate top cpp file for ip generation
path = self.get_nodeattr("code_gen_dir_ipgen")
+ self.code_gen_dict["$AP_INT_MAX_W$"] = [str(self.get_ap_int_max_w())]
self.generate_params(model, path)
self.global_includes()
self.defines("ipgen")
@@ -123,6 +200,7 @@ class HLSCustomOp(CustomOp):
self.code_gen_dict["$FINNHLSLIBDIR$"] = ["/workspace/finn-hlslib"]
self.code_gen_dict["$TOPFXN$"] = [node.name]
self.code_gen_dict["$CLKPERIOD$"] = [str(clk)]
+ self.code_gen_dict["$EXTRA_DIRECTIVES$"] = self.ipgen_extra_directives()
template = self.ipgentcl_template
@@ -136,6 +214,10 @@ class HLSCustomOp(CustomOp):
f.close()
self.code_gen_dict.clear()
+ def ipgen_extra_directives(self):
+ "Return a list of extra tcl directives for HLS synthesis."
+ return []
+
def ipgen_singlenode_code(self):
"""Builds the bash script for ip generation using the IPGenBuilder from
finn.util.fpgadataflow."""
@@ -146,16 +228,21 @@ class HLSCustomOp(CustomOp):
builder.set_ipgen_path(code_gen_dir + "/project_{}".format(node.name))
builder.build(code_gen_dir)
self.set_nodeattr("ipgen_path", builder.ipgen_path)
+ self.set_nodeattr("ip_path", builder.ipgen_path + "/sol1/impl/ip")
+ vlnv = "xilinx.com:hls:%s:1.0" % node.name
+ self.set_nodeattr("ip_vlnv", vlnv)
def code_generation_npysim(self, model):
"""Generates c++ code for simulation (npysim)."""
node = self.onnx_node
path = self.get_nodeattr("code_gen_dir_npysim")
+ self.code_gen_dict["$AP_INT_MAX_W$"] = [str(self.get_ap_int_max_w())]
self.generate_params(model, path)
self.global_includes()
self.defines("npysim")
self.read_npy_data()
self.strm_decl()
+ self.pragmas()
self.docompute()
self.dataoutstrm()
self.save_as_npy()
@@ -184,6 +271,7 @@ class HLSCustomOp(CustomOp):
builder.append_includes("-I/workspace/finn-hlslib")
builder.append_includes("-I{}/include".format(os.environ["VIVADO_PATH"]))
builder.append_includes("--std=c++11")
+ builder.append_includes("-O3")
builder.append_sources(code_gen_dir + "/*.cpp")
builder.append_sources("/workspace/cnpy/cnpy.cpp")
builder.append_includes("-lz")
@@ -207,9 +295,10 @@ Found no codegen dir for this node, did you run the codegen_npysim transformatio
# assuming dynamic inputs start from 0
for in_ind in range(count):
current_input_name = node.input[in_ind]
+ # make copy before saving array
+ input_array = context[current_input_name].copy()
np.save(
- os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)),
- context[current_input_name],
+ os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), input_array
)
def npy_to_dynamic_output(self, context):
@@ -422,3 +511,21 @@ compilation transformations?
def get_outstream_width(self):
"""Returns output stream width, if implemented."""
raise Exception("get_outstream_width not implemented for this op")
+
+ def get_instream_width_padded(self):
+ """Returns input stream width padded to a multiple of 8. This is required
+ by the AXI Stream spec."""
+ in_width = self.get_instream_width()
+ return roundup_to_integer_multiple(in_width, 8)
+
+ def get_outstream_width_padded(self):
+ """Returns output stream width padded to a multiple of 8. This is required
+ by the AXI Stream spec."""
+ out_width = self.get_outstream_width()
+ return roundup_to_integer_multiple(out_width, 8)
+
+ def get_ap_int_max_w(self):
+ "Return the maximum width of any ap_int used in this module."
+ instream = self.get_instream_width()
+ outstream = self.get_outstream_width()
+ return max([instream, outstream])
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
index 14016ce9ce22c729ad3279fb90dc900f88fda8ba..2b469f7b0d6e5ddc3068fa3fd2d6cb487a560d92 100644
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
@@ -29,10 +29,17 @@
import os
import numpy as np
-from pyverilator import PyVerilator
from finn.core.datatype import DataType
from finn.custom_op.fpgadataflow import HLSCustomOp
+from finn.custom_op.im2col import compute_conv_output_dim
+from onnx import TensorProto, helper
+from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
+
+# ONNX i/o tensor shape assumptions for ConvolutionInputGenerator:
+# input 0 is the input tensor, shape NHWC = (1, IFMDim, IFMDim, IFMChannels)
+# output 0 is the output tensor, shape NHWC:
+# = (1, OFMDim, OFMDim, (ConvKernelDim^2)*IFMChannels)
class ConvolutionInputGenerator(HLSCustomOp):
@@ -46,7 +53,6 @@ class ConvolutionInputGenerator(HLSCustomOp):
my_attrs = {
"ConvKernelDim": ("i", True, 0),
"IFMChannels": ("i", True, 0),
- "Input_precision": ("i", True, 0),
"IFMDim": ("i", True, 0),
"OFMDim": ("i", True, 0),
"SIMD": ("i", True, 0),
@@ -54,23 +60,83 @@ class ConvolutionInputGenerator(HLSCustomOp):
# FINN DataTypes for inputs, weights, outputs
"inputDataType": ("s", True, ""),
"outputDataType": ("s", True, ""),
+ # FPGA resource type for ConvolutionInputGenerator input buffer
+ # auto -- let Vivado HLS decide
+ # block -- use BRAM
+ # distributed -- use LUTRAM
+ # ultra -- use URAM
+ "ram_style": ("s", False, "distributed"),
}
my_attrs.update(super().get_nodeattr_types())
return my_attrs
- def make_shape_compatible_op(self):
- pass
+ def get_normal_input_shape(self):
- def infer_node_datatype(self, model):
- pass
+ ifm_dim = self.get_nodeattr("IFMDim")
+ ifm_ch = self.get_nodeattr("IFMChannels")
- def verify_node(self):
- pass
+ ishape = (1, ifm_dim, ifm_dim, ifm_ch)
+ return ishape
- def bram_estimation(self):
- pass
+ def get_folded_input_shape(self):
+ ifm_dim = self.get_nodeattr("IFMDim")
+ ifm_ch = self.get_nodeattr("IFMChannels")
+ simd = self.get_nodeattr("SIMD")
+ assert ifm_ch % simd == 0, "SIMD must divide IFMChannels"
+ wf = int(ifm_ch / simd)
+ folded_ishape = (1, ifm_dim, ifm_dim, wf, simd)
+ return folded_ishape
+
+ def get_normal_output_shape(self):
+ k = self.get_nodeattr("ConvKernelDim")
+ ifm_dim = self.get_nodeattr("IFMDim")
+ ifm_ch = self.get_nodeattr("IFMChannels")
+ stride = self.get_nodeattr("Stride")
+ pad = 0
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad)
+ oshape = (1, ofm_dim, ofm_dim, k * k * ifm_ch)
+ return oshape
- def lut_estimation(self):
+ def get_folded_output_shape(self):
+ k = self.get_nodeattr("ConvKernelDim")
+ ifm_dim = self.get_nodeattr("IFMDim")
+ ifm_ch = self.get_nodeattr("IFMChannels")
+ stride = self.get_nodeattr("Stride")
+ simd = self.get_nodeattr("SIMD")
+ pad = 0
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad)
+ assert ifm_ch % simd == 0, "SIMD must divide IFMChannels"
+ assert k % stride == 0, "stride must divide kernel size k"
+ wf = int((k * k * ifm_ch) // simd)
+ folded_oshape = (1, ofm_dim, ofm_dim, wf, simd)
+ return folded_oshape
+
+ def make_shape_compatible_op(self, model):
+ exp_ishape = self.get_normal_input_shape()
+ oshape = self.get_normal_output_shape()
+ ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0]))
+ assert ishape == exp_ishape, "Unexpect input shape for ConvInpGen."
+ # implement tensor with correct shape
+ values = np.random.randn(*oshape).astype(np.float32)
+ return helper.make_node(
+ "Constant",
+ inputs=[],
+ outputs=[self.onnx_node.output[0]],
+ value=helper.make_tensor(
+ name="const_tensor",
+ data_type=TensorProto.FLOAT,
+ dims=values.shape,
+ vals=values.flatten().astype(float),
+ ),
+ )
+
+ def infer_node_datatype(self, model):
+ node = self.onnx_node
+ # data type stays the same
+ dtype = model.get_tensor_datatype(node.input[0])
+ model.set_tensor_datatype(node.output[0], dtype)
+
+ def verify_node(self):
pass
def get_input_datatype(self):
@@ -81,122 +147,97 @@ class ConvolutionInputGenerator(HLSCustomOp):
"""Returns FINN DataType of output."""
return DataType[self.get_nodeattr("outputDataType")]
- def get_stream_width(self):
+ def get_instream_width(self):
"""Returns stream width, input and output stream width are equal for
the sliding window function"""
- return self.get_nodeattr("SIMD") * self.get_nodeattr("Input_precision")
-
- def get_number_output_values(self):
- k = self.get_nodeattr("ConvKernelDim")
+ ibits = self.get_input_datatype().bitwidth()
+ simd = self.get_nodeattr("SIMD")
ifm_ch = self.get_nodeattr("IFMChannels")
- ofm_dim = self.get_nodeattr("OFMDim")
- out_pix = ofm_dim * ofm_dim
+ assert ifm_ch % simd == 0, "SIMD must divide IFMChannels"
+ in_width = simd * ibits
+ return in_width
+
+ def get_outstream_width(self):
+ """Returns stream width, input and output stream width are equal for
+ the sliding window function, so the function to determine the input
+ stream width can be reused."""
+ return self.get_instream_width()
- return out_pix * k * k * ifm_ch
+ def get_number_output_values(self):
+ folded_oshape = self.get_folded_output_shape()
+ num_output_elems = np.prod(folded_oshape[:-1])
+ return num_output_elems
def execute_node(self, context, graph):
mode = self.get_nodeattr("exec_mode")
node = self.onnx_node
- k = self.get_nodeattr("ConvKernelDim")
- ifm_dim = self.get_nodeattr("IFMDim")
- ifm_ch = self.get_nodeattr("IFMChannels")
- ofm_dim = self.get_nodeattr("OFMDim")
- out_pix = ofm_dim * ofm_dim
+ exp_ishape = self.get_normal_input_shape()
+ exp_oshape = self.get_normal_output_shape()
+ folded_ishape = self.get_folded_input_shape()
+ folded_oshape = self.get_folded_output_shape()
+ # TODO ensure codegen dir exists
if mode == "npysim":
- idt = self.get_input_datatype()
- if idt == DataType.BIPOLAR:
- # use binary for bipolar storage
- idt = DataType.BINARY
-
- # TODO ensure codegen dir exists
code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
- # create a npy file for input of the node
-
- inp = context[node.input[0]]
- assert str(inp.dtype) == "float32", "Input datatype is not float32"
- assert inp.shape == (
- 1,
- ifm_ch,
- ifm_dim,
- ifm_dim,
- ), """Input shape doesn't
- match expected shape (1, ifm_ch, ifm_dim, ifm_dim)."""
- reshaped_inp = inp.transpose(0, 2, 3, 1)
- np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_inp)
+ elif mode == "rtlsim":
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ else:
+ raise Exception(
+ """Invalid value for attribute exec_mode! Is currently set to: {}
+ has to be set to one of the following value ("npysim", "rtlsim")""".format(
+ mode
+ )
+ )
+
+ inp = context[node.input[0]]
+ assert str(inp.dtype) == "float32", "Input datatype is not float32"
+ assert (
+ inp.shape == exp_ishape
+ ), """Input shape doesn't
+ match expected shape (1, ifm_dim, ifm_dim, ifm_ch)."""
+ if self.get_input_datatype() == DataType.BIPOLAR:
+ # store bipolar activations as binary
+ inp = (inp + 1) / 2
+ export_idt = DataType.BINARY
+ else:
+ export_idt = self.get_input_datatype()
+ # reshape input into folded form
+ inp = inp.reshape(folded_ishape)
+ # make copy before saving array
+ reshaped_input = inp.copy()
+ np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input)
+
+ if mode == "npysim":
# execute the precompiled model
super().exec_precompiled_singlenode_model()
# load output npy file
super().npy_to_dynamic_output(context)
- if self.get_output_datatype() == DataType.BIPOLAR:
- out = context[node.output[0]]
- out = 2 * out - 1
- context[node.output[0]] = out
- assert context[node.output[0]].shape == (
- 1,
- out_pix,
- k * k,
- ifm_ch,
- ), """Output
- shape doesn't match expected shape (1, out_pix, k*k, ifm_ch)."""
- # reshape output to have expected shape
- context[node.output[0]] = context[node.output[0]].reshape(
- 1, out_pix, k * k * ifm_ch
- )
+ assert (
+ context[node.output[0]].shape == folded_oshape
+ ), "npysim \
+ did not produce expected ofolded utput shape"
+ context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
elif mode == "rtlsim":
- code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
- prefixed_top_name = "%s_%s" % (node.name, node.name)
- # check if needed file exists
- verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
- code_gen_dir, node.name, prefixed_top_name
+ sim = self.get_rtlsim()
+ nbits = self.get_instream_width()
+ rtlsim_inp = npy_to_rtlsim_input(
+ "{}/input_0.npy".format(code_gen_dir), export_idt, nbits
)
- if os.path.isfile(verilog_file):
- inp = context[node.input[0]]
- inp = inp.transpose(0, 2, 3, 1)
- inp = inp.flatten()
-
- # TODO: check how to sort inputs for multichannel inputs
- # a = []
- # for i in range(len(inp)):
- # if (i+1) % 2 == 0:
- # a.append((int(inp[i-1]) << 1) + int(inp[i]))
- # inp = a
- sim = PyVerilator.build(
- verilog_file,
- verilog_path=[
- "{}/project_{}/sol1/impl/verilog/".format(
- code_gen_dir, node.name
- )
- ],
- )
- super().reset_rtlsim(sim)
- super().toggle_clk(sim)
- output = self.rtlsim(sim, inp)
- output = [int(x) for x in output]
- odt = self.get_output_datatype()
- if odt == DataType.BIPOLAR:
- output = [2 * x - 1 for x in output]
-
- # pyverilator interprets int2 as uint2, so output has to be corrected
- elif odt == DataType.INT2:
- mask = 2 ** (odt.bitwidth() - 1)
- output = [-(x & mask) + (x & ~mask) for x in output]
- # TODO: check how to sort inputs for multichannel inputs
- # output = [bin(x)[2:].zfill(ifm_ch) for x in output]
- # output_ch1 = [int(x[:1]) for x in output]
- # output_ch2 = [int(x[1:]) for x in output]
-
- # reshape output
- output = np.asarray([output], dtype=np.float32).reshape(
- 1, out_pix, k * k * ifm_ch
- )
- context[node.output[0]] = output
-
- else:
- raise Exception(
- """Found no verilog files for this node,
- did you run the codegen_ipgen transformation?"""
- )
+ super().reset_rtlsim(sim)
+ super().toggle_clk(sim)
+ rtlsim_output = self.rtlsim(sim, rtlsim_inp)
+ odt = export_idt
+ target_bits = odt.bitwidth()
+ packed_bits = self.get_outstream_width()
+ out_npy_path = "{}/output.npy".format(code_gen_dir)
+ out_shape = self.get_folded_output_shape()
+ rtlsim_output_to_npy(
+ rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits
+ )
+ # load and reshape output
+ output = np.load(out_npy_path)
+ output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape)
+ context[node.output[0]] = output
else:
raise Exception(
"""Invalid value for attribute exec_mode! Is currently set to: {}
@@ -204,6 +245,15 @@ class ConvolutionInputGenerator(HLSCustomOp):
mode
)
)
+ # binary -> bipolar if needed
+ if self.get_output_datatype() == DataType.BIPOLAR:
+ out = context[node.output[0]]
+ out = 2 * out - 1
+ context[node.output[0]] = out
+ assert (
+ context[node.output[0]].shape == exp_oshape
+ ), """Output
+ shape doesn't match expected shape (1, ofm_dim, ofm_dim, k*k*ifm_ch)."""
def global_includes(self):
self.code_gen_dict["$GLOBALS$"] = ['#include "slidingwindow.h"']
@@ -211,12 +261,13 @@ class ConvolutionInputGenerator(HLSCustomOp):
def defines(self, var):
numReps = 1
self.code_gen_dict["$DEFINES$"] = [
- """#define ConvKernelDim1 {}\n #define IFMChannels1 {}
- #define Input_precision1 {}\n #define IFMDim1 {}\n #define OFMDim1 {}
- #define SIMD1 {}\n #define Stride1 {}\n #define numReps {}""".format(
+ """#define ConvKernelDim1 {}\n #define IFMChannels1 {}\n
+ #define Input_precision1 {}\n #define IFMDim1 {}\n
+ #define OFMDim1 {}\n #define SIMD1 {}\n
+ #define Stride1 {}\n #define numReps {}""".format(
self.get_nodeattr("ConvKernelDim"),
self.get_nodeattr("IFMChannels"),
- self.get_nodeattr("Input_precision"),
+ self.get_input_datatype().bitwidth(),
self.get_nodeattr("IFMDim"),
self.get_nodeattr("OFMDim"),
self.get_nodeattr("SIMD"),
@@ -232,7 +283,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
- packed_bits = self.get_stream_width()
+ packed_bits = self.get_instream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
@@ -246,10 +297,10 @@ class ConvolutionInputGenerator(HLSCustomOp):
def strm_decl(self):
self.code_gen_dict["$STREAMDECLARATIONS$"] = []
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
- 'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_stream_width())
+ 'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_instream_width())
)
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
- 'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_stream_width())
+ 'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_outstream_width())
)
def docompute(self):
@@ -268,17 +319,13 @@ class ConvolutionInputGenerator(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
- packed_bits = self.get_stream_width()
+ packed_bits = self.get_outstream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
npy_out = "%s/output.npy" % code_gen_dir
- ofm_dim = self.get_nodeattr("OFMDim")
- out_pix = ofm_dim * ofm_dim
- k = self.get_nodeattr("ConvKernelDim")
- ifm_ch = self.get_nodeattr("IFMChannels")
- shape = (1, out_pix, k * k, ifm_ch)
- shape_cpp_str = str(shape).replace("(", "{").replace(")", "}")
+ oshape = self.get_folded_output_shape()
+ oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}")
self.code_gen_dict["$DATAOUTSTREAM$"] = [
'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");'
@@ -287,7 +334,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
elem_hls_type,
elem_bits,
npy_type,
- shape_cpp_str,
+ oshape_cpp_str,
npy_out,
)
]
@@ -309,3 +356,17 @@ class ConvolutionInputGenerator(HLSCustomOp):
self.code_gen_dict["$PRAGMAS$"].append(
"#pragma HLS INTERFACE ap_ctrl_none port=return"
)
+
+ def ipgen_extra_directives(self):
+ # add directive to control input buffer memory resources
+ ram_style = self.get_nodeattr("ram_style")
+ map_to_hls_ram_style = {
+ "auto": "RAM_2P",
+ "block": "RAM_2P_BRAM",
+ "distributed": "RAM_2P_LUTRAM",
+ "ultra": "RAM_2P_URAM",
+ }
+ hls_ram_style = map_to_hls_ram_style[ram_style]
+ directive = "set_directive_resource -core %s " % hls_ram_style
+ directive += "ConvolutionInputGenerator inputBuf"
+ return [directive]
diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
new file mode 100644
index 0000000000000000000000000000000000000000..f30871909b1c70f3b5df148f1b6eae22fdbadc25
--- /dev/null
+++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
@@ -0,0 +1,387 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import numpy as np
+
+from finn.custom_op.fpgadataflow import HLSCustomOp
+from finn.core.datatype import DataType
+from onnx import TensorProto, helper
+from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
+
+# does not do anything at the ONNX node-by-node level, and input-output
+# tensor shapes are the same. performs data width conversion at the rtlsim level
+
+
+class StreamingDataWidthConverter_Batch(HLSCustomOp):
+ """Class that corresponds to finn-hlslib StreamingDataWidthConverter_Batch
+ function."""
+
+ def get_nodeattr_types(self):
+ my_attrs = {
+ # shape of input/output tensors
+ "shape": ("ints", True, []),
+ # bit width of input and output streams
+ "inWidth": ("i", True, 0),
+ "outWidth": ("i", True, 0),
+ # FINN DataTypes for inputs/outputs
+ "dataType": ("s", True, ""),
+ }
+ my_attrs.update(super().get_nodeattr_types())
+ return my_attrs
+
+ def get_input_datatype(self):
+ """Returns FINN DataType of input."""
+ return DataType[self.get_nodeattr("dataType")]
+
+ def get_output_datatype(self):
+ """Returns FINN DataType of output."""
+ return DataType[self.get_nodeattr("dataType")]
+
+ def get_normal_input_shape(self):
+ ishape = self.get_nodeattr("shape")
+ return ishape
+
+ def get_normal_output_shape(self):
+ oshape = self.get_nodeattr("shape")
+ return oshape
+
+ def get_folded_input_shape(self):
+ # for correct functionality of the dwc node the
+ # following must apply:
+ # if inWidth > outWidth: inWidth % outWidth = 0
+ # if inWidth < outWidth: outWidth % inWidth = 0
+ iwidth = self.get_nodeattr("inWidth")
+ owidth = self.get_nodeattr("outWidth")
+ if iwidth > owidth:
+ assert (
+ iwidth % owidth == 0
+ ), """InWidth is bigger than OutWidth and is not divisible by it.
+ Please adjust PE and SIMD values so that InWidth % OutWidth = 0"""
+ else:
+ assert (
+ owidth % iwidth == 0
+ ), """OutWidth is bigger than InWidth and is not divisible by it.
+ Please adjust PE and SIMD values so that OutWidth % InWidth = 0"""
+
+ ishape = self.get_normal_input_shape()
+ dummy_t = np.random.randn(*ishape)
+ ibits = self.get_input_datatype().bitwidth()
+ assert (
+ iwidth % ibits == 0
+ ), """DWC input width must be divisible by
+ input element bitwidth"""
+ ielems = int(iwidth // ibits)
+ ichannels = ishape[-1]
+ new_shape = []
+ for i in ishape[:-1]:
+ new_shape.append(i)
+ new_shape.append(int(ichannels // ielems))
+ new_shape.append(ielems)
+ dummy_t = dummy_t.reshape(new_shape)
+ return dummy_t.shape
+
+ def get_folded_output_shape(self):
+ # for correct functionality of the dwc node the
+ # following must apply:
+ # if inWidth > outWidth: inWidth % outWidth = 0
+ # if inWidth < outWidth: outWidth % inWidth = 0
+ iwidth = self.get_nodeattr("inWidth")
+ owidth = self.get_nodeattr("outWidth")
+ if iwidth > owidth:
+ assert (
+ iwidth % owidth == 0
+ ), """InWidth is bigger than OutWidth and is not divisible by it.
+ Please adjust PE and SIMD values so that InWidth % OutWidth = 0"""
+ else:
+ assert (
+ owidth % iwidth == 0
+ ), """OutWidth is bigger than InWidth and is not divisible by it.
+ Please adjust PE and SIMD values so that OutWidth % InWidth = 0"""
+
+ oshape = self.get_normal_output_shape()
+ dummy_t = np.random.randn(*oshape)
+ obits = self.get_output_datatype().bitwidth()
+ assert (
+ owidth % obits == 0
+ ), """DWC output width must be divisible by
+ input element bitwidth"""
+ oelems = int(owidth // obits)
+ ochannels = oshape[-1]
+ new_shape = []
+ for i in oshape[:-1]:
+ new_shape.append(i)
+ new_shape.append(int(ochannels // oelems))
+ new_shape.append(oelems)
+ dummy_t = dummy_t.reshape(new_shape)
+
+ return dummy_t.shape
+
+ def get_number_output_values(self):
+ folded_oshape = self.get_folded_output_shape()
+ return np.prod(folded_oshape[:-1])
+
+ def get_number_input_values(self):
+ folded_ishape = self.get_folded_input_shape()
+ return np.prod(folded_ishape[:-1])
+
+ def get_instream_width(self):
+ in_width = self.get_nodeattr("inWidth")
+ return in_width
+
+ def get_outstream_width(self):
+ out_width = self.get_nodeattr("outWidth")
+ return out_width
+
+ def make_shape_compatible_op(self, model):
+ exp_ishape = self.get_normal_input_shape()
+ oshape = self.get_normal_output_shape()
+ ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0]))
+ assert ishape == tuple(exp_ishape), "Unexpect input shape for StreamingDWC."
+ # implement tensor with correct shape
+ values = np.random.randn(*oshape).astype(np.float32)
+ return helper.make_node(
+ "Constant",
+ inputs=[],
+ outputs=[self.onnx_node.output[0]],
+ value=helper.make_tensor(
+ name="const_tensor",
+ data_type=TensorProto.FLOAT,
+ dims=values.shape,
+ vals=values.flatten().astype(float),
+ ),
+ )
+
+ def infer_node_datatype(self, model):
+ node = self.onnx_node
+ # data type stays the same
+ dtype = model.get_tensor_datatype(node.input[0])
+ model.set_tensor_datatype(node.output[0], dtype)
+
+ def verify_node(self):
+ info_messages = []
+
+ # verify that "domain" is set to "finn"
+ domain_value = self.onnx_node.domain
+ if domain_value == "finn":
+ info_messages.append("Attribute domain is set correctly")
+ else:
+ info_messages.append('Attribute domain should be set to "finn"')
+
+ # verify that "backend" is set to "fpgadataflow"
+ backend_value = self.get_nodeattr("backend")
+ if backend_value == "fpgadataflow":
+ info_messages.append("Attribute backend is set correctly")
+ else:
+ info_messages.append('Attribute backend should be set to "fpgadataflow"')
+
+ # verify the number of inputs
+ if len(self.onnx_node.input) == 1:
+ info_messages.append("The number of inputs is correct")
+ else:
+ info_messages.append("""StreamingDWC needs 1 data input""")
+
+ return info_messages
+
+ def global_includes(self):
+ self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"']
+
+ def defines(self, var):
+ numReps = 1
+ numInWords = 1
+ inWidth = self.get_nodeattr("inWidth")
+ outWidth = self.get_nodeattr("outWidth")
+ if outWidth > inWidth:
+ numInWords = int(outWidth // inWidth)
+ self.code_gen_dict["$DEFINES$"] = [
+ "#define InWidth %d " % inWidth,
+ "#define OutWidth %d " % outWidth,
+ "#define NumInWords %d " % numInWords,
+ "#define numReps %d" % numReps,
+ ]
+
+ def read_npy_data(self):
+ code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
+ dtype = self.get_input_datatype()
+ if dtype == DataType.BIPOLAR:
+ # use binary for bipolar storage
+ dtype = DataType.BINARY
+ elem_bits = dtype.bitwidth()
+ packed_bits = self.get_instream_width()
+ packed_hls_type = "ap_uint<%d>" % packed_bits
+ elem_hls_type = dtype.get_hls_datatype_str()
+ npy_type = "float"
+ npy_in = "%s/input_0.npy" % code_gen_dir
+ self.code_gen_dict["$READNPYDATA$"] = []
+ self.code_gen_dict["$READNPYDATA$"].append(
+ 'npy2apintstream<%s, %s, %d, %s>("%s", in0);'
+ % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)
+ )
+
+ def strm_decl(self):
+ self.code_gen_dict["$STREAMDECLARATIONS$"] = []
+ self.code_gen_dict["$STREAMDECLARATIONS$"].append(
+ 'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_instream_width())
+ )
+ self.code_gen_dict["$STREAMDECLARATIONS$"].append(
+ 'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_outstream_width())
+ )
+
+ def docompute(self):
+ # TODO continue with fxns below, they are copy-pasted
+ op = "StreamingDataWidthConverter_Batch"
+ self.code_gen_dict["$DOCOMPUTE$"] = [
+ "%s<InWidth, OutWidth, NumInWords>(in0, out, numReps);" % (op)
+ ]
+
+ def dataoutstrm(self):
+ code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
+ dtype = self.get_output_datatype()
+ if dtype == DataType.BIPOLAR:
+ # use binary for bipolar storage
+ dtype = DataType.BINARY
+ elem_bits = dtype.bitwidth()
+ packed_bits = self.get_outstream_width()
+ packed_hls_type = "ap_uint<%d>" % packed_bits
+ elem_hls_type = dtype.get_hls_datatype_str()
+ npy_type = "float"
+ npy_out = "%s/output.npy" % code_gen_dir
+ oshape = self.get_folded_output_shape()
+ oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}")
+
+ self.code_gen_dict["$DATAOUTSTREAM$"] = [
+ 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");'
+ % (
+ packed_hls_type,
+ elem_hls_type,
+ elem_bits,
+ npy_type,
+ oshape_cpp_str,
+ npy_out,
+ )
+ ]
+
+ def save_as_npy(self):
+ self.code_gen_dict["$SAVEASCNPY$"] = []
+
+ def blackboxfunction(self):
+ in_packed_bits = self.get_instream_width()
+ in_packed_hls_type = "ap_uint<%d>" % in_packed_bits
+ out_packed_bits = self.get_outstream_width()
+ out_packed_hls_type = "ap_uint<%d>" % out_packed_bits
+ self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
+ "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)"
+ % (self.onnx_node.name, in_packed_hls_type, out_packed_hls_type)
+ ]
+
+ def pragmas(self):
+ self.code_gen_dict["$PRAGMAS$"] = ["#pragma HLS INTERFACE axis port=in0"]
+ self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE axis port=out")
+ self.code_gen_dict["$PRAGMAS$"].append(
+ "#pragma HLS INTERFACE ap_ctrl_none port=return"
+ )
+
+ def execute_node(self, context, graph):
+ mode = self.get_nodeattr("exec_mode")
+ node = self.onnx_node
+ exp_shape = self.get_normal_input_shape()
+ folded_ishape = self.get_folded_input_shape()
+
+ # TODO ensure codegen dir exists
+ if mode == "npysim":
+ code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
+ elif mode == "rtlsim":
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ else:
+ raise Exception(
+ """Invalid value for attribute exec_mode! Is currently set to: {}
+ has to be set to one of the following value ("npysim", "rtlsim")""".format(
+ mode
+ )
+ )
+
+ inp = context[node.input[0]]
+ assert str(inp.dtype) == "float32", "Input datatype is not float32"
+ assert inp.shape == tuple(
+ exp_shape
+ ), "Input shape does not match expected shape."
+
+ if self.get_input_datatype() == DataType.BIPOLAR:
+ # store bipolar activations as binary
+ inp = (inp + 1) / 2
+ export_idt = DataType.BINARY
+ else:
+ export_idt = self.get_input_datatype()
+ # reshape input into folded shape
+ reshaped_input = inp.reshape(folded_ishape)
+ # make copy before saving array
+ reshaped_input = reshaped_input.copy()
+ np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input)
+
+ if mode == "npysim":
+ output = inp
+ output = np.asarray([output], dtype=np.float32).reshape(*exp_shape)
+ context[node.output[0]] = output
+
+ elif mode == "rtlsim":
+ sim = self.get_rtlsim()
+ nbits = self.get_instream_width()
+ rtlsim_inp = npy_to_rtlsim_input(
+ "{}/input_0.npy".format(code_gen_dir), export_idt, nbits
+ )
+ super().reset_rtlsim(sim)
+ super().toggle_clk(sim)
+ rtlsim_output = self.rtlsim(sim, rtlsim_inp)
+ odt = export_idt
+ target_bits = odt.bitwidth()
+ packed_bits = self.get_outstream_width()
+ out_npy_path = "{}/output.npy".format(code_gen_dir)
+ out_shape = self.get_folded_output_shape()
+ rtlsim_output_to_npy(
+ rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits
+ )
+ # load and reshape output
+ output = np.load(out_npy_path)
+ output = np.asarray([output], dtype=np.float32).reshape(exp_shape)
+ context[node.output[0]] = output
+ else:
+ raise Exception(
+ """Invalid value for attribute exec_mode! Is currently set to: {}
+ has to be set to "rtlsim" """.format(
+ mode
+ )
+ )
+ # binary -> bipolar if needed
+ if self.get_output_datatype() == DataType.BIPOLAR:
+ out = context[node.output[0]]
+ out = 2 * out - 1
+ context[node.output[0]] = out
+ assert context[node.output[0]].shape == tuple(
+ exp_shape
+ ), """Output
+ shape doesn't match expected shape, should be same as input shape"""
diff --git a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
index a2c88c5d6eca723f4e853e09a685bc6478e9a01c..46920711e13057178be9fca5fe3a18ce3e14feda 100644
--- a/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py
@@ -28,24 +28,32 @@
import math
import os
+import subprocess
+from shutil import copy
import numpy as np
-from pyverilator import PyVerilator
+from onnx import TensorProto, helper
from finn.core.datatype import DataType
from finn.custom_op.fpgadataflow import HLSCustomOp
-from finn.util.basic import interleave_matrix_outer_dim_from_partitions
+from finn.util.basic import (
+ interleave_matrix_outer_dim_from_partitions,
+ roundup_to_integer_multiple,
+)
from finn.util.data_packing import (
npy_to_rtlsim_input,
numpy_to_hls_code,
rtlsim_output_to_npy,
+ pack_innermost_dim_as_hex_string,
)
+from . import templates
# ONNX i/o tensor shape assumptions for StreamingFCLayer:
-# input 0 is the input vector, shape (1, i_size) = (1, MW)
-# input 1 is the weight vector, shape (i_size, o_size) = (MW, MH)
-# (optional) input 2 is the threshold vector, shape (o_size, n_thres)
-# output 0 is the output vector, shape (1, o_size) = (1, MH)
+# input 0 is the input tensor, shape (.., i_size) = (..., MW)
+# input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH)
+# (optional) input 2 is the thresholds tensor, shape (o_size, n_thres)
+# output 0 is the output tensor, shape (.., o_size) = (..., MH)
+# the ... here can be any shape (representing groups of vectors)
class StreamingFCLayer_Batch(HLSCustomOp):
@@ -53,6 +61,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
def __init__(self, onnx_node):
super().__init__(onnx_node)
+ self.decoupled_wrapper = templates.decoupled_wrapper
def get_nodeattr_types(self):
my_attrs = {
@@ -71,13 +80,42 @@ class StreamingFCLayer_Batch(HLSCustomOp):
"binaryXnorMode": ("i", False, 0),
# no-activation mode (produce accumulators)
"noActivation": ("i", False, 0),
- # input and output FIFO depths
- "inFIFODepth": ("i", False, 0),
- "outFIFODepth": ("i", False, 0),
+ # number of input vectors, examples:
+ # [1] is a single vector (like a FC layer with batch=1)
+ # [4] is four vectors (like a FC layer with batch=4)
+ # [1, 4, 4] is four * four vectors (like a conv layer with batch=1)
+ "numInputVectors": ("ints", False, [1]),
+ # memory mode for the FC weights
+ # const -- embedded weights, default, long compile/synth times
+ # decoupled -- streaming weights
+ "mem_mode": ("s", False, "const"),
+ # FPGA resource type for memories in decoupled mode
+ # auto -- let Vivado decide
+ # block -- use BRAM
+ # distributed -- use LUTRAM
+ # see also https://www.xilinx.com/support/answers/38070.html
+ "ram_style": ("s", False, "auto"),
}
my_attrs.update(super().get_nodeattr_types())
return my_attrs
+ def get_verilog_top_module_name(self):
+ "Return the Verilog top module name for this node."
+
+ node = self.onnx_node
+ # set top name depending on mem_mode
+ mem_mode = self.get_nodeattr("mem_mode")
+ if mem_mode == "const":
+ prefixed_top_name = "%s_%s" % (node.name, node.name)
+ elif mem_mode == "decoupled":
+ prefixed_top_name = "%s_memstream" % (node.name)
+ else:
+ raise Exception(
+ """Please set mem_mode to "const" or "decoupled", currently no other
+ parameter value is supported!"""
+ )
+ return prefixed_top_name
+
def calc_wmem(self):
"""Calculates and returns WMEM."""
mw = self.get_nodeattr("MW")
@@ -98,27 +136,34 @@ class StreamingFCLayer_Batch(HLSCustomOp):
pe = self.get_nodeattr("PE")
return mh // pe
- def make_shape_compatible_op(self):
- pass
+ def make_shape_compatible_op(self, model):
+ oshape = self.get_normal_output_shape()
+ # implement tensor with correct shape
+ values = np.random.randn(*oshape).astype(np.float32)
+ return helper.make_node(
+ "Constant",
+ inputs=[],
+ outputs=[self.onnx_node.output[0]],
+ value=helper.make_tensor(
+ name="const_tensor",
+ data_type=TensorProto.FLOAT,
+ dims=values.shape,
+ vals=values.flatten().astype(float),
+ ),
+ )
def infer_node_datatype(self, model):
- pass
+ node = self.onnx_node
+ # check input datatype against property
+ idt_name = self.get_input_datatype().name
+ exp_idt_name = self.get_nodeattr("inputDataType")
+ assert exp_idt_name == idt_name, "Bad input DataType for StreamingFCLayer"
+ # set output datatype from property
+ odt = self.get_output_datatype()
+ model.set_tensor_datatype(node.output[0], odt)
def verify_node(self):
info_messages = []
-
- # verify number of attributes
- num_of_attr = 14
- if len(self.onnx_node.attribute) == num_of_attr:
- info_messages.append("The number of attributes is correct")
- else:
- info_messages.append(
- """The number of attributes is incorrect,
- {} should have {} attributes""".format(
- self.onnx_node.op_type, num_of_attr
- )
- )
-
# verify that "domain" is set to "finn"
domain_value = self.onnx_node.domain
if domain_value == "finn":
@@ -146,17 +191,10 @@ class StreamingFCLayer_Batch(HLSCustomOp):
self.get_nodeattr("inputDataType")
self.get_nodeattr("weightDataType")
self.get_nodeattr("outputDataType")
- self.get_nodeattr("ActVal")
- self.get_nodeattr("binaryXnorMode")
- self.get_nodeattr("noActivation")
info_messages.append("All necessary attributes exist")
except Exception:
info_messages.append(
- """The necessary attributes do not exist.
- StreamingFCLayer_Batch needs the following attributes:
- code_gen_dir_npysim, executable_path, resType, MW, MH, SIMD, PE,
- inputDataType, weightDataType, outputDataType, ActVal,
- binaryXnorMode, noActivation"""
+ """The required StreamingFCLayer attributes do not exist."""
)
# verify the number of inputs depending on noActivation value
@@ -243,26 +281,60 @@ class StreamingFCLayer_Batch(HLSCustomOp):
def get_instream_width(self):
i_bits = self.get_input_datatype().bitwidth()
- return i_bits * self.get_nodeattr("SIMD")
+ in_width = i_bits * self.get_nodeattr("SIMD")
+ return in_width
def get_outstream_width(self):
o_bits = self.get_output_datatype().bitwidth()
- return o_bits * self.get_nodeattr("PE")
+ out_width = o_bits * self.get_nodeattr("PE")
+ return out_width
+
+ def get_weightstream_width(self):
+ pe = self.get_nodeattr("PE")
+ simd = self.get_nodeattr("SIMD")
+ wp = self.get_weight_datatype().bitwidth()
+ w_width = pe * simd * wp
+ return w_width
+
+ def get_weightstream_width_padded(self):
+ weight_width = self.get_weightstream_width()
+ return roundup_to_integer_multiple(weight_width, 8)
+
+ def get_ap_int_max_w(self):
+ temp_value = super().get_ap_int_max_w()
+ weightstream = self.get_weightstream_width()
+ return max([weightstream, temp_value])
def get_folded_input_shape(self):
mw = self.get_nodeattr("MW")
simd = self.get_nodeattr("SIMD")
sf = mw // simd
- return (1, sf, simd)
+ vecs = list(self.get_nodeattr("numInputVectors"))
+ folded_input_shape = tuple(vecs + [sf, simd])
+ return folded_input_shape
def get_folded_output_shape(self):
mh = self.get_nodeattr("MH")
pe = self.get_nodeattr("PE")
nf = mh // pe
- return (1, nf, pe)
+ vecs = list(self.get_nodeattr("numInputVectors"))
+ folded_output_shape = tuple(vecs + [nf, pe])
+ return folded_output_shape
+
+ def get_normal_input_shape(self):
+ mw = self.get_nodeattr("MW")
+ vecs = list(self.get_nodeattr("numInputVectors"))
+ normal_input_shape = tuple(vecs + [mw])
+ return normal_input_shape
+
+ def get_normal_output_shape(self):
+ mh = self.get_nodeattr("MH")
+ vecs = list(self.get_nodeattr("numInputVectors"))
+ normal_output_shape = tuple(vecs + [mh])
+ return normal_output_shape
def get_number_output_values(self):
- nf = self.get_folded_output_shape()[1]
+ nf = np.prod(self.get_folded_output_shape()[:-1])
return nf
def get_template_param_values(self):
@@ -272,13 +344,13 @@ class StreamingFCLayer_Batch(HLSCustomOp):
inp_hls_str = self.get_input_datatype().get_hls_datatype_str()
out_hls_str = self.get_output_datatype().get_hls_datatype_str()
inp_is_binary = self.get_input_datatype() == DataType.BINARY
- out_is_binary = self.get_output_datatype() == DataType.BINARY
+ # out_is_binary = self.get_output_datatype() == DataType.BINARY
wt_is_binary = self.get_weight_datatype() == DataType.BINARY
bin_xnor_mode = self.get_nodeattr("binaryXnorMode") == 1
if (inp_is_binary or wt_is_binary) and (not bin_xnor_mode):
raise Exception("True binary (non-bipolar) inputs not yet supported")
inp_is_bipolar = self.get_input_datatype() == DataType.BIPOLAR
- out_is_bipolar = self.get_output_datatype() == DataType.BIPOLAR
+ # out_is_bipolar = self.get_output_datatype() == DataType.BIPOLAR
wt_is_bipolar = self.get_weight_datatype() == DataType.BIPOLAR
# reinterpret inp/wt as bipolar if bin_xnor_mode is iset
inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode)
@@ -298,11 +370,10 @@ class StreamingFCLayer_Batch(HLSCustomOp):
elif (not inp_is_bipolar) and (not wt_is_bipolar):
ret["TSrcI"] = "Slice<%s>" % inp_hls_str
ret["TWeightI"] = "Identity"
+
# fill in TDstI
- if out_is_bipolar or out_is_binary:
- ret["TDstI"] = "Identity"
- else:
- ret["TDstI"] = "Slice<%s>" % out_hls_str
+ ret["TDstI"] = "Slice<%s>" % out_hls_str
+
return ret
def get_hls_compatible_weight_tensor(self, orig_weight_matrix):
@@ -396,8 +467,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
return ret.reshape(1, pe, tmem, n_thres_steps)
def generate_params(self, model, path):
- """Saves weights into params.h and if existing thresholds into thresh.h."""
- code_gen_dir = path
+ mem_mode = self.get_nodeattr("mem_mode")
# weights
weights = model.get_initializer(self.onnx_node.input[1])
# convert weights into hlslib-compatible format
@@ -407,32 +477,95 @@ class StreamingFCLayer_Batch(HLSCustomOp):
# so use it as such for weight generation
if self.get_weight_datatype() == DataType.BIPOLAR:
export_wdt = DataType.BINARY
- weight_hls_code = numpy_to_hls_code(
- weight_tensor, export_wdt, "weights", True, True
- )
- # write weights into params.h
- # code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
- f_weights = open("{}/params.h".format(code_gen_dir), "w")
-
- if export_wdt.bitwidth() != 1:
- f_weights.write(
- "static FixedPointWeights<{},{},{},{}> weights = ".format(
- self.get_nodeattr("SIMD"),
- export_wdt.get_hls_datatype_str(),
- self.get_nodeattr("PE"),
- self.calc_wmem(),
+ code_gen_dir = path
+
+ if mem_mode == "const":
+ """Saves weights into params.h"""
+ weight_hls_code = numpy_to_hls_code(
+ weight_tensor, export_wdt, "weights", True, True
+ )
+ # write weights into params.h
+ f_weights = open("{}/params.h".format(code_gen_dir), "w")
+
+ if export_wdt.bitwidth() != 1:
+ f_weights.write(
+ "const FixedPointWeights<{},{},{},{}> weights = ".format(
+ self.get_nodeattr("SIMD"),
+ export_wdt.get_hls_datatype_str(),
+ self.get_nodeattr("PE"),
+ self.calc_wmem(),
+ )
)
+ else:
+ f_weights.write(
+ "const BinaryWeights<{},{},{}> weights = ".format(
+ self.get_nodeattr("SIMD"),
+ self.get_nodeattr("PE"),
+ self.calc_wmem(),
+ )
+ )
+ f_weights.write(weight_hls_code)
+ f_weights.close()
+
+ elif mem_mode == "decoupled":
+ """Saves weights in corresponding file format for npysim or rtlsim"""
+ # transpose weight tensor from (1, PE, WMEM, SIMD) to (1, WMEM, PE, SIMD)
+ # and save as unflipped weight tensor to be able to differentiate between
+ # flipped an unflipped weight tensor (has to be flipped for npysim)
+
+ weight_tensor_unflipped = np.transpose(weight_tensor, (0, 2, 1, 3))
+
+ # flip PE dimension and reverse SIMD flip for saving weights in .npy
+ weight_tensor_flipped = np.flip(weight_tensor_unflipped, axis=-2)
+ weight_tensor_flipped = np.flip(weight_tensor_flipped, axis=-1)
+
+ # reshape weight tensor (flipped and unflipped) to desired shape
+ pe = self.get_nodeattr("PE")
+ simd = self.get_nodeattr("SIMD")
+ # unflipped
+ weight_tensor_unflipped = weight_tensor_unflipped.reshape(1, -1, pe * simd)
+ weight_tensor_unflipped = weight_tensor_unflipped.copy()
+ # flipped
+ weight_tensor_flipped = weight_tensor_flipped.reshape(1, -1, pe * simd)
+ weight_tensor_flipped = weight_tensor_flipped.copy()
+
+ """Saves weights into .npy file"""
+ np.save(os.path.join(code_gen_dir, "weights.npy"), weight_tensor_flipped)
+
+ """Saves weights into .dat file"""
+ # convert weight values into hexstring
+ weight_width = self.get_weightstream_width()
+ # pad to nearest 4 bits to get hex strings
+ weight_width_padded = roundup_to_integer_multiple(weight_width, 4)
+ weight_tensor_unflipped = pack_innermost_dim_as_hex_string(
+ weight_tensor_unflipped, export_wdt, weight_width_padded, prefix=""
)
+ weight_stream_len = np.prod(weight_tensor_unflipped.shape)
+ factor = math.ceil(weight_stream_len / 1024)
+ # add zeroes to pad out file to 1024 entries
+ weight_stream = weight_tensor_unflipped.flatten()
+ pad_amt = (factor * 1024) - weight_stream_len
+ weight_stream = np.pad(
+ weight_stream, (0, pad_amt), mode="constant", constant_values="0"
+ )
+ weight_stream = weight_stream.copy()
+ i = 0
+ j = 0
+ for val in weight_stream:
+ if i == 1024:
+ i = 0
+ j += 1
+ with open("{}/memblock_{}.dat".format(code_gen_dir, j), "a+") as f:
+ f.write(val + "\n")
+ i += 1
+
else:
- f_weights.write(
- "static BinaryWeights<{},{},{}> weights = ".format(
- self.get_nodeattr("SIMD"), self.get_nodeattr("PE"), self.calc_wmem()
- )
+ raise Exception(
+ """Please set mem_mode to "const"i or "decoupled", currently no other
+ parameter value is supported!"""
)
- f_weights.write(weight_hls_code)
- f_weights.close()
- # thresholds
+ # save thresholds in thresh.h
if len(self.onnx_node.input) > 2:
thresholds = model.get_initializer(self.onnx_node.input[2])
if thresholds is not None:
@@ -453,7 +586,6 @@ class StreamingFCLayer_Batch(HLSCustomOp):
threshold_tensor, tdt, "thresholds", False, True
)
# write thresholds into thresh.h
- # code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
f_thresh = open("{}/thresh.h".format(code_gen_dir), "w")
tdt_hls = tdt.get_hls_datatype_str()
# use binary to export bipolar activations
@@ -463,7 +595,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
odt_hls = export_odt.get_hls_datatype_str()
f_thresh.write(
"static ThresholdsActivation<{},{},{},{},{},{},{}> threshs \
- = ".format(
+ = ".format(
self.calc_tmem(),
self.get_nodeattr("PE"),
threshold_tensor.shape[-1],
@@ -479,12 +611,6 @@ class StreamingFCLayer_Batch(HLSCustomOp):
def execute_node(self, context, graph):
mode = self.get_nodeattr("exec_mode")
node = self.onnx_node
- mw = self.get_nodeattr("MW")
- mh = self.get_nodeattr("MH")
- simd = self.get_nodeattr("SIMD")
- pe = self.get_nodeattr("PE")
- sf = mw // simd
- nf = mh // pe
# TODO ensure codegen dir exists
if mode == "npysim":
@@ -510,7 +636,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
str(context[inputs].dtype) == "float32"
), """Input datatype is
not float32 as expected."""
- expected_inp_shape = (1, sf, simd)
+ expected_inp_shape = self.get_folded_input_shape()
reshaped_input = context[inputs].reshape(expected_inp_shape)
if self.get_input_datatype() == DataType.BIPOLAR:
# store bipolar activations as binary
@@ -518,6 +644,8 @@ class StreamingFCLayer_Batch(HLSCustomOp):
export_idt = DataType.BINARY
else:
export_idt = self.get_input_datatype()
+ # make copy before saving the array
+ reshaped_input = reshaped_input.copy()
np.save(
os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)),
reshaped_input,
@@ -536,55 +664,35 @@ class StreamingFCLayer_Batch(HLSCustomOp):
out = context[node.output[0]]
out = 2 * out - 1
context[node.output[0]] = out
- assert context[node.output[0]].shape == (
- 1,
- nf,
- pe,
- ), """Output shape is not
- as expected (1, nf, pe)"""
+ assert (
+ context[node.output[0]].shape == self.get_folded_output_shape()
+ ), """Output shape is not as expected"""
# reshape output to have expected shape
- context[node.output[0]] = context[node.output[0]].reshape(1, mh)
+ oshape = self.get_normal_output_shape()
+ context[node.output[0]] = context[node.output[0]].reshape(*oshape)
elif mode == "rtlsim":
- prefixed_top_name = "%s_%s" % (node.name, node.name)
- # check if needed file exists
- verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
- code_gen_dir, node.name, prefixed_top_name
+ sim = self.get_rtlsim()
+ nbits = self.get_instream_width()
+ inp = npy_to_rtlsim_input(
+ "{}/input_0.npy".format(code_gen_dir), export_idt, nbits
+ )
+ super().reset_rtlsim(sim)
+ super().toggle_clk(sim)
+ output = self.rtlsim(sim, inp)
+ odt = self.get_output_datatype()
+ target_bits = odt.bitwidth()
+ packed_bits = self.get_outstream_width()
+ out_npy_path = "{}/output.npy".format(code_gen_dir)
+ out_shape = self.get_folded_output_shape()
+ rtlsim_output_to_npy(
+ output, out_npy_path, odt, out_shape, packed_bits, target_bits
)
- if os.path.isfile(verilog_file):
- nbits = self.get_instream_width()
- inp = npy_to_rtlsim_input(
- "{}/input_0.npy".format(code_gen_dir), export_idt, nbits
- )
- sim = PyVerilator.build(
- verilog_file,
- verilog_path=[
- "{}/project_{}/sol1/impl/verilog/".format(
- code_gen_dir, node.name
- )
- ],
- )
- super().reset_rtlsim(sim)
- super().toggle_clk(sim)
- output = self.rtlsim(sim, inp)
- odt = self.get_output_datatype()
- target_bits = odt.bitwidth()
- packed_bits = self.get_outstream_width()
- out_npy_path = "{}/output.npy".format(code_gen_dir)
- rtlsim_output_to_npy(
- output, out_npy_path, odt, (1, nf, pe), packed_bits, target_bits
- )
-
- # load and reshape output
- output = np.load(out_npy_path)
- output = np.asarray([output], dtype=np.float32).reshape(1, mh)
- context[node.output[0]] = output
-
- else:
- raise Exception(
- """Found no verilog files for this node,
- did you run the codegen_ipgen transformation?"""
- )
+ # load and reshape output
+ output = np.load(out_npy_path)
+ oshape = self.get_normal_output_shape()
+ output = np.asarray([output], dtype=np.float32).reshape(*oshape)
+ context[node.output[0]] = output
else:
raise Exception(
"""Invalid value for attribute exec_mode! Is currently set to: {}
@@ -596,17 +704,30 @@ class StreamingFCLayer_Batch(HLSCustomOp):
def global_includes(self):
self.code_gen_dict["$GLOBALS$"] = ['#include "weights.hpp"']
self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"']
- self.code_gen_dict["$GLOBALS$"] += ['#include "params.h"']
+
+ mem_mode = self.get_nodeattr("mem_mode")
+ if mem_mode == "const":
+ # self.code_gen_dict["$GLOBALS$"] += ['#include "params.h"']
+ pass
+ elif mem_mode == "decoupled":
+ self.code_gen_dict["$GLOBALS$"] += ['#include "mvau.hpp"']
+ else:
+ raise Exception(
+ """Please set mem_mode to "const" or "decoupled", currently no other
+ parameter value is supported!"""
+ )
if self.calc_tmem() != 0:
# TODO find a better way of checking for no pregenerated thresholds
self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"']
def defines(self, var):
- numReps = 1
+ mem_mode = self.get_nodeattr("mem_mode")
+ numInputVectors = list(self.get_nodeattr("numInputVectors"))
+ numReps = np.prod(numInputVectors)
self.code_gen_dict["$DEFINES$"] = [
- """#define MW1 {}\n #define MH1 {}\n #define SIMD1 {}\n
- #define PE1 {}\n #define WMEM1 {}\n #define TMEM1 {}\n
- #define numReps {}""".format(
+ """#define MW1 {}\n #define MH1 {}\n
+ #define SIMD1 {}\n #define PE1 {}\n #define WMEM1 {}\n
+ #define TMEM1 {}\n #define numReps {}""".format(
self.get_nodeattr("MW"),
self.get_nodeattr("MH"),
self.get_nodeattr("SIMD"),
@@ -616,9 +737,11 @@ class StreamingFCLayer_Batch(HLSCustomOp):
numReps,
)
]
- if var == "ipgen":
- self.code_gen_dict["$DEFINES$"].append("#define PRAGMA_SUB(x) _Pragma (#x)")
- self.code_gen_dict["$DEFINES$"].append("#define DO_PRAGMA(x) PRAGMA_SUB(x)")
+ if mem_mode == "decoupled":
+ wdt = self.get_weight_datatype()
+ self.code_gen_dict["$DEFINES$"].append(
+ "#define WP1 {}\n".format(wdt.bitwidth())
+ )
def read_npy_data(self):
code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
@@ -639,7 +762,23 @@ class StreamingFCLayer_Batch(HLSCustomOp):
% (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)
)
+ mem_mode = self.get_nodeattr("mem_mode")
+ if mem_mode == "decoupled":
+ wdt = self.get_weight_datatype()
+ elem_bits = wdt.bitwidth()
+ packed_bits = self.get_weightstream_width()
+ packed_hls_type = "ap_uint<%d>" % packed_bits
+ elem_hls_type = wdt.get_hls_datatype_str()
+ npy_type = "float"
+ npy_in = "%s/weights.npy" % code_gen_dir
+
+ self.code_gen_dict["$READNPYDATA$"].append(
+ 'npy2apintstream<%s, %s, %d, %s>("%s", weights, false, numReps);'
+ % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)
+ )
+
def strm_decl(self):
+ mem_mode = self.get_nodeattr("mem_mode")
self.code_gen_dict["$STREAMDECLARATIONS$"] = []
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_instream_width())
@@ -648,25 +787,58 @@ class StreamingFCLayer_Batch(HLSCustomOp):
'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_outstream_width())
)
+ if mem_mode == "decoupled":
+ self.code_gen_dict["$STREAMDECLARATIONS$"].append(
+ 'hls::stream<ap_uint<{}>> weights ("weights");'.format(
+ self.get_weightstream_width()
+ )
+ )
+
def docompute(self):
- node = self.onnx_node
+ mem_mode = self.get_nodeattr("mem_mode")
tmpl_args = self.get_template_param_values()
if self.calc_tmem() == 0:
odtype_hls_str = self.get_output_datatype().get_hls_datatype_str()
threshs = "PassThroughActivation<%s>()" % odtype_hls_str
else:
threshs = "threshs"
- self.code_gen_dict["$DOCOMPUTE$"] = [
- """{}<MW1, MH1, SIMD1, PE1, {}, {}, {}>
- (in0, out, weights, {}, numReps, {});""".format(
- node.op_type,
- tmpl_args["TSrcI"],
- tmpl_args["TDstI"],
- tmpl_args["TWeightI"],
- threshs,
- self.get_nodeattr("resType"),
+ if mem_mode == "const":
+ node = self.onnx_node
+ self.code_gen_dict["$DOCOMPUTE$"] = [
+ """{}<MW1, MH1, SIMD1, PE1, {}, {}, {}>
+ (in0, out, weights, {}, numReps, {});""".format(
+ node.op_type,
+ tmpl_args["TSrcI"],
+ tmpl_args["TDstI"],
+ tmpl_args["TWeightI"],
+ threshs,
+ self.get_nodeattr("resType"),
+ )
+ ]
+ elif mem_mode == "decoupled":
+ wdt = self.get_weight_datatype()
+ if wdt == DataType.BIPOLAR:
+ export_wdt = DataType.BINARY
+ else:
+ export_wdt = wdt
+ wdtype_hls_str = export_wdt.get_hls_datatype_str()
+ self.code_gen_dict["$DOCOMPUTE$"] = [
+ """Matrix_Vector_Activate_Stream_Batch<MW1, MH1, SIMD1, PE1, {}, {}, {}, {} >
+ (in0, out, weights, {}, numReps, {});""".format(
+ tmpl_args["TSrcI"],
+ tmpl_args["TDstI"],
+ tmpl_args["TWeightI"],
+ wdtype_hls_str,
+ threshs,
+ self.get_nodeattr("resType"),
+ )
+ ]
+
+ else:
+ raise Exception(
+ """Please set mem_mode to "const" or "decoupled", currently no other
+ parameter value is supported!"""
)
- ]
def dataoutstrm(self):
code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
@@ -680,8 +852,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
npy_out = "%s/output.npy" % code_gen_dir
- nf = int(self.get_nodeattr("MH") / self.get_nodeattr("PE"))
- shape = (1, nf, self.get_nodeattr("PE"))
+ shape = self.get_folded_output_shape()
shape_cpp_str = str(shape).replace("(", "{").replace(")", "}")
# note: the innermost dim is not reversed for the output
@@ -701,17 +872,39 @@ class StreamingFCLayer_Batch(HLSCustomOp):
self.code_gen_dict["$SAVEASCNPY$"] = []
def blackboxfunction(self):
- self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
- """void {}(hls::stream<ap_uint<{}>> &in0,
- hls::stream<ap_uint<{}>> &out
- )""".format(
- self.onnx_node.name,
- self.get_instream_width(),
- self.get_outstream_width(),
+ mem_mode = self.get_nodeattr("mem_mode")
+ if mem_mode == "const":
+ self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
+ """void {}(hls::stream<ap_uint<{}>> &in0,
+ hls::stream<ap_uint<{}>> &out
+ )""".format(
+ self.onnx_node.name,
+ self.get_instream_width(),
+ self.get_outstream_width(),
+ )
+ ]
+ elif mem_mode == "decoupled":
+ self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
+ """void {}(
+ hls::stream<ap_uint<{}>> &in0,
+ hls::stream<ap_uint<{}>> &weights,
+ hls::stream<ap_uint<{}>> &out
+ )""".format(
+ self.onnx_node.name,
+ self.get_instream_width(),
+ self.get_weightstream_width(),
+ self.get_outstream_width(),
+ )
+ ]
+
+ else:
+ raise Exception(
+ """Please set mem_mode to "const" or "decoupled", currently no other
+ parameter value is supported!"""
)
- ]
def pragmas(self):
+ mem_mode = self.get_nodeattr("mem_mode")
self.code_gen_dict["$PRAGMAS$"] = ["#pragma HLS INTERFACE axis port=in0"]
self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE axis port=out")
in_fifo_depth = self.get_nodeattr("inFIFODepth")
@@ -728,27 +921,154 @@ class StreamingFCLayer_Batch(HLSCustomOp):
self.code_gen_dict["$PRAGMAS$"].append(
"#pragma HLS INTERFACE ap_ctrl_none port=return"
)
- # the weight tensor is ap_uint<simd*prec> [PE][WMEM]
- # partition for parallel access along the PE dimension (dim 1)
- self.code_gen_dict["$PRAGMAS$"].append(
- (
- "DO_PRAGMA(HLS ARRAY_PARTITION "
- "variable=weights.m_weights complete dim=1)"
+
+ if mem_mode == "const":
+ self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"')
+ # the weight tensor is ap_uint<simd*prec> [PE][WMEM]
+ # partition for parallel access along the PE dimension (dim 1)
+ self.code_gen_dict["$PRAGMAS$"].append(
+ (
+ "#pragma HLS ARRAY_PARTITION variable=weights.m_weights "
+ "complete dim=1"
+ )
)
- )
+ elif mem_mode == "decoupled":
+ self.code_gen_dict["$PRAGMAS$"].append(
+ "#pragma HLS INTERFACE axis port=weights"
+ )
+ self.code_gen_dict["$PRAGMAS$"].append(
+ "#pragma HLS stream depth=8 variable=weights"
+ )
+
+ else:
+ raise Exception(
+ """Please set mem_mode to "const", currently no other
+ parameter value is supported!"""
+ )
+
# the threshold tensor is acc_type [PE][TMEM][N_THRES]
- # partition for parallel access along PE and N_THRES dimensions (dims 1 and 3)
+ # partition for parallel access along PE and N_THRES
+ # dimensions (dims 1 and 3)
if self.calc_tmem() != 0:
# TODO find a better way of checking for no pregenerated thresholds
self.code_gen_dict["$PRAGMAS$"].append(
(
- "DO_PRAGMA(HLS ARRAY_PARTITION variable=threshs.m_thresholds "
- "complete dim=1)"
+ "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds "
+ "complete dim=1"
)
)
self.code_gen_dict["$PRAGMAS$"].append(
(
- "DO_PRAGMA(HLS ARRAY_PARTITION variable=threshs.m_thresholds "
- "complete dim=3)"
+ "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds "
+ "complete dim=3"
)
)
+
+ def code_generation_ipgen(self, model, fpgapart, clk):
+ # generate code for all mem_mode of MVAU/FCLayer unit
+ super().code_generation_ipgen(model, fpgapart, clk)
+
+ # if mem_mode = "decoupled" generate code for verilog wrapper
+ mem_mode = self.get_nodeattr("mem_mode")
+ if mem_mode == "decoupled":
+ # empty code gen dictionary for new entries
+ self.code_gen_dict.clear()
+ self.code_gen_dict["$TOPNAME$"] = [
+ "{}_memstream".format(self.onnx_node.name)
+ ]
+ self.code_gen_dict["$LAYER_NAME$"] = [
+ "{}_{}".format(self.onnx_node.name, self.onnx_node.name)
+ ]
+ # make instream width a multiple of 8 for AXI stream interface
+ in_width = self.get_instream_width_padded()
+ self.code_gen_dict["$IN_RANGE$"] = ["[{}:0]".format(in_width - 1)]
+ self.code_gen_dict["$OUT_RANGE$"] = [
+ "[{}:0]".format(self.get_outstream_width_padded() - 1)
+ ]
+ # make weight stream width a multiple of 8 for AXI stream interface
+ weight_width = self.get_weightstream_width_padded()
+ self.code_gen_dict["$WEIGHT_RANGE$"] = ["[{}:0]".format(weight_width - 1)]
+ self.code_gen_dict["$WEIGHT_WIDTH$"] = [str(weight_width)]
+ self.code_gen_dict["$WSTREAM_DEPTH$"] = [str(self.calc_wmem())]
+ self.code_gen_dict["$MEM_DEPTH$"] = [
+ str(roundup_to_integer_multiple(self.calc_wmem(), 1024))
+ ]
+ self.code_gen_dict["$RAM_STYLE$"] = [self.get_nodeattr("ram_style")]
+
+ template = self.decoupled_wrapper
+
+ for key in self.code_gen_dict:
+ # transform list into long string separated by '\n'
+ code_gen_line = "\n".join(self.code_gen_dict[key])
+ template = template.replace(key, code_gen_line)
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ f = open(
+ os.path.join(
+ code_gen_dir, "{}_memstream.v".format(self.onnx_node.name)
+ ),
+ "w",
+ )
+ f.write(template)
+ f.close()
+ self.code_gen_dict.clear()
+
+ def ipgen_singlenode_code(self):
+ # generate ip block of MVAU/FCLayer unit for all mem modes
+ super().ipgen_singlenode_code()
+
+ mem_mode = self.get_nodeattr("mem_mode")
+ if mem_mode == "decoupled":
+ # copy necessary verilog and .dat files
+ # into verilog folder in code generation folder
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ verilog_folder = "{}/project_{}/sol1/impl/verilog/".format(
+ code_gen_dir, self.onnx_node.name
+ )
+ # copy memstream components from finn-rtllib
+ memstream_dir = "/workspace/finn/finn-rtllib/memstream/hdl/"
+ for file in os.listdir(memstream_dir):
+ if file.endswith(".v"):
+ verilog_file = os.path.join(memstream_dir, file)
+ copy(verilog_file, verilog_folder)
+ # copy .dat files of weights
+ for file in os.listdir(code_gen_dir):
+ if file.endswith(".dat"):
+ dat_file = os.path.join(code_gen_dir, file)
+ copy(dat_file, verilog_folder)
+ # copy verilog wrapper
+ verilog_wrapper = "{}/{}_memstream.v".format(
+ code_gen_dir, self.onnx_node.name
+ )
+ copy(verilog_wrapper, verilog_folder)
+ # prepare the IP packaging tcl template
+ template = templates.ip_package_tcl
+ self.code_gen_dict["$TOPNAME$"] = [
+ "{}_memstream".format(self.onnx_node.name)
+ ]
+ self.code_gen_dict["$VERILOG_DIR$"] = [verilog_folder]
+ for key in self.code_gen_dict:
+ # transform list into long string separated by '\n'
+ code_gen_line = "\n".join(self.code_gen_dict[key])
+ template = template.replace(key, code_gen_line)
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ f = open(os.path.join(verilog_folder, "package_ip.tcl"), "w")
+ f.write(template)
+ f.close()
+ # create a shell script and call Vivado to invoke the IP pkg script
+ make_project_sh = verilog_folder + "/make_ip.sh"
+ working_dir = os.environ["PWD"]
+ with open(make_project_sh, "w") as f:
+ f.write("#!/bin/bash \n")
+ f.write("cd {}\n".format(verilog_folder))
+ f.write("vivado -mode batch -source package_ip.tcl\n")
+ f.write("cd {}\n".format(working_dir))
+ bash_command = ["bash", make_project_sh]
+ process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
+ process_compile.communicate()
+ # re-set ip_path to point to the new packaged IP
+ self.set_nodeattr("ip_path", verilog_folder)
+ vlnv = "xilinx.com:hls:%s:1.0" % (
+ "{}_memstream".format(self.onnx_node.name)
+ )
+ self.set_nodeattr("ip_vlnv", vlnv)
+ self.code_gen_dict.clear()
diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py
new file mode 100644
index 0000000000000000000000000000000000000000..eb96c6c04eb0b7b83c3f925e10f86b17ec399e42
--- /dev/null
+++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py
@@ -0,0 +1,307 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+import os
+import numpy as np
+from shutil import copy
+import subprocess
+
+from finn.custom_op.fpgadataflow import HLSCustomOp
+from finn.core.datatype import DataType
+from onnx import TensorProto, helper
+from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
+
+from . import templates
+
+
+class StreamingFIFO(HLSCustomOp):
+ def __init__(self, onnx_node):
+ super().__init__(onnx_node)
+ self.strm_fifo_wrapper = templates.strm_fifo_wrapper
+
+ def get_nodeattr_types(self):
+ my_attrs = {
+ # FIFO depth
+ "depth": ("i", True, 0),
+ # folded shape of input/output
+ "folded_shape": ("ints", True, []),
+ # FINN DataTypes for inputs/outputs
+ "dataType": ("s", True, ""),
+ }
+ my_attrs.update(super().get_nodeattr_types())
+
+ return my_attrs
+
+ def make_shape_compatible_op(self, model):
+ exp_ishape = self.get_normal_input_shape()
+ oshape = self.get_normal_output_shape()
+ ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0]))
+ assert ishape == tuple(exp_ishape), "Unexpect input shape for StreamingFIFO."
+ # implement tensor with correct shape
+ values = np.random.randn(*oshape).astype(np.float32)
+ return helper.make_node(
+ "Constant",
+ inputs=[],
+ outputs=[self.onnx_node.output[0]],
+ value=helper.make_tensor(
+ name="const_tensor",
+ data_type=TensorProto.FLOAT,
+ dims=values.shape,
+ vals=values.flatten().astype(float),
+ ),
+ )
+
+ def infer_node_datatype(self, model):
+ node = self.onnx_node
+ # data type stays the same
+ dtype = model.get_tensor_datatype(node.input[0])
+ model.set_tensor_datatype(node.output[0], dtype)
+
+ def verify_node(self):
+ pass
+
+ def get_verilog_top_module_name(self):
+ "Return the Verilog top module name for this node."
+
+ node = self.onnx_node
+ prefixed_top_name = "%s" % (node.name)
+ return prefixed_top_name
+
+ def code_generation_ipgen(self, model, fpgapart, clk):
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ verilog_dir = "{}/project_{}/sol1/impl/verilog".format(
+ code_gen_dir, self.onnx_node.name
+ )
+ os.makedirs(verilog_dir)
+ # copy Q_srl.v from finn-rtllib to verilog directory
+ memstream_dir = "/workspace/finn/finn-rtllib/memstream/hdl/"
+ Q_file = os.path.join(memstream_dir, "Q_srl.v")
+ copy(Q_file, verilog_dir)
+
+ # empty code gen dictionary for new entries
+ self.code_gen_dict.clear()
+ self.code_gen_dict["$TOPNAME$"] = ["{}".format(self.onnx_node.name)]
+ self.code_gen_dict["$LAYER_NAME$"] = [
+ "{}_{}".format(self.onnx_node.name, self.onnx_node.name)
+ ]
+ # make instream width a multiple of 8 for axi interface
+ in_width = self.get_instream_width_padded()
+ self.code_gen_dict["$IN_RANGE$"] = ["[{}:0]".format(in_width - 1)]
+ self.code_gen_dict["$OUT_RANGE$"] = ["[{}:0]".format(in_width - 1)]
+ self.code_gen_dict["$WIDTH$"] = [str(in_width)]
+ self.code_gen_dict["$DEPTH$"] = [str(self.get_nodeattr("depth"))]
+
+ template = self.strm_fifo_wrapper
+
+ for key in self.code_gen_dict:
+ # transform list into long string separated by '\n'
+ code_gen_line = "\n".join(self.code_gen_dict[key])
+ template = template.replace(key, code_gen_line)
+ f = open(os.path.join(verilog_dir, "{}.v".format(self.onnx_node.name,)), "w",)
+ f.write(template)
+ f.close()
+ self.code_gen_dict.clear()
+
+ def ipgen_singlenode_code(self):
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ verilog_dir = "{}/project_{}/sol1/impl/verilog".format(
+ code_gen_dir, self.onnx_node.name
+ )
+ # prepare the IP packaging tcl template
+ template = templates.ip_package_tcl
+ self.code_gen_dict.clear()
+ self.code_gen_dict["$TOPNAME$"] = ["{}".format(self.onnx_node.name)]
+ self.code_gen_dict["$VERILOG_DIR$"] = [verilog_dir]
+ for key in self.code_gen_dict:
+ # transform list into long string separated by '\n'
+ code_gen_line = "\n".join(self.code_gen_dict[key])
+ template = template.replace(key, code_gen_line)
+ f = open(os.path.join(verilog_dir, "package_ip.tcl"), "w")
+ f.write(template)
+ f.close()
+ # create a shell script and call Vivado to invoke the IP pkg script
+ make_project_sh = verilog_dir + "/make_ip.sh"
+ working_dir = os.environ["PWD"]
+ with open(make_project_sh, "w") as f:
+ f.write("#!/bin/bash \n")
+ f.write("cd {}\n".format(verilog_dir))
+ f.write("vivado -mode batch -source package_ip.tcl\n")
+ f.write("cd {}\n".format(working_dir))
+ bash_command = ["bash", make_project_sh]
+ process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
+ process_compile.communicate()
+ # set ipgen_path and ip_path to point to the new packaged IP
+ self.set_nodeattr("ipgen_path", verilog_dir)
+ self.set_nodeattr("ip_path", verilog_dir)
+ vlnv = "xilinx.com:hls:%s:1.0" % (self.onnx_node.name)
+ self.set_nodeattr("ip_vlnv", vlnv)
+ self.code_gen_dict.clear()
+
+ def get_normal_input_shape(self):
+ depth = self.get_nodeattr("depth")
+ # depth has to be between 2 and 256 with the current
+ # StreamingFIFO implementation
+ assert (
+ depth >= 2
+ ), """Depth is too low. Please set node attribute "depth" to a value
+ between 2 and 256"""
+ assert (
+ depth <= 256
+ ), """Depth is too high. Please set node attribute "depth" to a value
+ between 2 and 256"""
+ # derive normal shape from folded shape
+ # StreamingFIFOs are inserted in between fpgadataflow nodes
+ # the folded shape could be for example (1, nf, pe)
+ # with nf (neuron folding): mh // pe
+ # the normal input shape is in this case (1, mh)
+ # so to achieve this the two inner dimensions are multiplied
+ # and together with all previous dimensions
+ # this gives the normal input shape
+
+ folded_shape = self.get_nodeattr("folded_shape")
+ # extract inner dimension
+ inner_dim = folded_shape[-1]
+ # multiply with the next inner dimension
+ folding_factor = folded_shape[-2] * inner_dim
+ normal_ishape = []
+ # create the normal_ishape
+ for i in range(len(folded_shape) - 2):
+ normal_ishape.append(folded_shape[i])
+ normal_ishape.append(folding_factor)
+
+ return normal_ishape
+
+ def get_normal_output_shape(self):
+ return self.get_normal_input_shape()
+
+ def get_folded_input_shape(self):
+ return self.get_nodeattr("folded_shape")
+
+ def get_folded_output_shape(self):
+ return self.get_nodeattr("folded_shape")
+
+ def get_instream_width(self):
+ dtype = DataType[self.get_nodeattr("dataType")]
+ folded_shape = self.get_nodeattr("folded_shape")
+ in_width = folded_shape[-1] * dtype.bitwidth()
+ return in_width
+
+ def get_outstream_width(self):
+ dtype = DataType[self.get_nodeattr("dataType")]
+ folded_shape = self.get_nodeattr("folded_shape")
+ in_width = folded_shape[-1] * dtype.bitwidth()
+ return in_width
+
+ def execute_node(self, context, graph):
+ mode = self.get_nodeattr("exec_mode")
+ node = self.onnx_node
+ inp = context[node.input[0]]
+ exp_shape = self.get_normal_input_shape()
+
+ if mode == "npysim":
+ output = inp
+ output = np.asarray([output], dtype=np.float32).reshape(*exp_shape)
+ context[node.output[0]] = output
+ elif mode == "rtlsim":
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ # create a npy file for the input of the node
+ assert (
+ str(inp.dtype) == "float32"
+ ), """Input datatype is
+ not float32 as expected."""
+ expected_inp_shape = self.get_folded_input_shape()
+ reshaped_input = inp.reshape(expected_inp_shape)
+ if DataType[self.get_nodeattr("dataType")] == DataType.BIPOLAR:
+ # store bipolar activations as binary
+ reshaped_input = (reshaped_input + 1) / 2
+ export_idt = DataType.BINARY
+ else:
+ export_idt = DataType[self.get_nodeattr("dataType")]
+ # make copy before saving the array
+ reshaped_input = reshaped_input.copy()
+ np.save(
+ os.path.join(code_gen_dir, "input_0.npy"), reshaped_input,
+ )
+ sim = self.get_rtlsim()
+ nbits = self.get_instream_width()
+ inp = npy_to_rtlsim_input(
+ "{}/input_0.npy".format(code_gen_dir), export_idt, nbits
+ )
+ super().reset_rtlsim(sim)
+ super().toggle_clk(sim)
+ output = self.rtlsim(sim, inp)
+ odt = DataType[self.get_nodeattr("dataType")]
+ target_bits = odt.bitwidth()
+ packed_bits = self.get_outstream_width()
+ out_npy_path = "{}/output.npy".format(code_gen_dir)
+ out_shape = self.get_folded_output_shape()
+ rtlsim_output_to_npy(
+ output, out_npy_path, odt, out_shape, packed_bits, target_bits
+ )
+ # load and reshape output
+ output = np.load(out_npy_path)
+ oshape = self.get_normal_output_shape()
+ output = np.asarray([output], dtype=np.float32).reshape(*oshape)
+ context[node.output[0]] = output
+
+ else:
+ raise Exception("Test")
+
+ def get_number_output_values(self):
+ folded_oshape = self.get_folded_output_shape()
+ return np.prod(folded_oshape[:-1])
+
+ def get_number_input_values(self):
+ folded_ishape = self.get_folded_input_shape()
+ return np.prod(folded_ishape[:-1])
+
+ def global_includes(self):
+ pass
+
+ def defines(self, var):
+ pass
+
+ def read_npy_data(self):
+ pass
+
+ def strm_decl(self):
+ pass
+
+ def docompute(self):
+ pass
+
+ def dataoutstrm(self):
+ pass
+
+ def save_as_npy(self):
+ pass
+
+ def blackboxfunction(self):
+ pass
+
+ def pragmas(self):
+ pass
diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
index 43951332d3637b548093958124735a45cb0edbc4..7334c913b6f85cad4835b6e65eb14c488432af6b 100644
--- a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
@@ -26,7 +26,14 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+import os
+import numpy as np
+
from finn.custom_op.fpgadataflow import HLSCustomOp
+from finn.custom_op.im2col import compute_conv_output_dim
+from finn.core.datatype import DataType
+from onnx import TensorProto, helper
+from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
class StreamingMaxPool_Batch(HLSCustomOp):
@@ -37,31 +44,95 @@ class StreamingMaxPool_Batch(HLSCustomOp):
"ImgDim": ("i", True, 0),
"PoolDim": ("i", True, 0),
"NumChannels": ("i", True, 0),
+ # FINN DataTypes for inputs/outputs
+ "dataType": ("s", True, ""),
}
my_attrs.update(super().get_nodeattr_types())
return my_attrs
- def make_shape_compatible_op(self):
- pass
+ def get_input_datatype(self):
+ """Returns FINN DataType of input."""
+ return DataType[self.get_nodeattr("dataType")]
+
+ def get_output_datatype(self):
+ """Returns FINN DataType of output."""
+ return DataType[self.get_nodeattr("dataType")]
+
+ def get_normal_input_shape(self):
+ ifm_dim = self.get_nodeattr("ImgDim")
+ ifm_ch = self.get_nodeattr("NumChannels")
+ ishape = (1, ifm_dim, ifm_dim, ifm_ch)
+ return ishape
+
+ def get_folded_input_shape(self):
+ # even though there is no folding in the current hlslib op,
+ # insert a time multiplexing axis to remain compatible with the
+ # shapes produced by the rest of the dataflow pipeline
+ ret = list(self.get_normal_input_shape())
+ ret.insert(-1, 1)
+ return tuple(ret)
+
+ def get_normal_output_shape(self):
+ k = self.get_nodeattr("PoolDim")
+ ifm_dim = self.get_nodeattr("ImgDim")
+ ifm_ch = self.get_nodeattr("NumChannels")
+ stride = k
+ pad = 0
+ assert ifm_dim % k == 0, "StreamingMaxPool needs ImgDim % PoolDim == 0"
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad)
+ oshape = (1, ofm_dim, ofm_dim, ifm_ch)
+ return oshape
+
+ def get_folded_output_shape(self):
+ # even though there is no folding in the current hlslib op,
+ # insert a time multiplexing axis to remain compatible with the
+ # shapes produced by the rest of the dataflow pipeline
+ ret = list(self.get_normal_output_shape())
+ ret.insert(-1, 1)
+ return tuple(ret)
+
+ def get_number_output_values(self):
+ folded_oshape = self.get_folded_output_shape()
+ return np.prod(folded_oshape[:-1])
+
+ def get_instream_width(self):
+ dt_bits = self.get_input_datatype().bitwidth()
+ ifm_ch = self.get_nodeattr("NumChannels")
+ in_width = int(dt_bits * ifm_ch)
+ return in_width
+
+ def get_outstream_width(self):
+ """For streaming maxpool out stream with is the same as in stream width"""
+ return self.get_instream_width()
+
+ def make_shape_compatible_op(self, model):
+ exp_ishape = self.get_normal_input_shape()
+ oshape = self.get_normal_output_shape()
+ ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0]))
+ assert ishape == exp_ishape, "Unexpect input shape for StreamingMaxPool."
+ # implement tensor with correct shape
+ values = np.random.randn(*oshape).astype(np.float32)
+ return helper.make_node(
+ "Constant",
+ inputs=[],
+ outputs=[self.onnx_node.output[0]],
+ value=helper.make_tensor(
+ name="const_tensor",
+ data_type=TensorProto.FLOAT,
+ dims=values.shape,
+ vals=values.flatten().astype(float),
+ ),
+ )
def infer_node_datatype(self, model):
- pass
+ node = self.onnx_node
+ # data type stays the same
+ dtype = model.get_tensor_datatype(node.input[0])
+ model.set_tensor_datatype(node.output[0], dtype)
def verify_node(self):
info_messages = []
- # verify number of attributes
- num_of_attr = 6
- if len(self.onnx_node.attribute) == num_of_attr:
- info_messages.append("The number of attributes is correct")
- else:
- info_messages.append(
- """The number of attributes is incorrect,
- {} should have {} attributes""".format(
- self.onnx_node.op_type, num_of_attr
- )
- )
-
# verify that "domain" is set to "finn"
domain_value = self.onnx_node.domain
if domain_value == "finn":
@@ -76,21 +147,6 @@ class StreamingMaxPool_Batch(HLSCustomOp):
else:
info_messages.append('Attribute backend should be set to "fpgadataflow"')
- # verify that all necessary attributes exist
- try:
- self.get_nodeattr("code_gen_dir_npysim")
- self.get_nodeattr("executable_path")
- self.get_nodeattr("ImgDim")
- self.get_nodeattr("PoolDim")
- self.get_nodeattr("NumChannels")
- info_messages.append("All necessary attributes exist")
- except Exception:
- info_messages.append(
- """The necessary attributes do not exist.
- StreamingMaxPool_Batch needs the following attributes:
- code_gen_dir_npysim, executable_path, ImgDim, PoolDim, NumChannels"""
- )
-
# verify the number of inputs
if len(self.onnx_node.input) == 1:
info_messages.append("The number of inputs is correct")
@@ -99,15 +155,6 @@ class StreamingMaxPool_Batch(HLSCustomOp):
return info_messages
- def get_number_output_values(self):
- pass
-
- def bram_estimation(self):
- pass
-
- def lut_estimation(self):
- pass
-
def global_includes(self):
self.code_gen_dict["$GLOBALS$"] = ['#include "maxpool.h"']
@@ -124,121 +171,175 @@ class StreamingMaxPool_Batch(HLSCustomOp):
]
def read_npy_data(self):
- node = self.onnx_node
code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
- # c++ code to read out an npy file
- # and put it in hls::stream in the correct order
+ dtype = self.get_input_datatype()
+ if dtype == DataType.BIPOLAR:
+ # use binary for bipolar storage
+ dtype = DataType.BINARY
+ elem_bits = dtype.bitwidth()
+ packed_bits = self.get_instream_width()
+ packed_hls_type = "ap_uint<%d>" % packed_bits
+ elem_hls_type = dtype.get_hls_datatype_str()
+ npy_type = "float"
+ npy_in = "%s/input_0.npy" % code_gen_dir
self.code_gen_dict["$READNPYDATA$"] = []
- input_ind = 0
- input_file_names = []
- for inputs in node.input:
- input_file_names.append("{}/input_{}.npy".format(code_gen_dir, input_ind))
- input_ind += 1
-
- input_ind = 0
- for input_file in input_file_names:
- self.code_gen_dict["$READNPYDATA$"].append(
- """cnpy::NpyArray arr = cnpy::npy_load("{}");\n
- float* loaded_data{} = arr.data<float>();""".format(
- input_file, input_ind
- )
- )
- self.code_gen_dict["$READNPYDATA$"].append(
- """int num_values = 1; \n
- for(int i = 0; i < arr.shape.size(); i++){\n
- num_values *= arr.shape[i]; \n }"""
- )
- self.code_gen_dict["$READNPYDATA$"].append(
- "ap_uint<{}> dat;".format(self.get_nodeattr("NumChannels"))
- )
- self.code_gen_dict["$READNPYDATA$"].append(
- "for(int i=0; i < num_values/{}; i++){{".format(
- self.get_nodeattr("NumChannels")
- )
- )
- for channel in range(self.get_nodeattr("NumChannels")):
- self.code_gen_dict["$READNPYDATA$"].append(
- "dat.range({},{}) = loaded_data{}[i+((num_values/{})*{})];".format(
- channel,
- channel,
- input_ind,
- self.get_nodeattr("NumChannels"),
- channel,
- )
- )
- self.code_gen_dict["$READNPYDATA$"].append("in{} << dat;".format(input_ind))
- self.code_gen_dict["$READNPYDATA$"].append("}")
- input_ind += 1
+ self.code_gen_dict["$READNPYDATA$"].append(
+ 'npy2apintstream<%s, %s, %d, %s>("%s", in0);'
+ % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)
+ )
def strm_decl(self):
- node = self.onnx_node
self.code_gen_dict["$STREAMDECLARATIONS$"] = []
- input_ind = 0
- for inputs in node.input:
- self.code_gen_dict["$STREAMDECLARATIONS$"].append(
- 'hls::stream<ap_uint<{}>> in{} ("in{}");'.format(
- self.get_nodeattr("NumChannels"), input_ind, input_ind
- )
- )
- input_ind += 1
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
- 'hls::stream<ap_uint<{}>> out ("out");'.format(
- self.get_nodeattr("NumChannels")
- )
+ 'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_instream_width())
+ )
+ self.code_gen_dict["$STREAMDECLARATIONS$"].append(
+ 'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_outstream_width())
)
def docompute(self):
- node = self.onnx_node
- self.code_gen_dict["$DOCOMPUTE$"] = [
- "{}<ImgDim, PoolDim, NumChannels>(in0, out, numReps);".format(node.op_type)
- ]
+ dtype = self.get_input_datatype()
+ if dtype.bitwidth() == 1:
+ op = "StreamingMaxPool_Batch"
+ self.code_gen_dict["$DOCOMPUTE$"] = [
+ "%s<ImgDim, PoolDim, NumChannels>(in0, out, numReps);" % (op)
+ ]
+ else:
+ op = "StreamingMaxPool_Precision_Batch"
+ dtype = self.get_input_datatype()
+ dtype_hls = dtype.get_hls_datatype_str()
+ minval_str = str(int(dtype.min()))
+ self.code_gen_dict["$DOCOMPUTE$"] = [
+ "%s<ImgDim, PoolDim, NumChannels, %s, %s>(in0, out, numReps);"
+ % (op, dtype_hls, minval_str)
+ ]
def dataoutstrm(self):
+ code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
+ dtype = self.get_output_datatype()
+ if dtype == DataType.BIPOLAR:
+ # use binary for bipolar storage
+ dtype = DataType.BINARY
+ elem_bits = dtype.bitwidth()
+ packed_bits = self.get_outstream_width()
+ packed_hls_type = "ap_uint<%d>" % packed_bits
+ elem_hls_type = dtype.get_hls_datatype_str()
+ npy_type = "float"
+ npy_out = "%s/output.npy" % code_gen_dir
+ oshape = self.get_folded_output_shape()
+ oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}")
+
self.code_gen_dict["$DATAOUTSTREAM$"] = [
- "ap_uint<{}> out_data;\n std::vector<ap_uint<{}>> out_data_vector;".format(
- self.get_nodeattr("NumChannels"), self.get_nodeattr("NumChannels")
+ 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");'
+ % (
+ packed_hls_type,
+ elem_hls_type,
+ elem_bits,
+ npy_type,
+ oshape_cpp_str,
+ npy_out,
)
]
- self.code_gen_dict["$DATAOUTSTREAM$"].append("while(out.read_nb(out_data)){")
- self.code_gen_dict["$DATAOUTSTREAM$"].append(
- "out_data_vector.push_back(out_data);\n}"
- )
- self.code_gen_dict["$DATAOUTSTREAM$"].append(
- "std::vector<float> output_data_vector;"
- )
- self.code_gen_dict["$DATAOUTSTREAM$"].append(
- """for(std::vector<ap_uint<{}>>::iterator it = out_data_vector.begin();
- it != out_data_vector.end(); ++it){{""".format(
- self.get_nodeattr("NumChannels")
- )
- )
- self.code_gen_dict["$DATAOUTSTREAM$"].append(
- "ap_uint<{}> output_data = *it;".format(self.get_nodeattr("NumChannels"))
- )
- for channel in range(self.get_nodeattr("NumChannels")):
- self.code_gen_dict["$DATAOUTSTREAM$"].append(
- "output_data_vector.push_back(output_data.range({},{}));".format(
- channel, channel
- )
- )
- self.code_gen_dict["$DATAOUTSTREAM$"].append("}")
def save_as_npy(self):
- code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
- numReps = 1
- self.code_gen_dict["$SAVEASCNPY$"] = [
- """cnpy::npy_save("{}/output.npy",&output_data_vector[0],
- {{{},{},{}}},"w");""".format(
- code_gen_dir,
- numReps,
- self.get_nodeattr("NumChannels"),
- int(self.get_nodeattr("ImgDim") / self.get_nodeattr("PoolDim")),
- int(self.get_nodeattr("ImgDim") / self.get_nodeattr("PoolDim")),
- )
- ]
+ self.code_gen_dict["$SAVEASCNPY$"] = []
def blackboxfunction(self):
- pass
+ packed_bits = self.get_instream_width()
+ packed_hls_type = "ap_uint<%d>" % packed_bits
+ self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
+ "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)"
+ % (self.onnx_node.name, packed_hls_type, packed_hls_type)
+ ]
def pragmas(self):
- pass
+ self.code_gen_dict["$PRAGMAS$"] = ["#pragma HLS INTERFACE axis port=in0"]
+ self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE axis port=out")
+ self.code_gen_dict["$PRAGMAS$"].append(
+ "#pragma HLS INTERFACE ap_ctrl_none port=return"
+ )
+
+ def execute_node(self, context, graph):
+ mode = self.get_nodeattr("exec_mode")
+ node = self.onnx_node
+ exp_ishape = self.get_normal_input_shape()
+ exp_oshape = self.get_normal_output_shape()
+ folded_oshape = self.get_folded_output_shape()
+
+ # TODO ensure codegen dir exists
+ if mode == "npysim":
+ code_gen_dir = self.get_nodeattr("code_gen_dir_npysim")
+ elif mode == "rtlsim":
+ code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+ else:
+ raise Exception(
+ """Invalid value for attribute exec_mode! Is currently set to: {}
+ has to be set to one of the following value ("npysim", "rtlsim")""".format(
+ mode
+ )
+ )
+
+ inp = context[node.input[0]]
+ assert str(inp.dtype) == "float32", "Input datatype is not float32"
+ assert (
+ inp.shape == exp_ishape
+ ), """Input shape doesn't
+ match expected shape (1, ifm_dim, ifm_dim, ifm_ch)."""
+ if self.get_input_datatype() == DataType.BIPOLAR:
+ # store bipolar activations as binary
+ inp = (inp + 1) / 2
+ export_idt = DataType.BINARY
+ else:
+ export_idt = self.get_input_datatype()
+ # no reshaping for input since assuming no folding on input
+ # make copy before saving array
+ reshaped_input = inp.copy()
+ np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input)
+
+ if mode == "npysim":
+ # execute the precompiled model
+ super().exec_precompiled_singlenode_model()
+ # load output npy file
+ super().npy_to_dynamic_output(context)
+ assert (
+ context[node.output[0]].shape == folded_oshape
+ ), "npysim \
+ did not produce expected ofolded utput shape"
+ context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape)
+ elif mode == "rtlsim":
+ sim = self.get_rtlsim()
+ nbits = self.get_instream_width()
+ rtlsim_inp = npy_to_rtlsim_input(
+ "{}/input_0.npy".format(code_gen_dir), export_idt, nbits
+ )
+ super().reset_rtlsim(sim)
+ super().toggle_clk(sim)
+ rtlsim_output = self.rtlsim(sim, rtlsim_inp)
+ odt = export_idt
+ target_bits = odt.bitwidth()
+ packed_bits = self.get_outstream_width()
+ out_npy_path = "{}/output.npy".format(code_gen_dir)
+ out_shape = self.get_folded_output_shape()
+ rtlsim_output_to_npy(
+ rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits
+ )
+ # load and reshape output
+ output = np.load(out_npy_path)
+ output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape)
+ context[node.output[0]] = output
+ else:
+ raise Exception(
+ """Invalid value for attribute exec_mode! Is currently set to: {}
+ has to be set to one of the following value ("npysim", "rtlsim")""".format(
+ mode
+ )
+ )
+ # binary -> bipolar if needed
+ if self.get_output_datatype() == DataType.BIPOLAR:
+ out = context[node.output[0]]
+ out = 2 * out - 1
+ context[node.output[0]] = out
+ assert (
+ context[node.output[0]].shape == exp_oshape
+ ), """Output
+ shape doesn't match expected shape (1, ofm_dim, ofm_dim, k*k*ifm_ch)."""
diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py
index bad2ba2eff8ebba8e1a16f5e6e1174b3348c1e56..5f526aa2aa1917144c7a048c9d9314aa9288a2d8 100644
--- a/src/finn/custom_op/fpgadataflow/templates.py
+++ b/src/finn/custom_op/fpgadataflow/templates.py
@@ -1,3 +1,4 @@
+# flake8: noqa
# Copyright (c) 2020, Xilinx
# All rights reserved.
#
@@ -28,11 +29,12 @@
# template for single node execution
docompute_template = """
-#define AP_INT_MAX_W 4096
+#define AP_INT_MAX_W $AP_INT_MAX_W$
#include "cnpy.h"
#include "npy2apintstream.hpp"
#include <vector>
#include "bnn-library.h"
+
// includes for network parameters
$GLOBALS$
@@ -40,6 +42,7 @@ $GLOBALS$
$DEFINES$
int main(){
+$PRAGMAS$
$STREAMDECLARATIONS$
@@ -59,8 +62,10 @@ $SAVEASCNPY$
# cpp file
ipgen_template = """
-#define AP_INT_MAX_W 4096
+#define AP_INT_MAX_W $AP_INT_MAX_W$
+
#include "bnn-library.h"
+
// includes for network parameters
$GLOBALS$
@@ -74,7 +79,7 @@ $DOCOMPUTE$
}
"""
-# tcl script
+# tcl script for IP generation
ipgentcl_template = """
set config_proj_name $PROJECTNAME$
puts "HLS project: $config_proj_name"
@@ -96,9 +101,345 @@ set_part $config_proj_part
config_interface -m_axi_addr64
config_rtl -auto_prefix
+$EXTRA_DIRECTIVES$
create_clock -period $config_clkperiod -name default
csynth_design
export_design -format ip_catalog
exit 0
"""
+
+# verilog wrapper for decoupled mem mode
+decoupled_wrapper = """
+module $TOPNAME$(
+ap_clk,
+ap_rst_n,
+in0_V_V_TDATA,
+in0_V_V_TVALID,
+in0_V_V_TREADY,
+out_V_V_TDATA,
+out_V_V_TVALID,
+out_V_V_TREADY
+);
+
+input ap_clk;
+input ap_rst_n;
+input $IN_RANGE$ in0_V_V_TDATA;
+input in0_V_V_TVALID;
+output in0_V_V_TREADY;
+output $OUT_RANGE$ out_V_V_TDATA;
+output out_V_V_TVALID;
+input out_V_V_TREADY;
+
+reg [31:0] config_address = 0;
+reg config_ce = 0;
+reg config_we = 0;
+reg [31:0] config_d0 = 0;
+wire [31:0] config_q0;
+
+//multiple wire AXI Streams
+wire m_axis_0_afull;
+// FIFO count to generate programmable full
+wire [5:0] fifo_0_count;
+wire m_axis_0_tready;
+wire m_axis_0_tvalid;
+wire $WEIGHT_RANGE$ m_axis_0_tdata;
+
+wire m_axis_0_tready_q;
+wire m_axis_0_tvalid_q;
+wire $WEIGHT_RANGE$ m_axis_0_tdata_q;
+
+wire m_axis_0_tready_q2;
+wire m_axis_0_tvalid_q2;
+wire $WEIGHT_RANGE$ m_axis_0_tdata_q2;
+
+reg m_axis_1_afull = 0;
+reg m_axis_1_tready = 1;
+wire m_axis_1_tvalid;
+wire $WEIGHT_RANGE$ m_axis_1_tdata;
+
+reg m_axis_2_afull = 0;
+reg m_axis_2_tready = 1;
+wire m_axis_2_tvalid;
+wire $WEIGHT_RANGE$ m_axis_2_tdata;
+
+reg m_axis_3_afull = 0;
+reg m_axis_3_tready = 1;
+wire m_axis_3_tvalid;
+wire $WEIGHT_RANGE$ m_axis_3_tdata;
+
+reg m_axis_4_afull = 0;
+reg m_axis_4_tready = 1;
+wire m_axis_4_tvalid;
+wire $WEIGHT_RANGE$ m_axis_4_tdata;
+
+reg m_axis_5_afull = 0;
+reg m_axis_5_tready = 1;
+wire m_axis_5_tvalid;
+wire $WEIGHT_RANGE$ m_axis_5_tdata;
+
+//memstream component
+
+memstream
+#(
+//parameters to enable/disable axi-mm, set number of streams, set readmemh for
+// memory, set per-stream offsets in memory, set per-stream widths
+.CONFIG_EN(1),
+.NSTREAMS(1),
+.MEM_DEPTH($MEM_DEPTH$),
+.MEM_WIDTH($WEIGHT_WIDTH$),
+.MEM_INIT("./"),
+.RAM_STYLE("$RAM_STYLE$"),
+
+//widths per stream
+.STRM0_WIDTH($WEIGHT_WIDTH$),
+.STRM1_WIDTH($WEIGHT_WIDTH$),
+.STRM2_WIDTH($WEIGHT_WIDTH$),
+.STRM3_WIDTH($WEIGHT_WIDTH$),
+.STRM4_WIDTH($WEIGHT_WIDTH$),
+.STRM5_WIDTH($WEIGHT_WIDTH$),
+
+//depths per stream
+.STRM0_DEPTH($WSTREAM_DEPTH$),
+.STRM1_DEPTH(1),
+.STRM2_DEPTH(1),
+.STRM3_DEPTH(1),
+.STRM4_DEPTH(1),
+.STRM5_DEPTH(1),
+
+//offsets for each stream
+.STRM0_OFFSET(0),
+.STRM1_OFFSET(0),
+.STRM2_OFFSET(0),
+.STRM3_OFFSET(0),
+.STRM4_OFFSET(0),
+.STRM5_OFFSET(0)
+)
+mem
+(
+.aclk(ap_clk),
+.aresetn(ap_rst_n),
+
+//optional configuration interface compatible with ap_memory
+.config_address(config_address),
+.config_ce(config_ce),
+.config_we(config_we),
+.config_d0(config_d0),
+.config_q0(config_q0),
+
+//multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
+.m_axis_0_afull(m_axis_0_afull),
+.m_axis_0_tready(m_axis_0_tready),
+.m_axis_0_tvalid(m_axis_0_tvalid),
+.m_axis_0_tdata(m_axis_0_tdata),
+
+.m_axis_1_afull(m_axis_1_afull),
+.m_axis_1_tready(m_axis_1_tready),
+.m_axis_1_tvalid(m_axis_1_tvalid),
+.m_axis_1_tdata(m_axis_1_tdata),
+
+.m_axis_2_afull(m_axis_2_afull),
+.m_axis_2_tready(m_axis_2_tready),
+.m_axis_2_tvalid(m_axis_2_tvalid),
+.m_axis_2_tdata(m_axis_2_tdata),
+
+.m_axis_3_afull(m_axis_3_afull),
+.m_axis_3_tready(m_axis_3_tready),
+.m_axis_3_tvalid(m_axis_3_tvalid),
+.m_axis_3_tdata(m_axis_3_tdata),
+
+.m_axis_4_afull(m_axis_4_afull),
+.m_axis_4_tready(m_axis_4_tready),
+.m_axis_4_tvalid(m_axis_4_tvalid),
+.m_axis_4_tdata(m_axis_4_tdata),
+
+.m_axis_5_afull(m_axis_5_afull),
+.m_axis_5_tready(m_axis_5_tready),
+.m_axis_5_tvalid(m_axis_5_tvalid),
+.m_axis_5_tdata(m_axis_5_tdata)
+
+
+);
+
+
+Q_srl #(
+.depth(32),
+.width($WEIGHT_WIDTH$)
+)
+$LAYER_NAME$_w_fifo_1
+(
+ .clock(ap_clk),
+ .reset(!ap_rst_n),
+ .i_d(m_axis_0_tdata),
+ .i_v(m_axis_0_tvalid),
+ .i_r(m_axis_0_tready),
+ .o_d(m_axis_0_tdata_q),
+ .o_v(m_axis_0_tvalid_q),
+ .o_r(m_axis_0_tready_q),
+ .count(fifo_0_count)
+);
+
+
+//MVA_Stream_Unit
+
+$LAYER_NAME$
+MVA_Stream_U
+(
+.ap_clk(ap_clk), //input
+.ap_rst_n(ap_rst_n), //input
+.in0_V_V_TDATA(in0_V_V_TDATA), //$IN_RANGE$ input
+.in0_V_V_TVALID(in0_V_V_TVALID), //input
+.in0_V_V_TREADY(in0_V_V_TREADY), //output
+.weights_V_V_TDATA(m_axis_0_tdata_q), //$WEIGHT_RANGE$ input
+.weights_V_V_TVALID(m_axis_0_tvalid_q), //input
+.weights_V_V_TREADY(m_axis_0_tready_q), //output
+.out_V_V_TDATA(out_V_V_TDATA), //$OUT_RANGE$ output
+.out_V_V_TVALID(out_V_V_TVALID), //output
+.out_V_V_TREADY(out_V_V_TREADY) //input
+);
+
+// programmable full threshold at 16 elements
+assign m_axis_0_afull = (fifo_0_count > 16);
+
+endmodule
+"""
+
+ip_package_tcl = """
+## IP Info
+set Vendor "xilinx.com"
+set Library "hls"
+set IPName "$TOPNAME$"
+set Version "1.0"
+set DisplayName "$TOPNAME$"
+set Description "An IP generated by Xilinx FINN"
+set Device "zynq"
+set Catalog "/UserIP"
+set RootDir "$VERILOG_DIR$"
+
+## Variables
+set Top "$TOPNAME$"
+set VerilogFiles [glob -nocomplain $RootDir/*]
+
+
+## Enter IP directory
+cd [file dir [info script]]
+
+## Generate sub cores
+set IPs ""
+set IPFiles ""
+
+## Basic info
+set core [ipx::create_core $Vendor $Library $IPName $Version]
+set_property display_name $DisplayName $core
+set_property description $Description $core
+set_property taxonomy $Catalog $core
+set_property supported_families { \
+ artix7 Production \
+ artix7l Production \
+ kintex7 Production \
+ kintex7l Production \
+ kintexu Production \
+ kintexuplus Production \
+ virtex7 Production \
+ virtexu Production \
+ virtexuplus Production \
+ zynq Production \
+ zynquplus Production \
+ aartix7 Production \
+ azynq Production \
+ qartix7 Production \
+ qkintex7 Production \
+ qkintex7l Production \
+ qvirtex7 Production \
+ qzynq Production \
+} $core;
+
+## Add verilog files
+if {[llength $VerilogFiles] > 0} {
+ # synthesis
+ set group [ipx::add_file_group xilinx_verilogsynthesis $core]
+ foreach f [concat $VerilogFiles $IPFiles] {
+ set current_file [ipx::add_file $f $group]
+ if {[file ext $f] == ".dat"} {
+ set_property type "mif" $current_file
+ }
+ }
+ set_property model_name $Top $group
+ if {$IPs != ""} {
+ set_property component_subcores $IPs $group
+ }
+
+ # simulation
+ set group [ipx::add_file_group xilinx_verilogbehavioralsimulation $core]
+ foreach f [concat $VerilogFiles $IPFiles] {
+ set current_file [ipx::add_file $f $group]
+ if {[file ext $f] == ".dat"} {
+ set_property type "mif" $current_file
+ }
+ }
+ set_property model_name $Top $group
+ if {$IPs != ""} {
+ set_property component_subcores $IPs $group
+ }
+}
+
+## Import ports
+ipx::add_ports_from_hdl \
+ -top_level_hdl_file $RootDir/$Top.v \
+ -top_module_name $Top \
+ $core
+
+## Infer interfaces
+ipx::infer_bus_interface ap_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface ap_rst_n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface {in0_V_V_TDATA in0_V_V_TVALID in0_V_V_TREADY} xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface {out_V_V_TREADY out_V_V_TDATA out_V_V_TVALID} xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
+ipx::associate_bus_interfaces -busif in0_V_V -clock ap_clk [ipx::current_core]
+ipx::associate_bus_interfaces -busif out_V_V -clock ap_clk [ipx::current_core]
+
+## Finalize
+set_property core_revision 2 [ipx::current_core]
+ipx::create_xgui_files [ipx::current_core]
+ipx::update_checksums [ipx::current_core]
+ipx::save_core [ipx::current_core]
+"""
+
+strm_fifo_wrapper = """
+module $TOPNAME$(
+ap_clk,
+ap_rst_n,
+in0_V_V_TDATA,
+in0_V_V_TVALID,
+in0_V_V_TREADY,
+out_V_V_TDATA,
+out_V_V_TVALID,
+out_V_V_TREADY
+);
+
+input ap_clk;
+input ap_rst_n;
+input $IN_RANGE$ in0_V_V_TDATA;
+input in0_V_V_TVALID;
+output in0_V_V_TREADY;
+output $OUT_RANGE$ out_V_V_TDATA;
+output out_V_V_TVALID;
+input out_V_V_TREADY;
+
+Q_srl #(
+.depth($DEPTH$),
+.width($WIDTH$)
+)
+$LAYER_NAME$
+(
+ .clock(ap_clk),
+ .reset(!ap_rst_n),
+ .i_d(in0_V_V_TDATA),
+ .i_v(in0_V_V_TVALID),
+ .i_r(in0_V_V_TREADY),
+ .o_d(out_V_V_TDATA),
+ .o_v(out_V_V_TVALID),
+ .o_r(out_V_V_TREADY)
+);
+
+endmodule
+"""
diff --git a/src/finn/custom_op/fpgadataflow/tlastmarker.py b/src/finn/custom_op/fpgadataflow/tlastmarker.py
index c0f599958affc9a3530431506a886919bc3117f1..25ea05e3607a52731ae1b64de421837bf137ee2b 100644
--- a/src/finn/custom_op/fpgadataflow/tlastmarker.py
+++ b/src/finn/custom_op/fpgadataflow/tlastmarker.py
@@ -59,7 +59,7 @@ class TLastMarker(HLSCustomOp):
i_tensor = context[i_name]
context[o_name] = i_tensor
- def make_shape_compatible_op(self):
+ def make_shape_compatible_op(self, model):
# not supported for shape inference
pass
@@ -82,7 +82,7 @@ class TLastMarker(HLSCustomOp):
self.code_gen_dict["$DEFINES$"] = [
"#define StreamWidth %d" % stream_width,
"#define OutDType %s" % out_stream_dtype,
- "#define NumIters %d" % self.get_nodeattr("NumIters"),
+ "#define NumItersPerImg %d" % self.get_nodeattr("NumIters"),
]
def read_npy_data(self):
@@ -90,12 +90,23 @@ class TLastMarker(HLSCustomOp):
def docompute(self):
self.code_gen_dict["$DOCOMPUTE$"] = [
- "for(int i=0; i<NumIters; i++) {",
- "#pragma HLS PIPELINE II=1",
+ "unsigned int n = 1;",
"OutDType t;",
- "t.set_data(in0.read());",
"t.set_keep(-1);",
- "t.set_last(i==(NumIters-1));",
+ "io_section: { // start of cycle accurate region",
+ "#pragma HLS protocol fixed",
+ "// do a first read from stream before we decide on numIters",
+ "// giving software a chance to set up the numIters prior to startup",
+ "t.set_data(in0.read());",
+ "n = (numIters == 0 ? NumItersPerImg : numIters);",
+ "t.set_last(n==1);",
+ "out.write(t);",
+ "} // end of cycle accurate region",
+ "// do one less iteration than spec since we already did one",
+ "for(unsigned int i=1; i<n; i++) {",
+ "#pragma HLS PIPELINE II=1",
+ "t.set_data(in0.read());",
+ "t.set_last(i==(n-1));",
"out.write(t);",
"}",
]
@@ -109,13 +120,16 @@ class TLastMarker(HLSCustomOp):
def blackboxfunction(self):
self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
"""void %s(hls::stream<ap_uint<StreamWidth> > &in0,
- hls::stream<OutDType> &out)"""
+ hls::stream<OutDType> &out, unsigned int numIters)"""
% self.onnx_node.name
]
def pragmas(self):
self.code_gen_dict["$PRAGMAS$"] = ["#pragma HLS INTERFACE axis port=in0"]
self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE axis port=out")
+ self.code_gen_dict["$PRAGMAS$"].append(
+ "#pragma HLS INTERFACE s_axilite port=numIters bundle=control"
+ )
self.code_gen_dict["$PRAGMAS$"].append(
"#pragma HLS INTERFACE ap_ctrl_none port=return"
)
diff --git a/src/finn/custom_op/im2col.py b/src/finn/custom_op/im2col.py
new file mode 100644
index 0000000000000000000000000000000000000000..2bd039c3acbcb3dfa99b478b012a4e89d5399f45
--- /dev/null
+++ b/src/finn/custom_op/im2col.py
@@ -0,0 +1,197 @@
+import numpy as np
+from onnx import TensorProto, helper
+
+from finn.custom_op import CustomOp
+import finn.util.basic as util
+from finn.core.datatype import DataType
+
+# adapted from A. Karpathy's CS231 im2col code
+# utilities to generate a patch matrix from a multichannel image
+# of shape (batches, channels, height, width)
+
+
+def compute_conv_output_dim(ifm_dim, k, stride, pad=0):
+ "Return spatial output dimension size for convolution with given params."
+ return int(((ifm_dim + 2 * pad - k) / stride) + 1)
+
+
+def get_im2col_indices_nchw(
+ x_shape, field_height, field_width, padding=0, stride_y=1, stride_x=1
+):
+ # First figure out what the size of the output should be
+ N, C, H, W = x_shape
+ assert (H + 2 * padding - field_height) % stride_y == 0
+ assert (W + 2 * padding - field_width) % stride_x == 0
+ out_height = compute_conv_output_dim(H, field_height, stride_y, padding)
+ out_width = compute_conv_output_dim(W, field_width, stride_x, padding)
+
+ i0 = np.repeat(np.arange(field_height), field_width)
+ i0 = np.tile(i0, C)
+ i1 = stride_y * np.repeat(np.arange(out_height), out_width)
+ j0 = np.tile(np.arange(field_width), field_height * C)
+ j1 = stride_x * np.tile(np.arange(out_width), out_height)
+ i = i0.reshape(-1, 1) + i1.reshape(1, -1)
+ j = j0.reshape(-1, 1) + j1.reshape(1, -1)
+
+ k = np.repeat(np.arange(C), field_height * field_width).reshape(-1, 1)
+
+ return (k, i, j)
+
+
+def im2col_indices_nchw(
+ x, field_height, field_width, padding=0, stride_y=1, stride_x=1, pad_val=0
+):
+ """ An implementation of im2col based on some fancy indexing """
+ # Zero-pad the input
+ p = padding
+ x_padded = np.pad(
+ x, ((0, 0), (0, 0), (p, p), (p, p)), mode="constant", constant_values=pad_val
+ )
+
+ k, i, j = get_im2col_indices_nchw(
+ x.shape, field_height, field_width, padding, stride_y, stride_x
+ )
+
+ cols = x_padded[:, k, i, j]
+ C = x.shape[1]
+ cols = cols.transpose(1, 2, 0).reshape(field_height * field_width * C, -1)
+ return cols
+
+
+# ONNX i/o tensor shape assumptions for Im2Col:
+# input 0 is the input vector, shape (1, ih, iw, ifm)
+# output 0 is the output vector, shape (1, oh, ow, k*k*ifm)
+# where:
+# * ih, iw are the height and width of the input image
+# * oh, ow are the height and width of the output (lowered) image
+# * ifm is the number of input channels
+# * k is the convolutional kernel size
+
+
+class Im2Col(CustomOp):
+ def get_nodeattr_types(self):
+ return {
+ "stride": ("i", True, 1),
+ "kernel_size": ("i", True, 1),
+ "input_shape": ("s", True, ""),
+ "pad_amount": ("i", False, 0),
+ "pad_value": ("i", False, 0),
+ }
+
+ def make_shape_compatible_op(self, model):
+ k = self.get_nodeattr("kernel_size")
+ stride = self.get_nodeattr("stride")
+ ishape = self.get_nodeattr("input_shape")
+ pad = self.get_nodeattr("pad_amount")
+
+ # convert string into list of integers
+ ishape = ishape.strip("(")
+ ishape = ishape.strip(")")
+ ishape = ishape.split(",")
+ for i in range(0, len(ishape)):
+ ishape[i] = int(ishape[i])
+
+ # extract all necessary information and determine output dimensions
+ ifm_ch = ishape[-1]
+ assert len(ishape) == 4, "Unexpected input shape for Im2Col"
+ assert ishape[1] == ishape[2], "Im2Col for non-square images unsupported"
+ ifm_dim = ishape[1]
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad)
+
+ # implement tensor with correct shape
+ values = np.random.randn(1, ofm_dim, ofm_dim, k * k * ifm_ch).astype(np.float32)
+ return helper.make_node(
+ "Constant",
+ inputs=[],
+ outputs=[self.onnx_node.output[0]],
+ value=helper.make_tensor(
+ name="const_tensor",
+ data_type=TensorProto.FLOAT,
+ dims=values.shape,
+ vals=values.flatten().astype(float),
+ ),
+ )
+
+ def infer_node_datatype(self, model):
+ node = self.onnx_node
+ # data type stays the same
+ dtype = model.get_tensor_datatype(node.input[0])
+ model.set_tensor_datatype(node.output[0], dtype)
+
+ def execute_node(self, context, graph):
+ node = self.onnx_node
+ k = self.get_nodeattr("kernel_size")
+ stride = self.get_nodeattr("stride")
+ pad = self.get_nodeattr("pad_amount")
+ pad_val = self.get_nodeattr("pad_value")
+ iname = node.input[0]
+ x = context[iname]
+ qnt_annotations = graph.quantization_annotation
+ ret = util.get_by_name(qnt_annotations, iname, "tensor_name")
+ ret = util.get_by_name(ret.quant_parameter_tensor_names, "finn_datatype", "key")
+ idt = DataType[ret.value]
+ if pad != 0:
+ assert idt.allowed(pad_val), "Im2Col dtype must allow pad_val"
+ # check that input is NHWC
+ assert x.ndim == 4, "Unexpected number of input dims for Im2Col"
+ N, H, W, C = x.shape
+ assert H == W, "Unexpected input shape for Im2Col"
+ out_dim = compute_conv_output_dim(H, k, stride, pad)
+ # internally convert input to NCHW
+ x = x.transpose(0, 3, 1, 2)
+ # call NCHW im2col implementation
+ ret = im2col_indices_nchw(x, k, k, pad, stride, stride, pad_val=pad_val)
+ # result shape is (k*k*N, out_dim*out_dim), convert to NCHW
+ ret = ret.reshape(N, C, k, k, out_dim, out_dim)
+ # (N=0,C=1,kh=2,kw=3,H=4,W=5) -> (N=0,H=4,W=5,kh=2,kw=3,C=1)
+ ret = ret.transpose(0, 4, 5, 2, 3, 1)
+ ret = ret.reshape(N, out_dim, out_dim, k * k * C)
+
+ # ret = ret.reshape(N, k * k * C, out_dim, out_dim)
+ # convert output back to NHWC
+ # ret = ret.transpose(0, 2, 3, 1)
+ context[node.output[0]] = ret
+
+ def verify_node(self):
+ node = self.onnx_node
+
+ info_messages = []
+
+ # verify number of attributes
+ num_of_attr = 3
+ if len(node.attribute) == num_of_attr:
+ info_messages.append("The number of attributes is correct")
+ else:
+ info_messages.append(
+ """The number of attributes is incorrect,
+ {} should have {} attributes""".format(
+ node.op_type, num_of_attr
+ )
+ )
+
+ # verify that "domain" is set to "finn"
+ domain_value = node.domain
+ if domain_value == "finn":
+ info_messages.append("Attribute domain is set correctly")
+ else:
+ info_messages.append('Attribute domain should be set to "finn"')
+
+ # verify that all necessary attributes exist
+ try:
+ self.get_nodeattr("stride")
+ self.get_nodeattr("kernel_size")
+ info_messages.append("All necessary attributes exist")
+ except Exception:
+ info_messages.append(
+ """The necessary attributes do not exist.
+ Im2Col needs the following attributes:
+ stride, kernel_size"""
+ )
+
+ # verify the number of inputs
+ if len(node.input) == 1:
+ info_messages.append("The number of inputs is correct")
+ else:
+ info_messages.append("{} needs 1 data input".format(node.op_type))
+
+ return info_messages
diff --git a/src/finn/custom_op/maxpoolnhwc.py b/src/finn/custom_op/maxpoolnhwc.py
new file mode 100644
index 0000000000000000000000000000000000000000..c623e40075e0ed6836dc9494ee5effb4539a46af
--- /dev/null
+++ b/src/finn/custom_op/maxpoolnhwc.py
@@ -0,0 +1,126 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from finn.custom_op import CustomOp
+import numpy as np
+from onnx import helper, TensorProto
+from finn.core.modelwrapper import ModelWrapper
+
+
+def compute_pool_output_dim(ifm_dim, k, stride, pad=0):
+ "Return spatial output dimension size for pooling with given params."
+ return int(((ifm_dim + 2 * pad - k) / stride) + 1)
+
+
+class MaxPoolNHWC(CustomOp):
+ # a MaxPool node, but using the NHWC data layout
+
+ def get_nodeattr_types(self):
+ # no specific attributes for MaxPoolNHWC
+ return {
+ "kernel_shape": ("ints", True, []),
+ "pads": ("ints", True, []),
+ "strides": ("ints", True, []),
+ }
+
+ def make_shape_compatible_op(self, model):
+ node = self.onnx_node
+ iname = node.input[0]
+ ishape = model.get_tensor_shape(iname)
+ kernel_shape = self.get_nodeattr("kernel_shape")
+ pads = self.get_nodeattr("pads")
+ strides = self.get_nodeattr("strides")
+ assert len(kernel_shape) == 2, "Non-2D MaxPoolNHWC not supported"
+ assert pads[0] == pads[2], "Uneven padding not supported"
+ assert pads[1] == pads[3], "Uneven padding not supported"
+ (n, hi, wi, c) = ishape
+ ho = compute_pool_output_dim(hi, kernel_shape[0], strides[0], pads[0])
+ wo = compute_pool_output_dim(wi, kernel_shape[1], strides[1], pads[2])
+ oshape = (n, ho, wo, c)
+ # implement tensor with correct shape
+ values = np.random.randn(*oshape).astype(np.float32)
+ return helper.make_node(
+ "Constant",
+ inputs=[],
+ outputs=[self.onnx_node.output[0]],
+ value=helper.make_tensor(
+ name="const_tensor",
+ data_type=TensorProto.FLOAT,
+ dims=values.shape,
+ vals=values.flatten().astype(float),
+ ),
+ )
+
+ def infer_node_datatype(self, model):
+ node = self.onnx_node
+ # data type stays the same
+ dtype = model.get_tensor_datatype(node.input[0])
+ model.set_tensor_datatype(node.output[0], dtype)
+
+ def execute_node(self, context, graph):
+ node = self.onnx_node
+ inp_name = node.input[0]
+ out_name = node.output[0]
+ inp = context[inp_name]
+ dummy_out = context[out_name]
+ # convert i/o NHWC -> NCHW
+ inp = np.transpose(inp, (0, 3, 1, 2))
+ dummy_out = np.transpose(dummy_out, (0, 3, 1, 2))
+ # execute as regular MaxPool
+ node.domain = ""
+ node.op_type = "MaxPool"
+ inp_vi = helper.make_tensor_value_info(inp_name, TensorProto.FLOAT, inp.shape)
+ out_vi = helper.make_tensor_value_info(
+ out_name, TensorProto.FLOAT, dummy_out.shape
+ )
+ tmp_graph = helper.make_graph(
+ nodes=[node], name="tmp_graph", inputs=[inp_vi], outputs=[out_vi]
+ )
+ tmp_model = helper.make_model(tmp_graph, producer_name="finn")
+ tmp_model = ModelWrapper(tmp_model)
+ new_ctx = {inp_name: inp}
+ from finn.core.onnx_exec import execute_onnx
+
+ ret = execute_onnx(tmp_model, new_ctx)
+ # restore original node props
+ node.domain = "finn"
+ node.op_type = "MaxPoolNHWC"
+ outp = ret[out_name]
+ # convert output NCHW -> NHWC
+ outp = np.transpose(outp, (0, 2, 3, 1))
+ context[out_name] = outp
+
+ def verify_node(self):
+ info_messages = []
+ # verify that "domain" is set to "finn"
+ domain_value = self.onnx_node.domain
+ if domain_value == "finn":
+ info_messages.append("Attribute domain is set correctly")
+ else:
+ info_messages.append('Attribute domain should be set to "finn"')
+ return info_messages
diff --git a/src/finn/custom_op/multithreshold.py b/src/finn/custom_op/multithreshold.py
index 73bdbc4177867350eecf75cef0943b01522e8508..37f8e0950b5fc352c8f9fe005884724f028879a0 100644
--- a/src/finn/custom_op/multithreshold.py
+++ b/src/finn/custom_op/multithreshold.py
@@ -50,7 +50,9 @@ def multithreshold(v, thresholds, out_scale=None, out_bias=None):
or equal to.
The output tensor will be scaled by out_scale and biased by out_bias."""
- # the inputs are expected to be in the shape (N,C,H,W)
+ # the inputs are expected to be in the shape (N,C,H,W) or (N, C)
+ # the MultiThreshold node supports a data_layout attribute that can be set
+ # to 'NHWC' to support (N,H,W,C) data layout mode for in-out as well
# N : Batch size
# C : Number of channels
# H : Heigth of the input images
@@ -104,9 +106,10 @@ class MultiThreshold(CustomOp):
"out_dtype": ("s", True, ""),
"out_scale": ("f", False, 1.0),
"out_bias": ("f", False, 0.0),
+ "data_layout": ("s", False, "NCHW"),
}
- def make_shape_compatible_op(self):
+ def make_shape_compatible_op(self, model):
node = self.onnx_node
return helper.make_node("Relu", [node.input[0]], [node.output[0]])
@@ -123,26 +126,40 @@ class MultiThreshold(CustomOp):
# retrieve attributes if output scaling is used
out_scale = self.get_nodeattr("out_scale")
out_bias = self.get_nodeattr("out_bias")
+ # transpose input if NHWC data layout is chosen
+ data_layout = self.get_nodeattr("data_layout")
+ if data_layout == "NHWC":
+ if v.ndim == 4:
+ # NHWC -> NCHW
+ v = np.transpose(v, (0, 3, 1, 2))
+ elif v.ndim == 2:
+ # no HW dimension means NHWC and NCHW layouts are equivalent
+ pass
+ else:
+ raise Exception(
+ "Unknown data_layout and input ndim"
+ " combination for MultiThreshold."
+ )
# calculate output
output = multithreshold(v, thresholds, out_scale, out_bias)
# setting context according to output
+ if data_layout == "NHWC":
+ if output.ndim == 4:
+ # NCHW -> NHWC
+ output = np.transpose(output, (0, 2, 3, 1))
+ elif output.ndim == 2:
+ # no HW dimension means NHWC and NCHW layouts are equivalent
+ pass
+ else:
+ raise Exception(
+ "Unknown data_layout and output ndim"
+ " combination for MultiThreshold."
+ )
context[node.output[0]] = output
def verify_node(self):
info_messages = []
- # verify number of attributes
- num_of_attr = 3
- if len(self.onnx_node.attribute) == num_of_attr:
- info_messages.append("The number of attributes is correct")
- else:
- info_messages.append(
- """The number of attributes is incorrect,
- {} should have {} attributes""".format(
- self.onnx_node.op_type, num_of_attr
- )
- )
-
# verify that "domain" is set to "finn"
domain_value = self.onnx_node.domain
if domain_value == "finn":
@@ -152,8 +169,6 @@ class MultiThreshold(CustomOp):
# verify that all necessary attributes exist
try:
- self.get_nodeattr("out_scale")
- self.get_nodeattr("out_bias")
self.get_nodeattr("out_dtype")
info_messages.append("All necessary attributes exist")
except Exception:
diff --git a/src/finn/custom_op/registry.py b/src/finn/custom_op/registry.py
index c1a67e083a4cf50323033e8a05defa226d518ef2..411311c2b9def953ee5ac6d03adfafb81704c177 100644
--- a/src/finn/custom_op/registry.py
+++ b/src/finn/custom_op/registry.py
@@ -33,21 +33,31 @@ from finn.custom_op.fpgadataflow.convolutioninputgenerator import (
)
from finn.custom_op.fpgadataflow.streamingfclayer_batch import StreamingFCLayer_Batch
from finn.custom_op.fpgadataflow.streamingmaxpool_batch import StreamingMaxPool_Batch
+from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO
+from finn.custom_op.im2col import Im2Col
from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker
from finn.custom_op.multithreshold import MultiThreshold
from finn.custom_op.streamingdataflowpartition import StreamingDataflowPartition
from finn.custom_op.xnorpopcount import XnorPopcountMatMul
+from finn.custom_op.maxpoolnhwc import MaxPoolNHWC
+from finn.custom_op.fpgadataflow.streamingdatawidthconverter_batch import (
+ StreamingDataWidthConverter_Batch,
+)
# create a mapping of all known CustomOp names and classes
custom_op = {}
custom_op["MultiThreshold"] = MultiThreshold
custom_op["XnorPopcountMatMul"] = XnorPopcountMatMul
+custom_op["Im2Col"] = Im2Col
custom_op["StreamingMaxPool_Batch"] = StreamingMaxPool_Batch
custom_op["StreamingFCLayer_Batch"] = StreamingFCLayer_Batch
custom_op["ConvolutionInputGenerator"] = ConvolutionInputGenerator
custom_op["TLastMarker"] = TLastMarker
custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition
+custom_op["MaxPoolNHWC"] = MaxPoolNHWC
+custom_op["StreamingDataWidthConverter_Batch"] = StreamingDataWidthConverter_Batch
+custom_op["StreamingFIFO"] = StreamingFIFO
def getCustomOp(node):
diff --git a/src/finn/custom_op/streamingdataflowpartition.py b/src/finn/custom_op/streamingdataflowpartition.py
index 586537460f9bf4a10bb581218a745c4a99fba6f6..b63326d676f4ded5ec1dd62f5cc7f02d7acb82ad 100644
--- a/src/finn/custom_op/streamingdataflowpartition.py
+++ b/src/finn/custom_op/streamingdataflowpartition.py
@@ -36,11 +36,9 @@ class StreamingDataflowPartition(CustomOp):
bitfile by itself."""
def get_nodeattr_types(self):
- return {
- "model": ("s", True, ""),
- }
+ return {"model": ("s", True, "")}
- def make_shape_compatible_op(self):
+ def make_shape_compatible_op(self, model):
pass
def infer_node_datatype(self, model):
diff --git a/src/finn/custom_op/xnorpopcount.py b/src/finn/custom_op/xnorpopcount.py
index 511a120b1c3894595dc068995d14862b54a73c7a..199b7a5d9938b662b8f23e30275768b427fd87a7 100644
--- a/src/finn/custom_op/xnorpopcount.py
+++ b/src/finn/custom_op/xnorpopcount.py
@@ -37,8 +37,10 @@ def xnorpopcountmatmul(inp0, inp1):
"""Simulates XNOR-popcount matrix multiplication as a regular bipolar
matrix multiplication followed by some post processing."""
# extract the operand shapes
- (M, K0) = inp0.shape
- (K1, N) = inp1.shape
+ # (M, K0) = inp0.shape
+ # (K1, N) = inp1.shape
+ K0 = inp0.shape[-1]
+ K1 = inp1.shape[0]
# make sure shapes are compatible with matmul
assert K0 == K1, "Matrix shapes are not compatible with matmul."
K = K0
@@ -65,7 +67,7 @@ class XnorPopcountMatMul(CustomOp):
def get_nodeattr_types(self):
return {}
- def make_shape_compatible_op(self):
+ def make_shape_compatible_op(self, model):
node = self.onnx_node
return helper.make_node(
"MatMul", [node.input[0], node.input[1]], [node.output[0]]
diff --git a/src/finn/data/cpp/npy2apintstream.hpp b/src/finn/data/cpp/npy2apintstream.hpp
index b1c563d1bc33bbcd1a17f49fdc644be16f5f9730..f3afbc5bfb16e2423184e334e78b96a8cdeef45c 100644
--- a/src/finn/data/cpp/npy2apintstream.hpp
+++ b/src/finn/data/cpp/npy2apintstream.hpp
@@ -13,54 +13,58 @@
#endif
template <typename PackedT, typename ElemT, int ElemBits, typename NpyT>
-void npy2apintstream(const char * npy_path, hls::stream<PackedT> & out_stream, bool reverse_inner = true) {
- cnpy::NpyArray arr = cnpy::npy_load(npy_path);
- DEBUG_NPY2APINTSTREAM("word_size " << arr.word_size << " num_vals " << arr.num_vals)
- if(arr.word_size != sizeof(NpyT)) {
- throw "Npy array word size and specified NpyT size do not match";
- }
- NpyT* loaded_data = arr.data<NpyT>();
- size_t outer_dim_elems = 1;
- for(size_t dim = 0; dim < arr.shape.size()-1; dim++) {
- outer_dim_elems *= arr.shape[dim];
- }
- size_t inner_dim_elems = arr.shape[arr.shape.size()-1];
- DEBUG_NPY2APINTSTREAM("n_outer " << outer_dim_elems << " n_inner " << inner_dim_elems)
- for(size_t outer_elem = 0; outer_elem < outer_dim_elems; outer_elem++) {
- PackedT packed_elem = 0;
- for(size_t ii = 0; ii < inner_dim_elems; ii++) {
- size_t i = reverse_inner ? inner_dim_elems-ii-1 : ii;
- NpyT loaded_elem_npyt = *loaded_data;
- ElemT loaded_elem = (ElemT) loaded_elem_npyt;
- DEBUG_NPY2APINTSTREAM("NpyT " << loaded_elem_npyt << " elem " << loaded_elem)
- packed_elem((i+1)*ElemBits-1, i*ElemBits) = loaded_elem;
- loaded_data++;
+void npy2apintstream(const char * npy_path, hls::stream<PackedT> & out_stream, bool reverse_inner = true, size_t numReps = 1) {
+ for(size_t rep = 0; rep < numReps; rep++) {
+ cnpy::NpyArray arr = cnpy::npy_load(npy_path);
+ DEBUG_NPY2APINTSTREAM("word_size " << arr.word_size << " num_vals " << arr.num_vals)
+ if(arr.word_size != sizeof(NpyT)) {
+ throw "Npy array word size and specified NpyT size do not match";
+ }
+ NpyT* loaded_data = arr.data<NpyT>();
+ size_t outer_dim_elems = 1;
+ for(size_t dim = 0; dim < arr.shape.size()-1; dim++) {
+ outer_dim_elems *= arr.shape[dim];
+ }
+ size_t inner_dim_elems = arr.shape[arr.shape.size()-1];
+ DEBUG_NPY2APINTSTREAM("n_outer " << outer_dim_elems << " n_inner " << inner_dim_elems)
+ for(size_t outer_elem = 0; outer_elem < outer_dim_elems; outer_elem++) {
+ PackedT packed_elem = 0;
+ for(size_t ii = 0; ii < inner_dim_elems; ii++) {
+ size_t i = reverse_inner ? inner_dim_elems-ii-1 : ii;
+ NpyT loaded_elem_npyt = *loaded_data;
+ ElemT loaded_elem = (ElemT) loaded_elem_npyt;
+ DEBUG_NPY2APINTSTREAM("NpyT " << loaded_elem_npyt << " elem " << loaded_elem)
+ packed_elem((i+1)*ElemBits-1, i*ElemBits) = loaded_elem;
+ loaded_data++;
+ }
+ DEBUG_NPY2APINTSTREAM("packed hls elem " << std::hex << packed_elem << std::dec)
+ out_stream << packed_elem;
}
- DEBUG_NPY2APINTSTREAM("packed hls elem " << std::hex << packed_elem << std::dec)
- out_stream << packed_elem;
}
}
template <typename PackedT, typename ElemT, int ElemBits, typename NpyT>
-void apintstream2npy(hls::stream<PackedT> & in_stream, const std::vector<size_t> & shape, const char * npy_path, bool reverse_inner = true) {
- std::vector<NpyT> data_to_save;
- size_t outer_dim_elems = 1;
- for(size_t dim = 0; dim < shape.size()-1; dim++) {
- outer_dim_elems *= shape[dim];
- }
- size_t inner_dim_elems = shape[shape.size()-1];
- DEBUG_APINTSTREAM2NPY("n_outer " << outer_dim_elems << " n_inner " << inner_dim_elems)
- for(size_t outer_elem = 0; outer_elem < outer_dim_elems; outer_elem++) {
- PackedT packed_elem;
- in_stream >> packed_elem;
- DEBUG_APINTSTREAM2NPY("packed hls elem " << std::hex << packed_elem << std::dec)
- for(size_t ii = 0; ii < inner_dim_elems; ii++) {
- size_t i = reverse_inner ? inner_dim_elems-ii-1 : ii;
- ElemT elem = packed_elem((i+1)*ElemBits-1, i*ElemBits);
- NpyT npyt = (NpyT) elem;
- DEBUG_APINTSTREAM2NPY("elem " << elem << " NpyT " << npyt)
- data_to_save.push_back(npyt);
+void apintstream2npy(hls::stream<PackedT> & in_stream, const std::vector<size_t> & shape, const char * npy_path, bool reverse_inner = true, size_t numReps = 1) {
+ for(size_t rep = 0; rep < numReps; rep++) {
+ std::vector<NpyT> data_to_save;
+ size_t outer_dim_elems = 1;
+ for(size_t dim = 0; dim < shape.size()-1; dim++) {
+ outer_dim_elems *= shape[dim];
+ }
+ size_t inner_dim_elems = shape[shape.size()-1];
+ DEBUG_APINTSTREAM2NPY("n_outer " << outer_dim_elems << " n_inner " << inner_dim_elems)
+ for(size_t outer_elem = 0; outer_elem < outer_dim_elems; outer_elem++) {
+ PackedT packed_elem;
+ in_stream >> packed_elem;
+ DEBUG_APINTSTREAM2NPY("packed hls elem " << std::hex << packed_elem << std::dec)
+ for(size_t ii = 0; ii < inner_dim_elems; ii++) {
+ size_t i = reverse_inner ? inner_dim_elems-ii-1 : ii;
+ ElemT elem = packed_elem((i+1)*ElemBits-1, i*ElemBits);
+ NpyT npyt = (NpyT) elem;
+ DEBUG_APINTSTREAM2NPY("elem " << elem << " NpyT " << npyt)
+ data_to_save.push_back(npyt);
+ }
}
+ cnpy::npy_save(npy_path, &data_to_save[0], shape, "w");
}
- cnpy::npy_save(npy_path, &data_to_save[0], shape, "w");
}
diff --git a/src/finn/transformation/__init__.py b/src/finn/transformation/__init__.py
index a4e0bcf330a8ad1797eb76e61ba63511eb903dcf..e9f5fe15f6bdefe1e739394495f67a972ccff669 100644
--- a/src/finn/transformation/__init__.py
+++ b/src/finn/transformation/__init__.py
@@ -48,6 +48,8 @@ Guide to writing FINN transformations
"""
from abc import ABC, abstractmethod
+from finn.util.basic import get_num_default_workers
+import multiprocessing as mp
class Transformation(ABC):
@@ -60,3 +62,54 @@ class Transformation(ABC):
@abstractmethod
def apply(self, model):
pass
+
+
+class NodeLocalTransformation(Transformation):
+ """
+ Parent class for transformations, which can be executed locally to one node
+ by accessing and modifying the attributes of only that node.
+ This class can then automatically parallelize the transformation.
+ Transformations sublcassing NodeLocalTransformation must implement the
+ abstract method applyNodeLocal().
+
+ To control the degree of parallelization, specify the num_workers argument
+ in the constructor, using one of the following values:
+ * None: use NUM_DEFAULT_WORKERS environment variable
+ * 0: use all available CPU cores
+ * (any other int>0): set number of parallel workers
+ """
+
+ def __init__(self, num_workers=None):
+ super().__init__()
+ if num_workers is None:
+ self._num_workers = get_num_default_workers()
+ else:
+ self._num_workers = num_workers
+ assert self._num_workers >= 0, "Number of workers must be nonnegative."
+ if self._num_workers == 0:
+ self._num_workers = mp.cpu_count()
+
+ @abstractmethod
+ def applyNodeLocal(self, node):
+ pass
+
+ def apply(self, model):
+ # Remove old nodes from the current model
+ old_nodes = []
+ for i in range(len(model.graph.node)):
+ old_nodes.append(model.graph.node.pop())
+
+ # Execute transformation in parallel
+ with mp.Pool(self._num_workers) as p:
+ new_nodes_and_bool = p.map(self.applyNodeLocal, old_nodes, chunksize=1)
+
+ # extract nodes and check if the transformation needs to run again
+ # Note: .pop() had initially reversed the node order
+ run_again = False
+ for node, run in reversed(new_nodes_and_bool):
+ # Reattach new nodes to old model
+ model.graph.node.append(node)
+ if run is True:
+ run_again = True
+
+ return (model, run_again)
diff --git a/src/finn/transformation/batchnorm_to_affine.py b/src/finn/transformation/batchnorm_to_affine.py
index 77657cf5e2ef14e38aa817e895488fd6dd310cde..401c5916415cd327a52a43f89c076bd7abd40647 100644
--- a/src/finn/transformation/batchnorm_to_affine.py
+++ b/src/finn/transformation/batchnorm_to_affine.py
@@ -67,6 +67,16 @@ class BatchNormToAffine(Transformation):
if consumer.op_type == "Squeeze":
bn_output = consumer.output[0]
data_shape = model.get_tensor_shape(bn_input)
+ assert A.ndim == B.ndim, "Unexpected mul/add dims in BatchNormToAffine"
+ assert (
+ len(data_shape) >= A.ndim
+ ), "Unexpected number of dims found in BatchNormToAffine"
+ # reshape the mul/add constants to match the data shape/dims
+ # by adding (1,) dimensions to the right
+ n_spatial_dims = len(data_shape) - 2
+ target_shape = (1, -1) + tuple(1 for i in range(n_spatial_dims))
+ A = A.reshape(target_shape)
+ B = B.reshape(target_shape)
# create value_info and initializers for Mul and Add constants
mul_const = oh.make_tensor_value_info(
model.make_new_valueinfo_name(), TensorProto.FLOAT, A.shape
diff --git a/src/finn/transformation/bipolar_to_xnor.py b/src/finn/transformation/bipolar_to_xnor.py
index 8e8633f3836ec15c35c769e0ed6d6829fed37538..4c7ebaf04e35f94e84e52e0b4520ee2369502120 100644
--- a/src/finn/transformation/bipolar_to_xnor.py
+++ b/src/finn/transformation/bipolar_to_xnor.py
@@ -33,6 +33,7 @@ from onnx import helper as oh
from finn.core.datatype import DataType
from finn.transformation import Transformation
from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.infer_datatypes import InferDataTypes
from finn.util.basic import get_by_name
@@ -53,7 +54,28 @@ class ConvertBipolarMatMulToXnorPopcount(Transformation):
i_bp = model.get_tensor_datatype(mm_input) == DataType.BIPOLAR
w_bp = model.get_tensor_datatype(mm_weight) == DataType.BIPOLAR
if i_bp and w_bp:
+ # find producing threshold node and adjust output to binary
+ def find_prod_mt(x):
+ is_mt = x.op_type == "MultiThreshold"
+ is_bp = False
+ if is_mt:
+ dt = get_by_name(x.attribute, "out_dtype").s
+ is_bp = dt.decode("utf-8") == "BIPOLAR"
+ return is_mt and is_bp
+
+ mt_chain = model.find_upstream(mm_input, find_prod_mt)
+ if len(mt_chain) == 0:
+ raise Exception(
+ """Could not find upstream bipolar
+ MultiThreshold"""
+ )
graph_modified = True
+ mt = mt_chain[-1]
+ bin_dt_attr = "BINARY".encode("utf-8")
+ get_by_name(mt.attribute, "out_dtype").s = bin_dt_attr
+ get_by_name(mt.attribute, "out_scale").f = 1.0
+ get_by_name(mt.attribute, "out_bias").f = 0
+ model.set_tensor_datatype(mm_input, DataType.BINARY)
# change node type and domain
n.op_type = "XnorPopcountMatMul"
n.domain = "finn"
@@ -63,19 +85,6 @@ class ConvertBipolarMatMulToXnorPopcount(Transformation):
K = Wbin.shape[0]
model.set_initializer(mm_weight, Wbin)
model.set_tensor_datatype(mm_weight, DataType.BINARY)
- # find producing threshold node and adjust output to binary
- mt = model.find_producer(mm_input)
- if mt is not None and mt.op_type == "MultiThreshold":
- bin_dt_attr = "BINARY".encode("utf-8")
- get_by_name(mt.attribute, "out_dtype").s = bin_dt_attr
- get_by_name(mt.attribute, "out_scale").f = 1.0
- get_by_name(mt.attribute, "out_bias").f = 0
- model.set_tensor_datatype(mm_input, DataType.BINARY)
- else:
- raise Exception(
- """Requires Bipolar2Binary, not yet
- implemented."""
- )
# make new output node with correct shape
mm_out_shape = model.get_tensor_shape(mm_output)
xnorpcout = oh.make_tensor_value_info(
@@ -113,5 +122,7 @@ class ConvertBipolarMatMulToXnorPopcount(Transformation):
# insert where the batchnorm is to preserve topological ordering
graph.node.insert(node_ind, mul_node)
graph.node.insert(node_ind + 1, add_node)
- model = model.transform(InferShapes())
+ if graph_modified:
+ model = model.transform(InferShapes())
+ model = model.transform(InferDataTypes())
return (model, graph_modified)
diff --git a/src/finn/transformation/double_to_single_float.py b/src/finn/transformation/double_to_single_float.py
new file mode 100644
index 0000000000000000000000000000000000000000..4f7eb1cc82b346321eb6ee711b87c2c98ccfdaee
--- /dev/null
+++ b/src/finn/transformation/double_to_single_float.py
@@ -0,0 +1,45 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from finn.transformation import Transformation
+import numpy as np
+
+
+class DoubleToSingleFloat(Transformation):
+ """Convert any float64 initializers to float32."""
+
+ def apply(self, model):
+ graph_modified = False
+ init_names = [x.name for x in model.graph.initializer]
+ for nm in init_names:
+ init = model.get_initializer(nm)
+ if init.dtype == np.float64:
+ init_f32 = init.astype(np.float32)
+ model.set_initializer(nm, init_f32)
+ graph_modified = True
+ return (model, graph_modified)
diff --git a/src/finn/transformation/fpgadataflow/annotate_resources.py b/src/finn/transformation/fpgadataflow/annotate_resources.py
new file mode 100644
index 0000000000000000000000000000000000000000..d192372a7d9c1f6ee2f088c6a058b994d21f6c99
--- /dev/null
+++ b/src/finn/transformation/fpgadataflow/annotate_resources.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import finn.custom_op.registry as registry
+from finn.transformation import Transformation
+from finn.transformation.move_reshape import _is_fpgadataflow_node
+from finn.analysis.fpgadataflow.res_estimation import res_estimation
+from finn.analysis.fpgadataflow.hls_synth_res_estimation import hls_synth_res_estimation
+from finn.analysis.fpgadataflow.post_synth_res import post_synth_res
+
+
+class AnnotateResources(Transformation):
+ """Annotate the amount of FPGA resources taken by each fpgadataflow
+ node as an attribute on the node, depending on the mode parameter:
+ * 'estimate' -- use the analytical estimation model
+ * 'hls' -- use results from the HLS synthesis report
+
+ No annotations can be provided unless the relevant transformation for the
+ chosen mode (e.g. HLSSynth_IPGen for hls) was previously run.
+ """
+
+ def __init__(self, mode):
+ super().__init__()
+ self.mode = mode
+
+ def apply(self, model):
+ graph = model.graph
+ if self.mode == "estimate":
+ res_fxn = res_estimation
+ elif self.mode == "hls":
+ res_fxn = hls_synth_res_estimation
+ elif self.mode == "synth":
+ res_fxn = post_synth_res
+ else:
+ raise Exception("Unrecognized mode for AnnotateResources")
+ res_dict = model.analysis(res_fxn)
+ total_dict = {}
+ for lname in res_dict.keys():
+ layer_res_dict = res_dict[lname]
+ for r_type in layer_res_dict.keys():
+ r_amount = layer_res_dict[r_type]
+ r_amount = float(r_amount)
+ if r_type in total_dict.keys():
+ total_dict[r_type] += r_amount
+ else:
+ total_dict[r_type] = r_amount
+ model.set_metadata_prop("res_total_" + self.mode, str(total_dict))
+ for node in graph.node:
+ if _is_fpgadataflow_node(node) and node.name in res_dict.keys():
+ op_inst = registry.getCustomOp(node)
+ op_inst.set_nodeattr("res_" + self.mode, str(res_dict[node.name]))
+
+ return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/cleanup.py b/src/finn/transformation/fpgadataflow/cleanup.py
index e1bf53f7ef53c986fffe3dcc507e6886660eb611..a31cbfa7dd30eff37ceb2d7bf3c162093a5a3a1c 100644
--- a/src/finn/transformation/fpgadataflow/cleanup.py
+++ b/src/finn/transformation/fpgadataflow/cleanup.py
@@ -30,7 +30,7 @@ import os
import shutil
import finn.custom_op.registry as registry
-import finn.util.basic as util
+from finn.util.fpgadataflow import is_fpgadataflow_node
from finn.transformation import Transformation
@@ -53,36 +53,33 @@ class CleanUp(Transformation):
model.set_metadata_prop("vivado_stitch_proj", "")
for node in model.graph.node:
op_type = node.op_type
- if node.domain == "finn":
- backend_attribute = util.get_by_name(node.attribute, "backend")
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- try:
- # lookup op_type in registry of CustomOps
- inst = registry.custom_op[op_type](node)
- # delete code_gen_dir from npysim
- code_gen_dir = inst.get_nodeattr("code_gen_dir_npysim")
- if os.path.isdir(code_gen_dir):
- shutil.rmtree(code_gen_dir)
- inst.set_nodeattr("code_gen_dir_npysim", "")
- inst.set_nodeattr("executable_path", "")
- # delete code_gen_dir from ipgen and project folder
- code_gen_dir = inst.get_nodeattr("code_gen_dir_ipgen")
- ipgen_path = inst.get_nodeattr("ipgen_path")
- if os.path.isdir(code_gen_dir):
- shutil.rmtree(code_gen_dir)
- if os.path.isdir(ipgen_path):
- shutil.rmtree(ipgen_path)
- inst.set_nodeattr("code_gen_dir_ipgen", "")
- inst.set_nodeattr("ipgen_path", "")
- # delete Java HotSpot Performance data log
- for d_name in os.listdir("/tmp/"):
- if "hsperfdata" in d_name:
- shutil.rmtree("/tmp/" + str(d_name))
+ if is_fpgadataflow_node(node) is True:
+ try:
+ # lookup op_type in registry of CustomOps
+ inst = registry.custom_op[op_type](node)
+ # delete code_gen_dir from npysim
+ code_gen_dir = inst.get_nodeattr("code_gen_dir_npysim")
+ if os.path.isdir(code_gen_dir):
+ shutil.rmtree(code_gen_dir)
+ inst.set_nodeattr("code_gen_dir_npysim", "")
+ inst.set_nodeattr("executable_path", "")
+ # delete code_gen_dir from ipgen and project folder
+ code_gen_dir = inst.get_nodeattr("code_gen_dir_ipgen")
+ ipgen_path = inst.get_nodeattr("ipgen_path")
+ if os.path.isdir(code_gen_dir):
+ shutil.rmtree(code_gen_dir)
+ if os.path.isdir(ipgen_path):
+ shutil.rmtree(ipgen_path)
+ inst.set_nodeattr("code_gen_dir_ipgen", "")
+ inst.set_nodeattr("ipgen_path", "")
+ # delete Java HotSpot Performance data log
+ for d_name in os.listdir("/tmp/"):
+ if "hsperfdata" in d_name:
+ shutil.rmtree("/tmp/" + str(d_name))
- except KeyError:
- # exception if op_type is not supported
- raise Exception(
- "Custom op_type %s is currently not supported." % op_type
- )
+ except KeyError:
+ # exception if op_type is not supported
+ raise Exception(
+ "Custom op_type %s is currently not supported." % op_type
+ )
return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/codegen_ipgen.py b/src/finn/transformation/fpgadataflow/codegen_ipgen.py
index ab3b4e820e04ff1f0a02b6b95254b5fe8b45de91..fa7725ae1fa03cc204aa58969d6fbc6cf71e7d97 100644
--- a/src/finn/transformation/fpgadataflow/codegen_ipgen.py
+++ b/src/finn/transformation/fpgadataflow/codegen_ipgen.py
@@ -30,7 +30,8 @@ import os
import finn.custom_op.registry as registry
from finn.transformation import Transformation
-from finn.util.basic import get_by_name, make_build_dir
+from finn.util.basic import make_build_dir
+from finn.util.fpgadataflow import is_fpgadataflow_node
def _codegen_single_node(node, model, fpgapart, clk):
@@ -46,7 +47,7 @@ def _codegen_single_node(node, model, fpgapart, clk):
# ensure that there is a directory
if code_gen_dir == "" or not os.path.isdir(code_gen_dir):
code_gen_dir = make_build_dir(
- prefix="code_gen_ipgen_" + str(node.op_type) + "_"
+ prefix="code_gen_ipgen_" + str(node.name) + "_"
)
inst.set_nodeattr("code_gen_dir_ipgen", code_gen_dir)
# ensure that there is generated code inside the dir
@@ -77,11 +78,6 @@ class CodeGen_ipgen(Transformation):
def apply(self, model):
for node in model.graph.node:
- if node.domain == "finn":
- backend_attribute = get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- _codegen_single_node(node, model, self.fpgapart, self.clk)
+ if is_fpgadataflow_node(node) is True:
+ _codegen_single_node(node, model, self.fpgapart, self.clk)
return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
index fcb4af37c951de3869b731e755ef48ba4fdb579f..bc1fce836a16f49e6549f6b24de2973b902bf066 100644
--- a/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
+++ b/src/finn/transformation/fpgadataflow/codegen_ipstitch.py
@@ -31,6 +31,7 @@ import subprocess
from finn.transformation import Transformation
from finn.util.basic import get_by_name, make_build_dir
+from finn.custom_op.registry import getCustomOp
class CodeGen_ipstitch(Transformation):
@@ -65,16 +66,11 @@ class CodeGen_ipstitch(Transformation):
backend_value == "fpgadataflow"
), """Backend node attribute is not
set to "fpgadataflow"."""
- ip_dir_attribute = get_by_name(node.attribute, "ipgen_path")
- assert (
- ip_dir_attribute is not None
- ), """Node attribute "ipgen_path" is not set.
- Please run transformation CodeGen_ipgen first."""
- ip_dir_value = ip_dir_attribute.s.decode("UTF-8")
- ip_dir_value += "/sol1/impl/ip"
+ node_inst = getCustomOp(node)
+ ip_dir_value = node_inst.get_nodeattr("ip_path")
assert os.path.isdir(ip_dir_value), "IP generation directory doesn't exist."
ip_dirs += [ip_dir_value]
- vlnv = "xilinx.com:hls:%s:1.0" % node.name
+ vlnv = node_inst.get_nodeattr("ip_vlnv")
inst_name = node.name
create_cmd = "create_bd_cell -type ip -vlnv %s %s" % (vlnv, inst_name)
create_cmds += [create_cmd]
@@ -125,6 +121,11 @@ class CodeGen_ipstitch(Transformation):
connect_cmds.append(
"make_bd_intf_pins_external [get_bd_intf_pins %s/out_r]" % inst_name
)
+ # make AXI lite IF external
+ connect_cmds.append(
+ "make_bd_intf_pins_external [get_bd_intf_pins %s/s_axi_control]"
+ % inst_name
+ )
# create a temporary folder for the project
prjname = "finn_vivado_stitch_proj"
@@ -146,6 +147,9 @@ class CodeGen_ipstitch(Transformation):
tcl.append('create_bd_design "%s"' % block_name)
tcl.extend(create_cmds)
tcl.extend(connect_cmds)
+ # TODO get from Transformation arg or metadata_prop
+ fclk_hz = 100 * 1000000
+ tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk_0]" % fclk_hz)
tcl.append("regenerate_bd_layout")
tcl.append("validate_bd_design")
tcl.append("save_bd_design")
@@ -180,7 +184,8 @@ class CodeGen_ipstitch(Transformation):
tcl.append("set all_v_files [get_files -filter {FILE_TYPE == Verilog}]")
v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
tcl.append("set fp [open %s w]" % v_file_list)
- tcl.append("puts $fp $all_v_files")
+ # write each verilog filename to all_verilog_srcs.txt
+ tcl.append("foreach vf $all_v_files {puts $fp $vf}")
tcl.append("close $fp")
# write the project creator tcl script
tcl_string = "\n".join(tcl) + "\n"
diff --git a/src/finn/transformation/fpgadataflow/codegen_npysim.py b/src/finn/transformation/fpgadataflow/codegen_npysim.py
index d2862d82cf76f62bc236ace9d44c607dd2ab86ff..02200e76db3f9c8207605bb93c4b07f0ebc76cab 100644
--- a/src/finn/transformation/fpgadataflow/codegen_npysim.py
+++ b/src/finn/transformation/fpgadataflow/codegen_npysim.py
@@ -30,7 +30,8 @@ import os
import finn.custom_op.registry as registry
from finn.transformation import Transformation
-from finn.util.basic import get_by_name, make_build_dir
+from finn.util.basic import make_build_dir
+from finn.util.fpgadataflow import is_fpgadataflow_node
def _codegen_single_node(node, model):
@@ -46,7 +47,7 @@ def _codegen_single_node(node, model):
# ensure that there is a directory
if code_gen_dir == "" or not os.path.isdir(code_gen_dir):
code_gen_dir = make_build_dir(
- prefix="code_gen_npysim_" + str(node.op_type) + "_"
+ prefix="code_gen_npysim_" + str(node.name) + "_"
)
inst.set_nodeattr("code_gen_dir_npysim", code_gen_dir)
# ensure that there is generated code inside the dir
@@ -67,11 +68,6 @@ class CodeGen_npysim(Transformation):
def apply(self, model):
for node in model.graph.node:
- if node.domain == "finn":
- backend_attribute = get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- _codegen_single_node(node, model)
+ if is_fpgadataflow_node(node) is True:
+ _codegen_single_node(node, model)
return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/compile.py b/src/finn/transformation/fpgadataflow/compile.py
index e577c3af6d2b92d8a2c63e89e3b1bca21d3d7c0a..40c7da8f77efeaa655459402699a401b642b776c 100644
--- a/src/finn/transformation/fpgadataflow/compile.py
+++ b/src/finn/transformation/fpgadataflow/compile.py
@@ -27,51 +27,49 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import finn.custom_op.registry as registry
-import finn.util.basic as util
-from finn.transformation import Transformation
+from finn.util.fpgadataflow import is_fpgadataflow_node
+from finn.transformation import NodeLocalTransformation
-class Compile(Transformation):
+class Compile(NodeLocalTransformation):
"""For every node: compile C++ code in node attribute "code_gen_dir_npysim"
and save path to executables in node attribute "executable_path".
All nodes in the graph must have the fpgadataflow backend attribute.
To use these executables, exec_mode must be set to "npysim" (using transformation
SetExecMode) and the model has to be executed using execute_onnx() from
- finn.core.onnx_exec"""
+ finn.core.onnx_exec
- def __init__(self):
- super().__init__()
+ * num_workers (int or None) number of parallel workers, see documentation in
+ NodeLocalTransformation for more details.
+ """
- def apply(self, model):
- for node in model.graph.node:
- op_type = node.op_type
- if node.domain == "finn":
- backend_attribute = util.get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- try:
- # lookup op_type in registry of CustomOps
- inst = registry.custom_op[op_type](node)
- # ensure that code is generated
- assert (
- inst.get_nodeattr("code_gen_dir_npysim") != ""
- ), """Node
- attribute "code_gen_dir_npysim" is not set. Please run
- Transformation CodeGen_npysim first."""
- # call the compilation function for this node
- inst.compile_singlenode_code()
- # ensure that executable path is now set
- assert (
- inst.get_nodeattr("executable_path") != ""
- ), """Transformation
- compile was not successful, there is no path to executables set
- in node attribute "executable_path"."""
- except KeyError:
- # exception if op_type is not supported
- raise Exception(
- "Custom op_type %s is currently not supported." % op_type
- )
- return (model, False)
+ def __init__(self, num_workers=None):
+ super().__init__(num_workers=num_workers)
+
+ def applyNodeLocal(self, node):
+ op_type = node.op_type
+ if is_fpgadataflow_node(node) is True:
+ try:
+ # lookup op_type in registry of CustomOps
+ inst = registry.custom_op[op_type](node)
+ # ensure that code is generated
+ assert (
+ inst.get_nodeattr("code_gen_dir_npysim") != ""
+ ), """Node
+ attribute "code_gen_dir_npysim" is not set. Please run
+ Transformation CodeGen_npysim first."""
+ # call the compilation function for this node
+ inst.compile_singlenode_code()
+ # ensure that executable path is now set
+ assert (
+ inst.get_nodeattr("executable_path") != ""
+ ), """Transformation
+ compile was not successful, there is no path to executables set
+ in node attribute "executable_path"."""
+ except KeyError:
+ # exception if op_type is not supported
+ raise Exception(
+ "Custom op_type %s is currently not supported." % op_type
+ )
+ return (node, False)
diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py
index 1cc42badc7c6f9ce88d802134596320c84f5ab4f..dbd98623c4cdf5baca9fa9c137debf8be0f70981 100644
--- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py
+++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py
@@ -31,6 +31,107 @@ from onnx import helper
from finn.core.datatype import DataType
from finn.transformation import Transformation
from finn.custom_op.registry import getCustomOp
+from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.infer_datatypes import InferDataTypes
+
+
+class InferConvInpGen(Transformation):
+ """Convert Im2Col layers to ConvolutionInputGenerator layers."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "Im2Col":
+ i2c_input = n.input[0]
+ i2c_output = n.output[0]
+ i2c_in_shape = model.get_tensor_shape(i2c_input)
+ i2c_out_shape = model.get_tensor_shape(i2c_output)
+ dt = model.get_tensor_datatype(i2c_input)
+ i2c_inst = getCustomOp(n)
+ stride = i2c_inst.get_nodeattr("stride")
+ k = i2c_inst.get_nodeattr("kernel_size")
+ pad = i2c_inst.get_nodeattr("pad_amount")
+ pad_val = i2c_inst.get_nodeattr("pad_value")
+ ifm_ch = i2c_in_shape[-1]
+ ifm_dim = i2c_in_shape[1]
+ ofm_dim = i2c_out_shape[1]
+ # if padding enabled, ensure pad_val supported by DataType
+ if pad > 0:
+ assert dt.allowed(pad_val), "Im2Col DataType must support pad_val"
+ # create equivalent ConvolutionInputGenerator node
+ # TODO support padding
+ new_node = helper.make_node(
+ "ConvolutionInputGenerator",
+ [i2c_input],
+ [i2c_output],
+ domain="finn",
+ backend="fpgadataflow",
+ ConvKernelDim=k,
+ IFMChannels=ifm_ch,
+ IFMDim=ifm_dim,
+ OFMDim=ofm_dim,
+ SIMD=ifm_ch,
+ Stride=stride,
+ inputDataType=dt.name,
+ outputDataType=dt.name,
+ )
+ graph.node.insert(node_ind, new_node)
+ # remove old nodes
+ graph.node.remove(n)
+ graph_modified = True
+ if graph_modified:
+ model = model.transform(InferShapes())
+ model = model.transform(InferDataTypes())
+ return (model, graph_modified)
+
+
+class InferStreamingMaxPool(Transformation):
+ """Convert MaxPoolNHWC layers to StreamingMaxPool layers."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "MaxPoolNHWC":
+ mp_input = n.input[0]
+ mp_output = n.output[0]
+ mp_in_shape = model.get_tensor_shape(mp_input)
+ # mp_out_shape = model.get_tensor_shape(mp_output)
+ dt = model.get_tensor_datatype(mp_input)
+ mp_inst = getCustomOp(n)
+ # stride = mp_inst.get_nodeattr("strides")[0]
+ k = mp_inst.get_nodeattr("kernel_shape")[0]
+ # pad = mp_inst.get_nodeattr("pads")[0]
+ ifm_ch = mp_in_shape[-1]
+ ifm_dim = mp_in_shape[1]
+ # ofm_dim = mp_out_shape[1]
+ if ifm_dim % k == 0:
+ # create equivalent StreamingMaxPool_Batch node
+ # TODO support non-k strides
+ new_node = helper.make_node(
+ "StreamingMaxPool_Batch",
+ [mp_input],
+ [mp_output],
+ domain="finn",
+ backend="fpgadataflow",
+ PoolDim=k,
+ NumChannels=ifm_ch,
+ ImgDim=ifm_dim,
+ dataType=dt.name,
+ )
+ graph.node.insert(node_ind, new_node)
+ # remove old nodes
+ graph.node.remove(n)
+ graph_modified = True
+ if graph_modified:
+ model = model.transform(InferShapes())
+ model = model.transform(InferDataTypes())
+ return (model, graph_modified)
class InferBinaryStreamingFCLayer(Transformation):
@@ -38,6 +139,10 @@ class InferBinaryStreamingFCLayer(Transformation):
StreamingFCLayer_Batch layers. Any immediately following MultiThreshold
layers will also be absorbed into the MVTU."""
+ def __init__(self, mem_mode="const"):
+ super().__init__()
+ self.mem_mode = mem_mode
+
def apply(self, model):
graph = model.graph
node_ind = 0
@@ -47,6 +152,9 @@ class InferBinaryStreamingFCLayer(Transformation):
if n.op_type == "XnorPopcountMatMul":
mm_input = n.input[0]
mm_weight = n.input[1]
+ mm_output = n.output[0]
+ mm_in_shape = model.get_tensor_shape(mm_input)
+ mm_out_shape = model.get_tensor_shape(mm_output)
assert (
model.get_tensor_datatype(mm_input) == DataType.BINARY
), """First
@@ -81,6 +189,7 @@ class InferBinaryStreamingFCLayer(Transformation):
# TODO ensure integer thresholds?
# create MVTU (i.e. including activation)
mt_output = consumer.output[0]
+ mt_out_shape = model.get_tensor_shape(mt_output)
mt_thres = consumer.input[1]
T = model.get_initializer(mt_thres)
assert (
@@ -93,10 +202,8 @@ class InferBinaryStreamingFCLayer(Transformation):
actval = 0
else:
actval = odt.min()
- in_shape = [1, mw]
- out_shape = [1, mh]
- model.set_tensor_shape(mm_input, in_shape)
- model.set_tensor_shape(mt_output, out_shape)
+ model.set_tensor_shape(mm_input, mm_in_shape)
+ model.set_tensor_shape(mt_output, mt_out_shape)
# create and insert new StreamingFCLayer node
new_node = helper.make_node(
"StreamingFCLayer_Batch",
@@ -115,6 +222,8 @@ class InferBinaryStreamingFCLayer(Transformation):
ActVal=actval,
binaryXnorMode=1,
noActivation=0,
+ numInputVectors=list(mm_in_shape[:-1]),
+ mem_mode=self.mem_mode,
)
graph.node.insert(node_ind, new_node)
# remove old nodes
@@ -123,11 +232,9 @@ class InferBinaryStreamingFCLayer(Transformation):
graph_modified = True
else:
# no activation, matmul only
- in_shape = [1, mw]
- out_shape = [1, mh]
odt = model.get_tensor_datatype(mm_output)
- model.set_tensor_shape(mm_input, in_shape)
- model.set_tensor_shape(mm_output, out_shape)
+ model.set_tensor_shape(mm_input, mm_in_shape)
+ model.set_tensor_shape(mm_output, mm_out_shape)
# create and insert new StreamingFCLayer node
new_node = helper.make_node(
"StreamingFCLayer_Batch",
@@ -146,12 +253,16 @@ class InferBinaryStreamingFCLayer(Transformation):
ActVal=0,
binaryXnorMode=1,
noActivation=1,
+ numInputVectors=list(mm_in_shape[:-1]),
+ mem_mode=self.mem_mode,
)
graph.node.insert(node_ind, new_node)
# remove old node
graph.node.remove(n)
graph_modified = True
-
+ if graph_modified:
+ model = model.transform(InferShapes())
+ model = model.transform(InferDataTypes())
return (model, graph_modified)
@@ -160,6 +271,10 @@ class InferQuantizedStreamingFCLayer(Transformation):
StreamingFCLayer_Batch layers. Any immediately following MultiThreshold
layers will also be absorbed into the MVTU."""
+ def __init__(self, mem_mode="const"):
+ super().__init__()
+ self.mem_mode = mem_mode
+
def apply(self, model):
graph = model.graph
node_ind = 0
@@ -169,6 +284,9 @@ class InferQuantizedStreamingFCLayer(Transformation):
if n.op_type == "MatMul":
mm_input = n.input[0]
mm_weight = n.input[1]
+ mm_output = n.output[0]
+ mm_in_shape = model.get_tensor_shape(mm_input)
+ mm_out_shape = model.get_tensor_shape(mm_output)
idt = model.get_tensor_datatype(mm_input)
wdt = model.get_tensor_datatype(mm_weight)
if idt.is_integer() and wdt.is_integer():
@@ -198,6 +316,7 @@ class InferQuantizedStreamingFCLayer(Transformation):
# TODO ensure integer thresholds?
# create MVTU (i.e. including activation)
mt_output = consumer.output[0]
+ mt_out_shape = model.get_tensor_shape(mt_output)
mt_thres = consumer.input[1]
T = model.get_initializer(mt_thres)
assert (
@@ -217,10 +336,8 @@ class InferQuantizedStreamingFCLayer(Transformation):
assert (not odt.signed()) or (
actval < 0
), "Signed output requres actval < 0"
- in_shape = [1, mw]
- out_shape = [1, mh]
- model.set_tensor_shape(mm_input, in_shape)
- model.set_tensor_shape(mt_output, out_shape)
+ model.set_tensor_shape(mm_input, mm_in_shape)
+ model.set_tensor_shape(mt_output, mt_out_shape)
# create and insert new StreamingFCLayer node
new_node = helper.make_node(
"StreamingFCLayer_Batch",
@@ -239,6 +356,8 @@ class InferQuantizedStreamingFCLayer(Transformation):
ActVal=actval,
binaryXnorMode=0,
noActivation=0,
+ numInputVectors=list(mm_in_shape[:-1]),
+ mem_mode=self.mem_mode,
)
graph.node.insert(node_ind, new_node)
# remove old nodes
@@ -247,11 +366,9 @@ class InferQuantizedStreamingFCLayer(Transformation):
graph_modified = True
else:
# no activation, matmul only
- in_shape = [1, mw]
- out_shape = [1, mh]
odt = model.get_tensor_datatype(mm_output)
- model.set_tensor_shape(mm_input, in_shape)
- model.set_tensor_shape(mm_output, out_shape)
+ model.set_tensor_shape(mm_input, mm_in_shape)
+ model.set_tensor_shape(mm_output, mm_out_shape)
# create and insert new StreamingFCLayer node
new_node = helper.make_node(
"StreamingFCLayer_Batch",
@@ -270,9 +387,14 @@ class InferQuantizedStreamingFCLayer(Transformation):
ActVal=0,
binaryXnorMode=0,
noActivation=1,
+ numInputVectors=list(mm_in_shape[:-1]),
+ mem_mode=self.mem_mode,
)
graph.node.insert(node_ind, new_node)
# remove old node
graph.node.remove(n)
graph_modified = True
+ if graph_modified:
+ model = model.transform(InferShapes())
+ model = model.transform(InferDataTypes())
return (model, graph_modified)
diff --git a/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py b/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
index 9fb7f8652d1fa5e624776a81ff6946d67882aa2a..2af623818fe0e830883ef5065e5e7c9c7364ef1e 100644
--- a/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
+++ b/src/finn/transformation/fpgadataflow/hlssynth_ipgen.py
@@ -27,51 +27,49 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import finn.custom_op.registry as registry
-import finn.util.basic as util
-from finn.transformation import Transformation
+from finn.util.fpgadataflow import is_fpgadataflow_node
+from finn.transformation import NodeLocalTransformation
-class HLSSynth_IPGen(Transformation):
+class HLSSynth_IPGen(NodeLocalTransformation):
"""For each node: generate IP block from code in folder
that is referenced in node attribute "code_gen_dir_ipgen"
and save path of generated project in node attribute "ipgen_path".
All nodes in the graph must have the fpgadataflow backend attribute.
This transformation calls Vivado HLS for synthesis, so it will run for
- some time (several minutes)"""
+ some time (several minutes)
- def __init__(self):
- super().__init__()
+ * num_workers (int or None) number of parallel workers, see documentation in
+ NodeLocalTransformation for more details.
+ """
- def apply(self, model):
- for node in model.graph.node:
- op_type = node.op_type
- if node.domain == "finn":
- backend_attribute = util.get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- try:
- # lookup op_type in registry of CustomOps
- inst = registry.custom_op[op_type](node)
- # ensure that code is generated
- assert (
- inst.get_nodeattr("code_gen_dir_ipgen") != ""
- ), """Node
- attribute "code_gen_dir_ipgen" is empty. Please run
- transformation CodeGen_ipgen first."""
- # call the compilation function for this node
- inst.ipgen_singlenode_code()
- # ensure that executable path is now set
- assert (
- inst.get_nodeattr("ipgen_path") != ""
- ), """Transformation
- HLSSynth_IPGen was not successful. Node attribute "ipgen_path"
- is empty."""
- except KeyError:
- # exception if op_type is not supported
- raise Exception(
- "Custom op_type %s is currently not supported." % op_type
- )
- return (model, False)
+ def __init__(self, num_workers=None):
+ super().__init__(num_workers=num_workers)
+
+ def applyNodeLocal(self, node):
+ op_type = node.op_type
+ if is_fpgadataflow_node(node) is True:
+ try:
+ # lookup op_type in registry of CustomOps
+ inst = registry.custom_op[op_type](node)
+ # ensure that code is generated
+ assert (
+ inst.get_nodeattr("code_gen_dir_ipgen") != ""
+ ), """Node
+ attribute "code_gen_dir_ipgen" is empty. Please run
+ transformation CodeGen_ipgen first."""
+ # call the compilation function for this node
+ inst.ipgen_singlenode_code()
+ # ensure that executable path is now set
+ assert (
+ inst.get_nodeattr("ipgen_path") != ""
+ ), """Transformation
+ HLSSynth_IPGen was not successful. Node attribute "ipgen_path"
+ is empty."""
+ except KeyError:
+ # exception if op_type is not supported
+ raise Exception(
+ "Custom op_type %s is currently not supported." % op_type
+ )
+ return (node, False)
diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py
new file mode 100644
index 0000000000000000000000000000000000000000..3fe60292e8f54a8cdf394b5e09f8a3d2bca7605c
--- /dev/null
+++ b/src/finn/transformation/fpgadataflow/insert_dwc.py
@@ -0,0 +1,87 @@
+from onnx import TensorProto
+from onnx import helper as oh
+
+from finn.custom_op.registry import getCustomOp
+from finn.transformation import Transformation
+from finn.util.fpgadataflow import is_fpgadataflow_node
+
+
+def _is_dwc_node(node):
+ if node.op_type == "StreamingDataWidthConverter_Batch":
+ return True
+ else:
+ return False
+
+
+def _suitable_node(node):
+ if node is not None:
+ if is_fpgadataflow_node(node) is True:
+ if _is_dwc_node(node) is False:
+ return True
+ else:
+ return False
+ else:
+ return False
+ else:
+ return False
+
+
+class InsertDWC(Transformation):
+ """Ensure that the graph is terminated with a TLastMarker node, inserting
+ one if necessary."""
+
+ def __init__(self):
+ super().__init__()
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = -1
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if _suitable_node(n):
+ n_output = n.output[0]
+ consumer = model.find_consumer(n_output)
+ if _suitable_node(consumer) is True:
+ n0 = getCustomOp(n)
+ n1 = getCustomOp(consumer)
+ n0_out_shape = n0.get_folded_output_shape()
+ n1_in_shape = n1.get_folded_input_shape()
+ if n0_out_shape[-1] != n1_in_shape[-1]:
+ graph_modified = True
+ # determine dwc inwidth
+ dwc_in_width = n0.get_outstream_width()
+ # determine dwc outwidth
+ dwc_out_width = n1.get_instream_width()
+
+ # determine shape for dwc
+ dwc_shape = n0.get_normal_output_shape()
+
+ # determine dtype for dwc
+ dtype = n0.get_output_datatype()
+
+ dwc_output_tensor = oh.make_tensor_value_info(
+ model.make_new_valueinfo_name(),
+ TensorProto.FLOAT,
+ dwc_shape,
+ )
+ graph.value_info.append(dwc_output_tensor)
+
+ dwc_node = oh.make_node(
+ "StreamingDataWidthConverter_Batch",
+ [n_output],
+ [dwc_output_tensor.name],
+ domain="finn",
+ backend="fpgadataflow",
+ shape=dwc_shape,
+ inWidth=dwc_in_width,
+ outWidth=dwc_out_width,
+ dataType=str(dtype.name),
+ )
+ # insert dwc
+ graph.node.insert(node_ind + 1, dwc_node)
+
+ # set dwc output tensor as new input tensor of second node
+ consumer.input[0] = dwc_output_tensor.name
+
+ return (model, graph_modified)
diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py
new file mode 100644
index 0000000000000000000000000000000000000000..95a7a7154f10c15b38d94d4bef653649aa30a569
--- /dev/null
+++ b/src/finn/transformation/fpgadataflow/insert_fifo.py
@@ -0,0 +1,195 @@
+from onnx import TensorProto
+from onnx import helper as oh
+
+from finn.custom_op.registry import getCustomOp
+from finn.transformation import Transformation
+from finn.util.fpgadataflow import is_fpgadataflow_node
+import numpy as np
+
+
+def _is_fifo_node(node):
+ if node.op_type == "StreamingFIFO":
+ return True
+ else:
+ return False
+
+
+def _suitable_node(node):
+ if node is not None:
+ if is_fpgadataflow_node(node) is True:
+ if _is_fifo_node(node) is False:
+ return True
+ else:
+ return False
+ else:
+ return False
+ else:
+ return False
+
+
+def _suitable_folded_shapes(ishape, oshape):
+ i_dummy = np.random.rand(*ishape)
+ o_dummy = np.random.rand(*oshape)
+ ishape_canonical = np.squeeze(i_dummy).shape
+ oshape_canonical = np.squeeze(o_dummy).shape
+ return ishape_canonical == oshape_canonical
+
+
+class InsertFIFO(Transformation):
+ """Inserting FIFOs in the beginning and end of the graph as well as
+ between fpgadataflow nodes.
+
+ Takes the setting for the depth from the surrounding nodes by extracting
+ node attribute 'outFIFODepth' of the previous and node attribute 'inFIFODepth'
+ of the subsequent node. max() of these two values sets the FIFO depth.
+
+ The other node attributes necessary to create a FIFO node are taking from the
+ node the FIFO node is inserted after: 'folded_shape' and 'dtype'"""
+
+ def __init__(self):
+ super().__init__()
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = -1
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if _suitable_node(n):
+ n_output = n.output[0]
+ consumer = model.find_consumer(n_output)
+ if _suitable_node(consumer) is True:
+ n0 = getCustomOp(n)
+ # determine fifo node attributes
+ fld_shape = n0.get_folded_output_shape()
+ dtype = n0.get_output_datatype()
+
+ # check if folded_shape of output of first node and
+ # input of the second node is equal
+ n1 = getCustomOp(consumer)
+ fld_shape_2 = n1.get_folded_input_shape()
+ assert _suitable_folded_shapes(
+ fld_shape, fld_shape_2
+ ), """The
+ folded output shape of the first node is not the same as the
+ folded output shape of the second node. A streaming fifo can't
+ be implemented in between these nodes."""
+
+ # check if outFIFOdepth attribute of first node
+ # and inFIFOdepth attribute of consumer node is equal
+ n0_depth = n0.get_nodeattr("outFIFODepth")
+ n1_depth = n1.get_nodeattr("inFIFODepth")
+ if n0_depth == n1_depth:
+ fifo_depth = n0_depth
+ elif n0_depth != n1_depth:
+ fifo_depth = max(n0_depth, n1_depth)
+
+ if fifo_depth > 2:
+ # assumption: HLS streaming components already have
+ # depth-2 FIFOs on inputs and outputs, so no point
+ # creating additional small FIFOs in between --
+ # we only create the larger FIFOs specified
+ # create fifo node
+ fifo_output_tensor = oh.make_tensor_value_info(
+ model.make_new_valueinfo_name(),
+ TensorProto.FLOAT,
+ n0.get_normal_output_shape(),
+ )
+ graph.value_info.append(fifo_output_tensor)
+ model.set_tensor_datatype(fifo_output_tensor.name, dtype)
+
+ fifo_node = oh.make_node(
+ "StreamingFIFO",
+ [n_output],
+ [fifo_output_tensor.name],
+ domain="finn",
+ backend="fpgadataflow",
+ depth=fifo_depth,
+ folded_shape=fld_shape,
+ dataType=str(dtype.name),
+ )
+ # insert fifo
+ graph.node.insert(node_ind + 1, fifo_node)
+ # set fifo output tensor as new input tensor of second node
+ consumer.input[0] = fifo_output_tensor.name
+ # ensure created FIFO depth is reflected on both sides
+ n0.set_nodeattr("outFIFODepth", fifo_depth)
+ n1.set_nodeattr("inFIFODepth", fifo_depth)
+ graph_modified = True
+
+ if graph_modified is False:
+ # insert FIFO as first node
+ if graph.node[0].op_type != "StreamingFIFO":
+ n = graph.node[0]
+ n_input = n.input[0]
+ n0 = getCustomOp(n)
+ # determine fifo node attributes
+ fld_shape = n0.get_folded_input_shape()
+ dtype = n0.get_input_datatype()
+ fifo_depth = n0.get_nodeattr("inFIFODepth")
+
+ # create fifo node
+ fifo_output_tensor = oh.make_tensor_value_info(
+ model.make_new_valueinfo_name(),
+ TensorProto.FLOAT,
+ n0.get_normal_input_shape(),
+ )
+ graph.value_info.append(fifo_output_tensor)
+ model.set_tensor_datatype(fifo_output_tensor.name, dtype)
+
+ fifo_node = oh.make_node(
+ "StreamingFIFO",
+ [n_input],
+ [fifo_output_tensor.name],
+ domain="finn",
+ backend="fpgadataflow",
+ depth=fifo_depth,
+ folded_shape=fld_shape,
+ dataType=str(dtype.name),
+ )
+ # insert fifo
+ graph.node.insert(0, fifo_node)
+
+ # set fifo output tensor as new input tensor of second node
+ n.input[0] = fifo_output_tensor.name
+
+ # insert FIFO as last node
+ if graph.node[-1].op_type != "StreamingFIFO":
+ n = graph.node[-1]
+ assert (
+ n.op_type != "TLastMarker"
+ ), """Insert tlast marker should be done
+ after inserting the FIFOs"""
+ graph_out_name = graph.output[0].name
+ n0 = getCustomOp(n)
+ # determine fifo node attributes
+ fld_shape = n0.get_folded_output_shape()
+ dtype = n0.get_output_datatype()
+ fifo_depth = n0.get_nodeattr("inFIFODepth")
+
+ # create fifo node
+ fifo_input_tensor = oh.make_tensor_value_info(
+ model.make_new_valueinfo_name(),
+ TensorProto.FLOAT,
+ n0.get_normal_output_shape(),
+ )
+ graph.value_info.append(fifo_input_tensor)
+ model.set_tensor_datatype(fifo_output_tensor.name, dtype)
+
+ fifo_node = oh.make_node(
+ "StreamingFIFO",
+ [fifo_input_tensor.name],
+ [graph_out_name],
+ domain="finn",
+ backend="fpgadataflow",
+ depth=fifo_depth,
+ folded_shape=fld_shape,
+ dataType=str(dtype.name),
+ )
+ # insert fifo
+ graph.node.append(fifo_node)
+
+ # set fifo output tensor as new input tensor of second node
+ n.output[0] = fifo_input_tensor.name
+
+ return (model, graph_modified)
diff --git a/src/finn/transformation/fpgadataflow/make_deployment.py b/src/finn/transformation/fpgadataflow/make_deployment.py
index d797773fe540e930267839c5926269a73736f354..a185f5392c4b5ec848cd463e02ebab4be9c56a46 100644
--- a/src/finn/transformation/fpgadataflow/make_deployment.py
+++ b/src/finn/transformation/fpgadataflow/make_deployment.py
@@ -42,9 +42,10 @@ class DeployToPYNQ(Transformation):
IP address of board, username and password for board and target directory where
the files are stored on the board"""
- def __init__(self, ip, username, password, target_dir):
+ def __init__(self, ip, port, username, password, target_dir):
super().__init__()
self.ip = ip
+ self.port = port
self.username = username
self.password = password
self.target_dir = target_dir
@@ -52,6 +53,7 @@ class DeployToPYNQ(Transformation):
def apply(self, model):
# set metadata properties accordingly to user input specifications
model.set_metadata_prop("pynq_ip", self.ip)
+ model.set_metadata_prop("pynq_port", str(self.port))
model.set_metadata_prop("pynq_username", self.username)
model.set_metadata_prop("pynq_password", self.password)
model.set_metadata_prop("pynq_target_dir", self.target_dir)
@@ -76,18 +78,21 @@ class DeployToPYNQ(Transformation):
copy_tree(pynq_driver_dir, deployment_dir)
model.set_metadata_prop("pynq_deploy_dir", deployment_dir)
model.set_metadata_prop("exec_mode", "remote_pynq")
-
# create target directory on PYNQ board
- cmd = 'sshpass -p {} ssh {}@{} "mkdir -p {}"'.format(
- self.password, self.username, self.ip, self.target_dir
+ cmd = 'sshpass -p {} ssh {}@{} -p {} "mkdir -p {}"'.format(
+ self.password, self.username, self.ip, self.port, self.target_dir
)
bash_command = ["/bin/bash", "-c", cmd]
process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
process_compile.communicate()
-
# copy directory to PYNQ board using scp and sshpass
- cmd = "sshpass -p {} scp -r {} {}@{}:{}".format(
- self.password, deployment_dir, self.username, self.ip, self.target_dir
+ cmd = "sshpass -p {} scp -P{} -r {} {}@{}:{}".format(
+ self.password,
+ self.port,
+ deployment_dir,
+ self.username,
+ self.ip,
+ self.target_dir,
)
bash_command = ["/bin/bash", "-c", cmd]
process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_driver.py b/src/finn/transformation/fpgadataflow/make_pynq_driver.py
index 0bde02fa2c330748a718f6debf931b7d83ac7814..c5b8d35dba1069ac749e0a0d92060c8216ada507 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_driver.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_driver.py
@@ -87,14 +87,25 @@ class MakePYNQDriver(Transformation):
# fill in the driver template
driver_py = pynq_driver_dir + "/driver.py"
driver = templates.pynq_driver_template
+
+ def mss(x, batch_var_name="N"):
+ # "make shape string"
+ # for a shape like (1, ...) emit a string (N, ...)
+ # where N is the default value for batch_var_name
+ # this lets the driver work with a batch of samples at once
+ ret = str(x)
+ ret = ret.replace("(1,", "(%s," % batch_var_name)
+ ret = ret.replace("[1,", "[%s," % batch_var_name)
+ return ret
+
driver = driver.replace("$INPUT_FINN_DATATYPE$", str(i_tensor_dt))
- driver = driver.replace("$INPUT_SHAPE_NORMAL$", str(i_tensor_shape_normal))
- driver = driver.replace("$INPUT_SHAPE_FOLDED$", str(i_tensor_shape_folded))
- driver = driver.replace("$INPUT_SHAPE_PACKED$", str(i_tensor_shape_packed))
+ driver = driver.replace("$INPUT_SHAPE_NORMAL$", mss(i_tensor_shape_normal))
+ driver = driver.replace("$INPUT_SHAPE_FOLDED$", mss(i_tensor_shape_folded))
+ driver = driver.replace("$INPUT_SHAPE_PACKED$", mss(i_tensor_shape_packed))
driver = driver.replace("$OUTPUT_FINN_DATATYPE$", str(o_tensor_dt))
- driver = driver.replace("$OUTPUT_SHAPE_NORMAL$", str(o_tensor_shape_normal))
- driver = driver.replace("$OUTPUT_SHAPE_FOLDED$", str(o_tensor_shape_folded))
- driver = driver.replace("$OUTPUT_SHAPE_PACKED$", str(o_tensor_shape_packed))
+ driver = driver.replace("$OUTPUT_SHAPE_NORMAL$", mss(o_tensor_shape_normal))
+ driver = driver.replace("$OUTPUT_SHAPE_FOLDED$", mss(o_tensor_shape_folded))
+ driver = driver.replace("$OUTPUT_SHAPE_PACKED$", mss(o_tensor_shape_packed))
with open(driver_py, "w") as f:
f.write(driver)
diff --git a/src/finn/transformation/fpgadataflow/make_pynq_proj.py b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
index 41498edc078506b0d6db87f28dce558fdf5a1aa4..9fe5781ecd3aa885281bde772571d307ad0669c8 100644
--- a/src/finn/transformation/fpgadataflow/make_pynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_pynq_proj.py
@@ -70,13 +70,12 @@ class MakePYNQProject(Transformation):
# collect list of all IP dirs
ip_dirs = ["list"]
for node in model.graph.node:
- ip_dir_attribute = get_by_name(node.attribute, "ipgen_path")
+ ip_dir_attribute = get_by_name(node.attribute, "ip_path")
assert (
ip_dir_attribute is not None
- ), """Node attribute "ipgen_path" is
+ ), """Node attribute "ip_path" is
empty. Please run transformation HLSSynth_ipgen first."""
ip_dir_value = ip_dir_attribute.s.decode("UTF-8")
- ip_dir_value += "/sol1/impl/ip"
assert os.path.isdir(
ip_dir_value
), """The directory that should
@@ -109,16 +108,23 @@ class MakePYNQProject(Transformation):
out_if_name = "out_r_0"
clk_name = "ap_clk_0"
nrst_name = "ap_rst_n_0"
+ axi_lite_if_name = "s_axi_control_0"
vivado_ip_cache = os.getenv("VIVADO_IP_CACHE", default="")
+ # TODO get from Transformation arg or metadata_prop
+ fclk_mhz = 100.0
# create a temporary folder for the project
vivado_pynq_proj_dir = make_build_dir(prefix="vivado_pynq_proj_")
model.set_metadata_prop("vivado_pynq_proj", vivado_pynq_proj_dir)
+ # filename for the synth utilization report
+ synth_report_filename = vivado_pynq_proj_dir + "/synth_report.xml"
+ model.set_metadata_prop("vivado_synth_rpt", synth_report_filename)
ip_config_tcl = templates.ip_config_tcl_template % (
vivado_pynq_proj_dir,
ip_dirs_str,
vivado_pynq_proj_dir,
+ synth_report_filename,
vivado_stitch_vlnv,
in_bytes,
out_bytes,
@@ -126,7 +132,9 @@ class MakePYNQProject(Transformation):
out_if_name,
clk_name,
nrst_name,
+ axi_lite_if_name,
vivado_ip_cache,
+ fclk_mhz,
)
with open(vivado_pynq_proj_dir + "/ip_config.tcl", "w") as f:
diff --git a/src/finn/transformation/fpgadataflow/prepare_rtlsim.py b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py
new file mode 100644
index 0000000000000000000000000000000000000000..baac3e7bdf5ac936a963ac8346f01638657b042c
--- /dev/null
+++ b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py
@@ -0,0 +1,73 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import finn.custom_op.registry as registry
+from finn.util.fpgadataflow import is_fpgadataflow_node
+
+from finn.transformation import NodeLocalTransformation
+
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
+
+
+class PrepareRTLSim(NodeLocalTransformation):
+ """For a graph with generated RTL sources (after HLSSynth_IPGen), create a
+ Verilator emulation library for each node to prepare for rtlsim
+ execution and set the rtlsim_so property to the path to the generated
+ emulation library.
+
+ To use these libraries, exec_mode must be set to "rtlsim" (using
+ SetExecMode) and the model has to be executed using execute_onnx() from
+ finn.core.onnx_exec
+
+ * num_workers (int or None) number of parallel workers, see documentation in
+ NodeLocalTransformation for more details.
+ """
+
+ def __init__(self, num_workers=None):
+ super().__init__(num_workers=num_workers)
+
+ def applyNodeLocal(self, node):
+ op_type = node.op_type
+ if is_fpgadataflow_node(node) is True:
+ try:
+ # lookup op_type in registry of CustomOps
+ inst = registry.custom_op[op_type](node)
+ inst.prepare_rtlsim()
+ # ensure that executable path is now set
+ assert (
+ inst.get_nodeattr("rtlsim_so") != ""
+ ), "Failed to prepare RTLSim, no rtlsim_so attribute found."
+ except KeyError:
+ # exception if op_type is not supported
+ raise Exception(
+ "Custom op_type %s is currently not supported." % op_type
+ )
+ return (node, False)
diff --git a/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py b/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py
index dc0a17893d9d9aa8f25fa7ca67242fca94810e3d..e63ae4e0203188d9664f432f75e36994e8a71ac5 100644
--- a/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py
+++ b/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py
@@ -29,7 +29,7 @@
import os
import finn.custom_op.registry as registry
-import finn.util.basic as util
+from finn.util.fpgadataflow import is_fpgadataflow_node
from finn.transformation import Transformation
@@ -42,29 +42,27 @@ class ReplaceVerilogRelPaths(Transformation):
def apply(self, model):
for node in model.graph.node:
op_type = node.op_type
- if node.domain == "finn":
- backend_attribute = util.get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- try:
- # lookup op_type in registry of CustomOps
- inst = registry.custom_op[op_type](node)
- # find the IP gen dir
- ipgen_path = inst.get_nodeattr("ipgen_path")
- if ipgen_path is not None and os.path.isdir(ipgen_path):
- for dname, dirs, files in os.walk(ipgen_path):
- for fname in files:
- if fname.endswith(".v"):
- fpath = os.path.join(dname, fname)
- with open(fpath, "r") as f:
- s = f.read()
- old = '$readmemh(".'
- new = '$readmemh("%s' % dname
- s = s.replace(old, new)
- with open(fpath, "w") as f:
- f.write(s)
- except KeyError:
- pass
+ if is_fpgadataflow_node(node) is True:
+ try:
+ # lookup op_type in registry of CustomOps
+ inst = registry.custom_op[op_type](node)
+ # find the IP gen dir
+ ipgen_path = inst.get_nodeattr("ipgen_path")
+ if ipgen_path is not None and os.path.isdir(ipgen_path):
+ for dname, dirs, files in os.walk(ipgen_path):
+ for fname in files:
+ if fname.endswith(".v"):
+ fpath = os.path.join(dname, fname)
+ with open(fpath, "r") as f:
+ s = f.read()
+ old = '$readmemh(".'
+ new = '$readmemh("%s' % dname
+ s = s.replace(old, new)
+ old = '"./'
+ new = '"%s/' % dname
+ s = s.replace(old, new)
+ with open(fpath, "w") as f:
+ f.write(s)
+ except KeyError:
+ pass
return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/set_exec_mode.py b/src/finn/transformation/fpgadataflow/set_exec_mode.py
index 1f9c4c42189950e456da2dda77dee98fda49d522..83dda7ceccfd26fa1c43ab517ade2e19ccae4a61 100644
--- a/src/finn/transformation/fpgadataflow/set_exec_mode.py
+++ b/src/finn/transformation/fpgadataflow/set_exec_mode.py
@@ -27,7 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import finn.custom_op.registry as registry
-import finn.util.basic as util
+from finn.util.fpgadataflow import is_fpgadataflow_node
from finn.transformation import Transformation
@@ -42,25 +42,20 @@ class SetExecMode(Transformation):
def apply(self, model):
for node in model.graph.node:
op_type = node.op_type
- if node.domain == "finn":
- backend_attribute = util.get_by_name(node.attribute, "backend")
- if backend_attribute is None:
- continue
- backend_value = backend_attribute.s.decode("UTF-8")
- if backend_value == "fpgadataflow":
- try:
- # lookup op_type in registry of CustomOps
- inst = registry.custom_op[op_type](node)
- # set sim_mode accordingly to argument mode
- inst.set_nodeattr("exec_mode", self.mode)
- # ensure that sim_mode is now set
- assert (
- inst.get_nodeattr("exec_mode") != ""
- ), """Transformation
+ if is_fpgadataflow_node(node) is True:
+ try:
+ # lookup op_type in registry of CustomOps
+ inst = registry.custom_op[op_type](node)
+ # set sim_mode accordingly to argument mode
+ inst.set_nodeattr("exec_mode", self.mode)
+ # ensure that sim_mode is now set
+ assert (
+ inst.get_nodeattr("exec_mode") != ""
+ ), """Transformation
was not successful. Node attribute "exec_mode" is not set"""
- except KeyError:
- # exception if op_type is not supported
- raise Exception(
- "Custom op_type %s is currently not supported." % op_type
- )
+ except KeyError:
+ # exception if op_type is not supported
+ raise Exception(
+ "Custom op_type %s is currently not supported." % op_type
+ )
return (model, False)
diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
index edbf28c4e9d49129d22da12985f3b8c003e3d745..55a5af2ad887e4a8cfa5e3836bef00f2defe7284 100644
--- a/src/finn/transformation/fpgadataflow/templates.py
+++ b/src/finn/transformation/fpgadataflow/templates.py
@@ -26,6 +26,8 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# flake8: noqa
+
# template for the PYNQ shell integration configuration tcl script
ip_config_tcl_template = """
variable config_ip_repo
@@ -35,9 +37,12 @@ variable config_ip_bytes_out
variable config_ip_axis_name_in
variable config_ip_axis_name_out
variable config_ip_use_axilite
+variable config_ip_axilite_name
variable config_ip_project_dir
variable config_output_products_dir
variable config_remote_cache
+variable config_util_report_filename
+variable config_ip_fclk
# for arguments involving paths below: use absolute paths or relative to the
# platform/overlay/bitstream folder
@@ -47,6 +52,8 @@ set config_ip_project_dir %s
set config_ip_repo %s
# where the produced bitfile and .hwh file will be placed
set config_output_products_dir %s
+# where the synth util XML report will be written
+set config_util_report_filename %s
# non-path arguments
# VLNV of the IP block
@@ -64,9 +71,13 @@ set config_ip_clk_name %s
# the name of the active-low reset signal
set config_ip_nrst_name %s
# whether the IP needs an AXI Lite interface for control
-set config_ip_use_axilite 0
+set config_ip_use_axilite 1
+# name of AXI Lite interface
+set config_ip_axilite_name %s
# Vivado OOC IP cache
set config_remote_cache "%s"
+# clock frequency
+set config_ip_fclk %f
"""
call_pynqshell_makefile_template = """
@@ -79,64 +90,156 @@ cd %s
"""
pynq_driver_template = """
+import argparse
+
from pynq import Overlay
import numpy as np
from pynq import allocate
+import time
from finn.util.data_packing import (
finnpy_to_packed_bytearray,
packed_bytearray_to_finnpy
)
from finn.core.datatype import DataType
-bitfile_path = "resizer.bit"
-ol = Overlay(bitfile_path)
-dma=ol.axi_dma_0
-
-# declare input/output types and shapes for the accelerator
-# input FINN DataType
-idt = $INPUT_FINN_DATATYPE$
-# normal, folded and packed input shapes
-ishape_normal = $INPUT_SHAPE_NORMAL$
-ishape_folded = $INPUT_SHAPE_FOLDED$
-ishape_packed = $INPUT_SHAPE_PACKED$
-# output FINN DataType
-odt = $OUTPUT_FINN_DATATYPE$
-# normal, folded and packed output shapes
-oshape_normal = $OUTPUT_SHAPE_NORMAL$
-oshape_folded = $OUTPUT_SHAPE_FOLDED$
-oshape_packed = $OUTPUT_SHAPE_PACKED$
-
-# load desired input .npy file
-ibuf_normal = np.load("input.npy")
-# ensure that shape is as expected
-assert ibuf_normal.shape == ishape_normal
-# convert to folded form
-ibuf_folded = ibuf_normal.reshape(ishape_folded)
-
-# pack the input buffer, reversing both SIMD dim and endianness
-ibuf_packed = finnpy_to_packed_bytearray(
- ibuf_folded, idt, reverse_endian=True, reverse_inner=True
-)
-# allocate a PYNQ buffer for the packed input buffer
-ibuf_packed_device = allocate(shape=ishape_packed, dtype=np.uint8)
-# copy the packed data into the PYNQ buffer
-# TODO optimization: pack directly into the PYNQ buffer?
-np.copyto(ibuf_packed_device, ibuf_packed)
-
-# allocate a PYNQ buffer for the returned packed output buffer
-obuf_packed = allocate(shape=oshape_packed, dtype=np.uint8)
-
-# set up the DMA and wait until all transfers complete
-dma.sendchannel.transfer(ibuf_packed_device)
-dma.recvchannel.transfer(obuf_packed)
-dma.sendchannel.wait()
-dma.recvchannel.wait()
-
-# unpack the packed output buffer from accelerator
-obuf_folded = packed_bytearray_to_finnpy(
- obuf_packed, odt, oshape_folded, reverse_endian=True, reverse_inner=True
-)
-# convert to normal reshape and save
-obuf_normal = obuf_folded.reshape(oshape_normal)
-np.save("output.npy", obuf_normal)
+class RemoteTest():
+ def __init__(
+ self,
+ exec_mode,
+ N,
+ bitfile="resizer.bit",
+ inputfile="input.npy",
+ outputfile="output.npy"):
+
+ self.exec_mode = exec_mode
+ self.N = N
+ self.inputfile = inputfile
+ self.outputfile = outputfile
+ self.ol = Overlay(bitfile)
+ self.dma = self.ol.axi_dma_0
+ self.ctrl_regs = self.ol.resize_accel_0
+ self.ishape_packed = $INPUT_SHAPE_PACKED$
+ self.oshape_packed = $OUTPUT_SHAPE_PACKED$
+ # neuron folding factor of output = iterations per sample
+ self.itersPerSample = self.oshape_packed[-2]
+ # AXI lite register offset for number of iterations
+ # used by TLastMarker to signal end of transmission for AXI CDMA
+ self.REG_OFFSET_NUM_ITERS = 0x10
+
+ def load_input(self):
+ N = self.N
+ ishape_normal = $INPUT_SHAPE_NORMAL$
+ # load desired input .npy file
+ ibuf_normal = np.load(self.inputfile)
+ # ensure that shape is as expected
+ assert ibuf_normal.shape == ishape_normal
+ return ibuf_normal
+
+ def pack_input(self, ibuf_normal):
+ N = self.N
+ # input FINN DataType
+ idt = $INPUT_FINN_DATATYPE$
+ ishape_folded = $INPUT_SHAPE_FOLDED$
+ # convert to folded form
+ ibuf_folded = ibuf_normal.reshape(ishape_folded)
+ # pack the input buffer, reversing both SIMD dim and endianness
+ ibuf_packed = finnpy_to_packed_bytearray(
+ ibuf_folded, idt, reverse_endian=True, reverse_inner=True
+ )
+ return ibuf_packed
+
+ def unpack_output(self, obuf_packed):
+ N = self.N
+ # output FINN DataType
+ odt = $OUTPUT_FINN_DATATYPE$
+ oshape_folded = $OUTPUT_SHAPE_FOLDED$
+ # unpack the packed output buffer from accelerator
+ obuf_folded = packed_bytearray_to_finnpy(
+ obuf_packed, odt, oshape_folded, reverse_endian=True, reverse_inner=True
+ )
+ return obuf_folded
+
+ def save_output(self, obuf_folded):
+ N = self.N
+ # convert to normal reshape and save
+ oshape_normal = $OUTPUT_SHAPE_NORMAL$
+ obuf_normal = obuf_folded.reshape(oshape_normal)
+ np.save(self.outputfile, obuf_normal)
+
+ def allocate_pynqbuffer(self, shape, data=None):
+ buf_device = allocate(shape=shape, dtype=np.uint8)
+
+ # if necessary copy the packed data into the PYNQ buffer
+ # TODO optimization: pack directly into the PYNQ buffer?
+ if data is not None:
+ np.copyto(buf_device, data)
+
+ return buf_device
+
+
+ def run_nw(self):
+ exec_mode = self.exec_mode
+ if exec_mode == "remote_pynq":
+ ibuf_normal = self.load_input()
+ ibuf_packed = self.pack_input(ibuf_normal)
+ elif exec_mode != "throughput_test":
+ raise Exception("Exec mode has to be set to remote_pynq or throughput_test")
+
+ # set up TLastMarker with correct num. samples
+ self.ctrl_regs.write(self.REG_OFFSET_NUM_ITERS, N*self.itersPerSample)
+
+ # allocate a PYNQ buffer for the packed input buffer
+ if exec_mode == "remote_pynq":
+ ibuf_packed_device = self.allocate_pynqbuffer(self.ishape_packed, ibuf_packed)
+ else:
+ ibuf_packed_device = self.allocate_pynqbuffer(self.ishape_packed)
+
+ # allocate a PYNQ buffer for the returned packed output buffer
+ obuf_packed = self.allocate_pynqbuffer(self.oshape_packed)
+
+ if exec_mode == "throughput_test":
+ # measure runtime of network
+ start = time.time()
+ res={}
+
+ # set up the DMA and wait until all transfers complete
+ dma = self.dma
+ dma.sendchannel.transfer(ibuf_packed_device)
+ dma.recvchannel.transfer(obuf_packed)
+ dma.sendchannel.wait()
+ dma.recvchannel.wait()
+
+
+ if exec_mode == "throughput_test":
+ end = time.time()
+ runtime = end - start
+ res["runtime[ms]"] = runtime*1000
+ res["throughput[images/s]"] = N / runtime
+ res["DRAM_in_bandwidth[Mb/s]"] = np.prod(self.ishape_packed)*0.000001 / runtime
+ res["DRAM_out_bandwidth[Mb/s]"] = np.prod(self.oshape_packed)*0.000001 / runtime
+ file = open("nw_metrics.txt", "w")
+ file.write(str(res))
+ file.close()
+ else:
+ obuf_folded = self.unpack_output(obuf_packed)
+ self.save_output(obuf_folded)
+
+
+if __name__ == "__main__":
+ parser = argparse.ArgumentParser(description='Set exec mode, batchsize N, bitfile name, inputfile name and outputfile name')
+ parser.add_argument('exec_mode', help='Please select functional verification ("remote_pynq") or throughput test ("throughput_test")')
+ parser.add_argument('N', help='number of samples for inference', type=int)
+ parser.add_argument('bitfile', default="resizer.bit")
+ parser.add_argument('inputfile', default="input.npy")
+ parser.add_argument('outputfile', default="output.npy")
+ args = parser.parse_args()
+ exec_mode = args.exec_mode
+ N = args.N
+ bitfile = args.bitfile
+ inputfile = args.inputfile
+ outputfile = args.outputfile
+
+ Test = RemoteTest(exec_mode, N, bitfile, inputfile, outputfile)
+ Test.run_nw()
+
"""
diff --git a/src/finn/transformation/general.py b/src/finn/transformation/general.py
index 176772be902474b1ca0ff96ec6b8f88304749550..53c73e1dc4fe0bfab53e3f126add992cb338c11d 100644
--- a/src/finn/transformation/general.py
+++ b/src/finn/transformation/general.py
@@ -82,7 +82,7 @@ class GiveReadableTensorNames(Transformation):
class ConvertSubToAdd(Transformation):
- """Convert sub nodes to add nodes of appropriate sign."""
+ """Convert subtract-a-constant nodes to add-a-constant nodes."""
def apply(self, model):
graph = model.graph
@@ -94,3 +94,18 @@ class ConvertSubToAdd(Transformation):
model.set_initializer(n.input[1], -A)
# return model_was_changed = False as single iteration is always enough
return (model, False)
+
+
+class ConvertDivToMul(Transformation):
+ """Convert divide by constant nodes to multiply by constant nodes."""
+
+ def apply(self, model):
+ graph = model.graph
+ for n in graph.node:
+ if n.op_type == "Div":
+ A = model.get_initializer(n.input[1])
+ if A is not None:
+ n.op_type = "Mul"
+ model.set_initializer(n.input[1], 1.0 / A)
+ # return model_was_changed = False as single iteration is always enough
+ return (model, False)
diff --git a/src/finn/transformation/infer_datatypes.py b/src/finn/transformation/infer_datatypes.py
index 4c4620da472c5d34985be4054c36099bcc6c811d..1acd4e3abe2d77248810cf15c15475e806a3bd32 100644
--- a/src/finn/transformation/infer_datatypes.py
+++ b/src/finn/transformation/infer_datatypes.py
@@ -34,6 +34,7 @@ from finn.transformation import Transformation
def _infer_node_datatype(model, node):
"""Infer output datatype(s) for a particular node. Returns True if any
changes were made."""
+ dt_identity_optypes = ["Reshape", "Transpose"]
idtypes = list(map(lambda x: model.get_tensor_datatype(x), node.input))
odtypes = list(map(lambda x: model.get_tensor_datatype(x), node.output))
op_type = node.op_type
@@ -63,6 +64,10 @@ def _infer_node_datatype(model, node):
else:
odtype = DataType.UINT32
model.set_tensor_datatype(node.output[0], odtype)
+ elif node.op_type in dt_identity_optypes:
+ # set output dtype = input dtype
+ idtype = model.get_tensor_datatype(node.input[0])
+ model.set_tensor_datatype(node.output[0], idtype)
else:
# unknown, assume node produces float32 outputs
for o in node.output:
diff --git a/src/finn/transformation/infer_shapes.py b/src/finn/transformation/infer_shapes.py
index 74a3e62e39ea9e60139b9385327c493ffaa25880..361ef7f6ad46c23faa48d50b34d78e38d0823796 100644
--- a/src/finn/transformation/infer_shapes.py
+++ b/src/finn/transformation/infer_shapes.py
@@ -33,7 +33,7 @@ from finn.core.modelwrapper import ModelWrapper
from finn.transformation import Transformation
-def _make_shape_compatible_op(node):
+def _make_shape_compatible_op(node, model):
"""Return a shape-compatible non-FINN op for a given FINN op. Used for
shape inference with custom ops."""
assert node.domain == "finn", 'Node domain is not set to "finn".'
@@ -41,7 +41,7 @@ def _make_shape_compatible_op(node):
try:
# lookup op_type in registry of CustomOps
inst = registry.custom_op[op_type](node)
- return inst.make_shape_compatible_op()
+ return inst.make_shape_compatible_op(model)
except KeyError:
# exception if op_type is not supported
raise Exception("Custom op_type %s is currently not supported." % op_type)
@@ -56,7 +56,7 @@ def _hide_finn_ops(model):
for node in model.graph.node:
node_ind += 1
if node.domain == "finn":
- new_node = _make_shape_compatible_op(node)
+ new_node = _make_shape_compatible_op(node, model)
hidden_ops[str(new_node)] = node
model.graph.node.insert(node_ind, new_node)
model.graph.node.remove(node)
diff --git a/src/finn/transformation/insert_topk.py b/src/finn/transformation/insert_topk.py
new file mode 100644
index 0000000000000000000000000000000000000000..213d2cedf92c0276e33fcf2b50e6966aeee8c847
--- /dev/null
+++ b/src/finn/transformation/insert_topk.py
@@ -0,0 +1,96 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import numpy as np
+
+from onnx import TensorProto
+from onnx import helper as oh
+
+from finn.transformation import Transformation
+from finn.core.datatype import DataType
+
+
+class InsertTopK(Transformation):
+ """Add TopK node at the network output and replace the graph output with
+ the TopK indices."""
+
+ def __init__(self, k=5, axis=-1, largest=1, sorted=1):
+ super().__init__()
+ self.k = k
+ self.axis = axis
+ self.largest = largest
+ self.sorted = sorted
+
+ def apply(self, model):
+ # get name of output tensor
+ graph_out_name = model.graph.output[0].name
+ # find final node
+ final_node = model.find_producer(graph_out_name)
+ # if a top-select op is already present, do nothing
+ if final_node.op_type == "TopK":
+ return (model, False)
+ else:
+ out_shape = model.get_tensor_shape(graph_out_name)
+ out_dtype = model.get_tensor_datatype(graph_out_name)
+ # adjust shape
+ out_shape[self.axis] = self.k
+ # make new buffer
+ k_tensor = np.array([self.k]).astype(np.int64)
+ k_value = oh.make_tensor_value_info(
+ model.make_new_valueinfo_name(), TensorProto.INT64, [1]
+ )
+ topk_values = oh.make_tensor_value_info(
+ model.make_new_valueinfo_name(), TensorProto.FLOAT, out_shape
+ )
+ topk_indices = oh.make_tensor_value_info(
+ model.make_new_valueinfo_name(), TensorProto.INT64, out_shape
+ )
+ model.graph.value_info.append(k_value)
+ model.set_tensor_datatype(k_value.name, out_dtype) # TODO set to int64
+ model.graph.value_info.append(topk_values)
+ model.set_tensor_datatype(topk_values.name, out_dtype)
+ # create and append topk node
+ model.set_initializer(k_value.name, k_tensor)
+ topk_node = oh.make_node(
+ "TopK",
+ inputs=[graph_out_name, k_value.name],
+ outputs=[topk_values.name, topk_indices.name],
+ axis=self.axis,
+ largest=self.largest,
+ sorted=self.sorted,
+ )
+ model.graph.node.append(topk_node)
+ # replace the existing output definition with topk indices
+ model.graph.output.insert(0, topk_indices)
+ model.graph.output.pop(1)
+ # set quantization annotation for indices
+ # minimal output dtype for TopK indices dependens on num. classes
+ # assuming UINT32 is large enough for now (FINN has currently no
+ # DataType.INT64)
+ model.set_tensor_datatype(topk_indices.name, DataType.UINT32)
+ return (model, True)
diff --git a/src/finn/transformation/lower_convs_to_matmul.py b/src/finn/transformation/lower_convs_to_matmul.py
new file mode 100644
index 0000000000000000000000000000000000000000..3da785d8dd21b2c6701bffc8ce3869fb14b237a9
--- /dev/null
+++ b/src/finn/transformation/lower_convs_to_matmul.py
@@ -0,0 +1,133 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from onnx import TensorProto
+from onnx import helper
+
+from finn.transformation import Transformation
+from finn.transformation.infer_shapes import InferShapes
+from finn.util.basic import get_by_name
+
+
+class LowerConvsToMatMul(Transformation):
+ """Replace Conv layers with pairs of Im2Col-MatMul layers, plus Transpose
+ layers to keep the original data layout."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "Conv":
+ graph_modified = True
+ cnv_input = n.input[0]
+ cnv_output = n.output[0]
+ idt = model.get_tensor_datatype(cnv_input)
+ odt = model.get_tensor_datatype(cnv_output)
+ # extract conv parameters
+ k = get_by_name(n.attribute, "kernel_shape").ints[-1]
+ pad = get_by_name(n.attribute, "pads").ints[-1]
+ stride = get_by_name(n.attribute, "strides").ints[-1]
+ weight_name = n.input[1]
+ W_conv = model.get_initializer(weight_name)
+ ifm_ch = W_conv.shape[1]
+ ofm_ch = W_conv.shape[0]
+ ifm_dim = model.get_tensor_shape(n.input[0])[-1] # assume NCHW
+ ofm_dim = model.get_tensor_shape(n.output[0])[-1] # assume NCHW
+ # reuse conv weights for new matmul weights
+ # conv weights are [OFM][IFM][k][k]
+ # first convert to [OFM][k][k][IFM] (to remain compatible with
+ # finn-hlslib and how it does im2col/sliding window)
+ W_matmul = W_conv.transpose(0, 2, 3, 1)
+ # reshape into [OFM][k*k*IFM] matrix
+ W_matmul = W_matmul.reshape(ofm_ch, ifm_ch * k * k)
+ # transpose to get ONNX-compatible [k*k*IFM][OFM] matrix
+ W_matmul = W_matmul.T
+ model.set_initializer(weight_name, W_matmul)
+ # create new intermediate values
+ inp_trans_out = helper.make_tensor_value_info(
+ model.make_new_valueinfo_name(),
+ TensorProto.FLOAT,
+ (1, ifm_dim, ifm_dim, ifm_ch), # NHWC
+ )
+ graph.value_info.append(inp_trans_out)
+ inp_trans_out = inp_trans_out.name
+ model.set_tensor_datatype(inp_trans_out, idt)
+
+ im2col_out = helper.make_tensor_value_info(
+ model.make_new_valueinfo_name(),
+ TensorProto.FLOAT,
+ (1, ofm_dim, ofm_dim, ifm_ch * k * k),
+ )
+ graph.value_info.append(im2col_out)
+ im2col_out = im2col_out.name
+ model.set_tensor_datatype(im2col_out, idt)
+
+ matmul_out = helper.make_tensor_value_info(
+ model.make_new_valueinfo_name(),
+ TensorProto.FLOAT,
+ (1, ofm_dim, ofm_dim, ofm_ch),
+ )
+ graph.value_info.append(matmul_out)
+ matmul_out = matmul_out.name
+ model.set_tensor_datatype(matmul_out, odt)
+
+ # create new nodes
+ # NCHW -> NHWC
+ inp_trans_node = helper.make_node(
+ "Transpose", [cnv_input], [inp_trans_out], perm=[0, 2, 3, 1]
+ )
+ # lower input tensor
+ im2col_node = helper.make_node(
+ "Im2Col",
+ [inp_trans_out],
+ [im2col_out],
+ domain="finn",
+ stride=stride,
+ kernel_size=k,
+ pad_amount=pad,
+ input_shape="(1,{},{},{})".format(ifm_dim, ifm_dim, ifm_ch),
+ )
+ # do matmul
+ matmul_node = helper.make_node(
+ "MatMul", [im2col_out, weight_name], [matmul_out]
+ )
+ # NHWC -> NCHW
+ out_trans_node = helper.make_node(
+ "Transpose", [matmul_out], [cnv_output], perm=[0, 3, 1, 2]
+ )
+ # insert nodes where the conv is to preserve topological ordering
+ graph.node.insert(node_ind, inp_trans_node)
+ graph.node.insert(node_ind + 1, im2col_node)
+ graph.node.insert(node_ind + 2, matmul_node)
+ graph.node.insert(node_ind + 3, out_trans_node)
+ # remove old nodes
+ graph.node.remove(n)
+ model = model.transform(InferShapes())
+ return (model, graph_modified)
diff --git a/src/finn/transformation/move_reshape.py b/src/finn/transformation/move_reshape.py
new file mode 100644
index 0000000000000000000000000000000000000000..6a30fd93cc0bdc322b6ec7d892d42d3c3ca96fd6
--- /dev/null
+++ b/src/finn/transformation/move_reshape.py
@@ -0,0 +1,40 @@
+from finn.transformation import Transformation
+from finn.util.basic import get_by_name
+
+
+def _is_fpgadataflow_node(node):
+ if node is not None:
+ if node.domain == "finn":
+ n_backend = get_by_name(node.attribute, "backend")
+ if n_backend is None:
+ return False
+ backend_value = n_backend.s.decode("UTF-8")
+ if backend_value == "fpgadataflow":
+ return True
+ else:
+ return False
+ else:
+ return False
+
+
+class MoveReshape(Transformation):
+ """Removes a node that implements a (1, -1) reshape if it is
+ between two fpgadataflow nodes"""
+
+ def apply(self, model):
+
+ graph = model.graph
+ graph_modified = False
+ for n in graph.node:
+ if n.op_type == "Reshape":
+ graph_modified = True
+ shape = model.get_initializer(n.input[1])
+ if (shape == [1, -1]).all():
+ producer = model.find_producer(n.input[0])
+ if _is_fpgadataflow_node(producer) is True:
+ consumer = model.find_consumer(n.output[0])
+ if _is_fpgadataflow_node(consumer) is True:
+ consumer.input[0] = n.input[0]
+ graph.node.remove(n)
+
+ return (model, graph_modified)
diff --git a/src/finn/transformation/streamline/__init__.py b/src/finn/transformation/streamline/__init__.py
index b5a5bd2f65b41fdb1d0e1c048949c206adfa357b..c9c73fa4c8303ee28bc1cc6aee879d633740e01e 100644
--- a/src/finn/transformation/streamline/__init__.py
+++ b/src/finn/transformation/streamline/__init__.py
@@ -30,6 +30,7 @@ from finn.transformation import Transformation
from finn.transformation.infer_datatypes import InferDataTypes
from finn.transformation.general import (
ConvertSubToAdd,
+ ConvertDivToMul,
GiveReadableTensorNames,
GiveUniqueNodeNames,
)
@@ -39,6 +40,7 @@ from finn.transformation.streamline.absorb import (
AbsorbMulIntoMultiThreshold,
FactorOutMulSignMagnitude,
Absorb1BitMulIntoMatMul,
+ Absorb1BitMulIntoConv,
)
from finn.transformation.streamline.collapse_repeated import (
@@ -50,6 +52,8 @@ from finn.transformation.streamline.reorder import (
MoveAddPastMul,
MoveScalarMulPastMatMul,
MoveScalarAddPastMatMul,
+ MoveScalarAddPastConv,
+ MoveScalarMulPastConv,
)
from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds
@@ -63,11 +67,14 @@ class Streamline(Transformation):
def apply(self, model):
streamline_transformations = [
ConvertSubToAdd(),
+ ConvertDivToMul(),
BatchNormToAffine(),
ConvertSignToThres(),
MoveAddPastMul(),
MoveScalarAddPastMatMul(),
+ MoveScalarAddPastConv(),
MoveScalarMulPastMatMul(),
+ MoveScalarMulPastConv(),
MoveAddPastMul(),
CollapseRepeatedAdd(),
CollapseRepeatedMul(),
@@ -75,6 +82,7 @@ class Streamline(Transformation):
FactorOutMulSignMagnitude(),
AbsorbMulIntoMultiThreshold(),
Absorb1BitMulIntoMatMul(),
+ Absorb1BitMulIntoConv(),
RoundAndClipThresholds(),
]
for trn in streamline_transformations:
diff --git a/src/finn/transformation/streamline/absorb.py b/src/finn/transformation/streamline/absorb.py
index eb5845f198bc636e85d395b7bdf32e01b0222cf2..0d709297a9132b15b51435b7ab4b51ce55c7e9f3 100644
--- a/src/finn/transformation/streamline/absorb.py
+++ b/src/finn/transformation/streamline/absorb.py
@@ -31,6 +31,9 @@ from onnx import helper as oh
from finn.core.datatype import DataType
from finn.transformation import Transformation
+from finn.util.basic import get_by_name
+from finn.custom_op.registry import getCustomOp
+from finn.transformation.infer_datatypes import InferDataTypes
class AbsorbAddIntoMultiThreshold(Transformation):
@@ -55,7 +58,8 @@ class AbsorbAddIntoMultiThreshold(Transformation):
start_name = n.input[0]
# we can only absorb 0d or 1d adds
is_scalar = A.ndim == 0 or all(x == 1 for x in A.shape)
- is_1d = A.ndim > 0 and np.prod(A.shape) == A.shape[-1]
+ actual_ndims = len(tuple(filter(lambda x: x > 1, A.shape)))
+ is_1d = actual_ndims == 1
if is_scalar or is_1d:
Tnew = T - A.reshape(-1, 1)
# Tnew = T - A.reshape(-1, T.shape[1])
@@ -85,7 +89,8 @@ class AbsorbMulIntoMultiThreshold(Transformation):
assert A is not None, "Initializer for mul weights is not set."
is_signed = (A < 0).any()
is_scalar = A.ndim == 0 or all(x == 1 for x in A.shape)
- is_1d = A.ndim > 0 and np.prod(A.shape) == A.shape[-1]
+ actual_ndims = len(tuple(filter(lambda x: x > 1, A.shape)))
+ is_1d = actual_ndims == 1
consumer = model.find_consumer(n.output[0])
if consumer is not None and consumer.op_type == "MultiThreshold":
if not is_signed and (is_1d or is_scalar):
@@ -122,7 +127,8 @@ class FactorOutMulSignMagnitude(Transformation):
A = model.get_initializer(mul_weight_name)
assert A is not None, "Initializer for mul weights is not set."
is_scalar = np.prod(A.shape) == 1
- is_1d = len(A.shape) == 2 and A.shape[0] == 1
+ actual_ndims = len(tuple(filter(lambda x: x > 1, A.shape)))
+ is_1d = actual_ndims == 1
is_not_bipolar = (
model.get_tensor_datatype(mul_weight_name) != DataType.BIPOLAR
)
@@ -161,6 +167,7 @@ class Absorb1BitMulIntoMatMul(Transformation):
if n.op_type == "MatMul":
matmul_weight_name = n.input[1]
W = model.get_initializer(matmul_weight_name)
+ Wdt = model.get_tensor_datatype(matmul_weight_name)
assert W is not None, "Initializer for matmul weights is not set."
consumer = model.find_consumer(n.output[0])
if consumer is not None and consumer.op_type == "Mul":
@@ -174,8 +181,104 @@ class Absorb1BitMulIntoMatMul(Transformation):
Wnew.shape == W.shape
), """Shape of new weights is not
the same as the shape of the weight matrix before."""
- model.set_initializer(matmul_weight_name, Wnew)
- n.output[0] = consumer.output[0]
- graph.node.remove(consumer)
- graph_modified = True
+ check_fxn = np.vectorize(lambda x: Wdt.allowed(x))
+ # only absorb if permitted by W datatype
+ if check_fxn(Wnew).all():
+ model.set_initializer(matmul_weight_name, Wnew)
+ n.output[0] = consumer.output[0]
+ graph.node.remove(consumer)
+ graph_modified = True
+ return (model, graph_modified)
+
+
+class Absorb1BitMulIntoConv(Transformation):
+ """Absorb bipolar or binary multiplications into the preciding convolution."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "Conv":
+ conv_weight_name = n.input[1]
+ W = model.get_initializer(conv_weight_name)
+ Wdt = model.get_tensor_datatype(conv_weight_name)
+ assert W is not None, "Initializer for conv weights is not set."
+ consumer = model.find_consumer(n.output[0])
+ if consumer is not None and consumer.op_type == "Mul":
+ mul_weight_name = consumer.input[1]
+ A = model.get_initializer(mul_weight_name)
+ assert A is not None, "Initializer for mul weights is not set."
+ is_1bit = model.get_tensor_datatype(mul_weight_name).bitwidth() == 1
+ is_scalar = np.prod(A.shape) == 1
+ actual_ndims = len(tuple(filter(lambda x: x > 1, A.shape)))
+ is_1d = actual_ndims == 1
+ if is_1bit and (is_1d or is_scalar):
+ # move the mul to the OFM position, since the mul is
+ # applied on the outputs channelwise or as scalar
+ Wnew = A.reshape(-1, 1, 1, 1) * W
+ assert (
+ Wnew.shape == W.shape
+ ), """Shape of new weights is not
+ the same as the shape of the conv weights before."""
+ check_fxn = np.vectorize(lambda x: Wdt.allowed(x))
+ # only absorb if permitted by W datatype
+ if check_fxn(Wnew).all():
+ model.set_initializer(conv_weight_name, Wnew)
+ n.output[0] = consumer.output[0]
+ graph.node.remove(consumer)
+ graph_modified = True
+ return (model, graph_modified)
+
+
+class AbsorbTransposeIntoMultiThreshold(Transformation):
+ """Change (NHWCTranpose -> MultiThreshold -> NCHWTranspose) to (MultiThreshold)
+ with NHWC mode."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "Transpose":
+ perms = list(get_by_name(n.attribute, "perm").ints)
+ if perms == [0, 3, 1, 2]:
+ mt_cand = model.find_consumer(n.output[0])
+ if mt_cand.op_type == "MultiThreshold":
+ final_t_cand = model.find_consumer(mt_cand.output[0])
+ if final_t_cand.op_type == "Transpose":
+ perms = list(
+ get_by_name(final_t_cand.attribute, "perm").ints
+ )
+ if perms == [0, 2, 3, 1]:
+ mt = getCustomOp(mt_cand)
+ mt.set_nodeattr("data_layout", "NHWC")
+ # get rid of tranpose nodes, wire MT directly
+ mt_cand.input[0] = n.input[0]
+ mt_cand.output[0] = final_t_cand.output[0]
+ graph.node.remove(n)
+ graph.node.remove(final_t_cand)
+ graph_modified = True
+ elif final_t_cand.op_type == "Reshape":
+ oshape = model.get_tensor_shape(final_t_cand.output[0])
+ if len(oshape) == 2:
+ # transition to FC part, can still use NHWC
+ mt = getCustomOp(mt_cand)
+ mt.set_nodeattr("data_layout", "NHWC")
+ # get rid of first tranpose node
+ mt_cand.input[0] = n.input[0]
+ # fix output shape for MultiThreshold
+ mt_ishape = model.get_tensor_shape(mt_cand.input[0])
+ (b, h, w, c) = mt_ishape
+ assert (
+ h == 1 and w == 1
+ ), """Untested spatial dim
+ in conv->fc transition, proceed with caution!"""
+ model.set_tensor_shape(mt_cand.output[0], mt_ishape)
+ graph.node.remove(n)
+ graph_modified = True
+ if graph_modified:
+ model = model.transform(InferDataTypes())
return (model, graph_modified)
diff --git a/src/finn/transformation/streamline/reorder.py b/src/finn/transformation/streamline/reorder.py
index db55dc2021a0c9ef8330270aa9eb950dcf66c575..1fd9ce5108bbe9c317f180680febfc088072b98c 100644
--- a/src/finn/transformation/streamline/reorder.py
+++ b/src/finn/transformation/streamline/reorder.py
@@ -31,6 +31,8 @@ from onnx import helper as oh
from finn.transformation import Transformation
from finn.transformation.infer_shapes import InferShapes
+from finn.core.onnx_exec import execute_node
+from finn.util.basic import get_by_name
class MoveAddPastMul(Transformation):
@@ -167,3 +169,136 @@ class MoveScalarAddPastMatMul(Transformation):
graph_modified = True
model = model.transform(InferShapes())
return (model, graph_modified)
+
+
+class MoveScalarAddPastConv(Transformation):
+ """Move scalar add operations past conv operations. We want to have adds
+ next to each other such that they can be collapsed into a single add."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "Add":
+ consumer = model.find_consumer(n.output[0])
+ if consumer is not None and consumer.op_type == "Conv":
+ conv_node = consumer
+ add_node = n
+ add_weight_name = n.input[1]
+ conv_in_name = consumer.input[0]
+ conv_in_shape = model.get_tensor_shape(conv_in_name)
+ A = model.get_initializer(add_weight_name)
+ assert A is not None, "Initializer for add weights is not set."
+ start_name = n.input[0]
+ end_name = consumer.output[0]
+ conv_out_shape = model.get_tensor_shape(end_name)
+ if all(x == 1 for x in A.shape):
+ # create a tensor filled with the add constant, in
+ # the shape expected by the convolution
+ conv_in_const = np.zeros(conv_in_shape, dtype=np.float32)
+ conv_in_const.fill(A.item())
+ # create an execution context and put in const input
+ exec_ctx = model.make_empty_exec_context()
+ exec_ctx[conv_in_name] = conv_in_const
+ # execute the conv node only
+ execute_node(conv_node, exec_ctx, model.graph)
+ # retrieve the conv output
+ Anew = exec_ctx[end_name]
+ # strip out repetition
+ Anew = Anew[0, :, 0, 0].reshape(1, -1, 1, 1)
+ # update the add weight
+ model.set_initializer(add_weight_name, Anew)
+ # rewire add input to be conv input
+ conv_node.input[0] = start_name
+ model.set_tensor_shape(start_name, conv_in_shape)
+ # use old conv input tensor as conv output
+ conv_node.output[0] = conv_in_name
+ model.set_tensor_shape(conv_in_name, conv_out_shape)
+ # use new conv output as new add node input
+ add_node.input[0] = conv_in_name
+ # use old conv output as new add node output
+ add_node.output[0] = end_name
+ # move add node past conv node
+ graph.node.remove(add_node)
+ graph.node.insert(node_ind, add_node)
+ graph_modified = True
+ model = model.transform(InferShapes())
+ return (model, graph_modified)
+
+
+class MoveScalarMulPastConv(Transformation):
+ """Move scalar mul operations past conv operations. We want to have muls
+ next to each other such that they can be collapsed into a single mul."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "Mul":
+ consumer = model.find_consumer(n.output[0])
+ if consumer is not None and consumer.op_type == "Conv":
+ mul_weight_name = n.input[1]
+ A = model.get_initializer(mul_weight_name)
+ assert A is not None, "Initializer for mul weights is not set."
+ conv_node = consumer
+ mul_node = n
+ start_name = mul_node.input[0]
+ conv_in_name = conv_node.input[0]
+ conv_in_shape = model.get_tensor_shape(conv_in_name)
+ conv_out_name = conv_node.output[0]
+ conv_out_shape = model.get_tensor_shape(conv_out_name)
+ if all(x == 1 for x in A.shape):
+ # if the mul is scalar, we can simply swap the order of ops
+ # rewire mul input to be conv input
+ conv_node.input[0] = start_name
+ model.set_tensor_shape(start_name, conv_in_shape)
+ # use old conv input tensor as conv output
+ conv_node.output[0] = conv_in_name
+ model.set_tensor_shape(conv_in_name, conv_out_shape)
+ # use new conv output as new mul node input
+ mul_node.input[0] = conv_in_name
+ # use old conv output as new mul node output
+ mul_node.output[0] = conv_out_name
+ # move add node past conv node
+ graph.node.remove(mul_node)
+ graph.node.insert(node_ind, mul_node)
+ graph_modified = True
+ model = model.transform(InferShapes())
+ return (model, graph_modified)
+
+
+class MakeMaxPoolNHWC(Transformation):
+ """Convert (MaxPool, NHWCTranpose) into (MaxPoolNHWC)."""
+
+ def apply(self, model):
+ graph = model.graph
+ node_ind = 0
+ graph_modified = False
+ for n in graph.node:
+ node_ind += 1
+ if n.op_type == "MaxPool":
+ consumer = model.find_consumer(n.output[0])
+ if consumer is not None and consumer.op_type == "Transpose":
+ perms = list(get_by_name(consumer.attribute, "perm").ints)
+ if perms == [0, 2, 3, 1]:
+ n.op_type = "MaxPoolNHWC"
+ n.domain = "finn"
+ start_name = n.input[0]
+ mid_name = consumer.input[0]
+ end_name = consumer.output[0]
+ (b, c, hi, wi) = model.get_tensor_shape(start_name)
+ (b, c, ho, wo) = model.get_tensor_shape(mid_name)
+ consumer.input[0] = start_name
+ consumer.output[0] = mid_name
+ n.input[0] = mid_name
+ n.output[0] = end_name
+ model.set_tensor_shape(mid_name, (b, hi, wi, c))
+ model.set_tensor_shape(end_name, (b, ho, wo, c))
+ graph.node.remove(consumer)
+ graph.node.insert(node_ind - 1, consumer)
+ graph_modified = True
+ return (model, graph_modified)
diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py
index ecc7cb192177cb2bb57a8d2efdfea91f22a488a1..bc413bf665e96be1d58a5de13b0744fd6a80f855 100644
--- a/src/finn/util/basic.py
+++ b/src/finn/util/basic.py
@@ -40,6 +40,33 @@ from finn.core.datatype import DataType
pynq_part_map = dict()
pynq_part_map["Ultra96"] = "xczu3eg-sbva484-1-e"
pynq_part_map["Pynq-Z1"] = "xc7z020clg400-1"
+pynq_part_map["Pynq-Z2"] = "xc7z020clg400-1"
+pynq_part_map["ZCU104"] = "xczu7ev-ffvc1156-2-e"
+
+
+def get_rtlsim_trace_depth():
+ """Return the trace depth for rtlsim via PyVerilator. Controllable
+ via the RTLSIM_TRACE_DEPTH environment variable. If the env.var. is
+ undefined, the default value of 1 is returned. A trace depth of 1
+ will only show top-level signals and yield smaller .vcd files.
+ """
+
+ try:
+ return int(os.environ["RTLSIM_TRACE_DEPTH"])
+ except KeyError:
+ return 1
+
+
+def get_num_default_workers():
+ """Return the number of workers for parallel transformations. Controllable
+ via the NUM_DEFAULT_WORKERS environment variable. If the env.var. is
+ undefined, the default value of 1 is returned.
+ """
+
+ try:
+ return int(os.environ["NUM_DEFAULT_WORKERS"])
+ except KeyError:
+ return 1
def get_finn_root():
diff --git a/src/finn/util/data_packing.py b/src/finn/util/data_packing.py
index ae98d312e7c5923a572f918430aececf29f3e094..e67638bd1ca81d933fbfbffec9efcd7f84fa961e 100644
--- a/src/finn/util/data_packing.py
+++ b/src/finn/util/data_packing.py
@@ -119,7 +119,9 @@ def npbytearray2hexstring(npbytearray, prefix="0x"):
return prefix + binascii.hexlify(bytearray(npbytearray)).decode("utf-8")
-def pack_innermost_dim_as_hex_string(ndarray, dtype, pad_to_nbits, reverse_inner=False):
+def pack_innermost_dim_as_hex_string(
+ ndarray, dtype, pad_to_nbits, reverse_inner=False, prefix="0x"
+):
"""Pack the innermost dimension of the given numpy ndarray into hex
strings using array2hexstring.
@@ -143,7 +145,9 @@ def pack_innermost_dim_as_hex_string(ndarray, dtype, pad_to_nbits, reverse_inner
ndarray = np.asarray(ndarray, dtype=np.float32)
def fun(x):
- return array2hexstring(x, dtype, pad_to_nbits, reverse=reverse_inner)
+ return array2hexstring(
+ x, dtype, pad_to_nbits, reverse=reverse_inner, prefix=prefix
+ )
return np.apply_along_axis(fun, ndarray.ndim - 1, ndarray)
@@ -228,6 +232,7 @@ def numpy_to_hls_code(
if pack_innermost_dim:
idimlen = ndarray.shape[-1]
idimbits = idimlen * dtype.bitwidth()
+ idimbits = roundup_to_integer_multiple(idimbits, 4)
ndarray = pack_innermost_dim_as_hex_string(ndarray, dtype, idimbits)
hls_dtype = "ap_uint<%d>" % idimbits
ndims = ndarray.ndim
@@ -270,6 +275,7 @@ def npy_to_rtlsim_input(input_file, input_dtype, pad_to_nbits, reverse_inner=Tru
finn.util.basic.pack_innermost_dim_as_hex_string() for more info on how the
packing works. If reverse_inner is set, the innermost dimension will be
reversed prior to packing."""
+ pad_to_nbits = roundup_to_integer_multiple(pad_to_nbits, 4)
if issubclass(type(input_file), np.ndarray):
inp = input_file
elif os.path.isfile(input_file):
@@ -297,6 +303,8 @@ def rtlsim_output_to_npy(
out_array = unpack_innermost_dim_from_hex_string(
output, dtype, shape, packedBits=packedBits, reverse_inner=reverse_inner
)
+ # make copy before saving the array
+ out_array = out_array.copy()
np.save(path, out_array)
return out_array
diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py
index 29607b002bd7d7748d450c84f816606d18fded81..7a404cd53e0fcbc758a960fa2d31792fb6263a18 100644
--- a/src/finn/util/fpgadataflow.py
+++ b/src/finn/util/fpgadataflow.py
@@ -29,7 +29,11 @@
import os
import subprocess
-from pyverilator import PyVerilator
+try:
+ from pyverilator import PyVerilator
+except ModuleNotFoundError:
+ PyVerilator = None
+from finn.util.basic import get_by_name, make_build_dir, get_rtlsim_trace_depth
class IPGenBuilder:
@@ -69,6 +73,9 @@ class IPGenBuilder:
def pyverilate_stitched_ip(model):
"Given a model with stitched IP, return a PyVerilator sim object."
+ if PyVerilator is None:
+ raise ImportError("Installation of PyVerilator is required.")
+
vivado_stitch_proj_dir = model.get_metadata_prop("vivado_stitch_proj")
with open(vivado_stitch_proj_dir + "/all_verilog_srcs.txt", "r") as f:
all_verilog_srcs = f.read().split()
@@ -78,7 +85,13 @@ def pyverilate_stitched_ip(model):
all_verilog_dirs = list(map(file_to_dir, all_verilog_srcs))
top_verilog = model.get_metadata_prop("wrapper_filename")
- sim = PyVerilator.build(top_verilog, verilog_path=all_verilog_dirs)
+ build_dir = make_build_dir("pyverilator_ipstitched_")
+ sim = PyVerilator.build(
+ top_verilog,
+ verilog_path=all_verilog_dirs,
+ build_dir=build_dir,
+ trace_depth=get_rtlsim_trace_depth(),
+ )
return sim
@@ -87,3 +100,16 @@ def pyverilate_get_liveness_threshold_cycles():
the simulation is not finishing and throwing an exception."""
return int(os.getenv("LIVENESS_THRESHOLD", 10000))
+
+
+def is_fpgadataflow_node(node):
+ is_node = False
+ if node is not None:
+ if node.domain == "finn":
+ n_backend = get_by_name(node.attribute, "backend")
+ if n_backend is not None:
+ backend_value = n_backend.s.decode("UTF-8")
+ if backend_value == "fpgadataflow":
+ is_node = True
+
+ return is_node
diff --git a/src/finn/util/test.py b/src/finn/util/test.py
index 428ac3ea63e6913ed12364785b3ebfae527d1fdb..34edc3cacdecc461d1254c35c026c56ff8813549 100644
--- a/src/finn/util/test.py
+++ b/src/finn/util/test.py
@@ -53,7 +53,11 @@ def get_test_model_trained(netname, wbits, abits):
and activations from the FINN Brevitas test networks."""
model_def_fxn = get_test_model_def_fxn(netname)
checkpoint_loc = get_trained_checkpoint(netname, wbits, abits)
- fc = model_def_fxn(weight_bit_width=wbits, act_bit_width=abits, in_bit_width=abits)
+ if netname == "CNV":
+ ibits = 8
+ else:
+ ibits = abits
+ fc = model_def_fxn(weight_bit_width=wbits, act_bit_width=abits, in_bit_width=ibits)
checkpoint = torch.load(checkpoint_loc, map_location="cpu")
fc.load_state_dict(checkpoint["state_dict"])
return fc.eval()
@@ -62,5 +66,9 @@ def get_test_model_trained(netname, wbits, abits):
def get_test_model_untrained(netname, wbits, abits):
"""Returns untrained model specified by input arguments."""
model_def_fxn = get_test_model_def_fxn(netname)
- fc = model_def_fxn(weight_bit_width=wbits, act_bit_width=abits, in_bit_width=abits)
+ if netname == "CNV":
+ ibits = 8
+ else:
+ ibits = abits
+ fc = model_def_fxn(weight_bit_width=wbits, act_bit_width=abits, in_bit_width=ibits)
return fc.eval()
diff --git a/tests/brevitas/test_brevitas_act_export.py b/tests/brevitas/test_brevitas_act_export.py
new file mode 100644
index 0000000000000000000000000000000000000000..08c4a99151d1105ad4258a8d7d6c19cc72da7a99
--- /dev/null
+++ b/tests/brevitas/test_brevitas_act_export.py
@@ -0,0 +1,43 @@
+import numpy as np
+import torch
+import brevitas.onnx as bo
+from brevitas.nn import QuantHardTanh
+from brevitas.core.restrict_val import RestrictValueType
+from brevitas.core.scaling import ScalingImplType
+from models.common import get_quant_type
+import pytest
+from finn.core.modelwrapper import ModelWrapper
+import finn.core.onnx_exec as oxe
+from finn.transformation.infer_shapes import InferShapes
+
+export_onnx_path = "test_act.onnx"
+
+
+@pytest.mark.parametrize("abits", [1, 2, 4, 8])
+@pytest.mark.parametrize("narrow_range", [False, True])
+@pytest.mark.parametrize("max_val", [1.0, 1 - 2 ** (-7)])
+def test_brevitas_act_export(abits, narrow_range, max_val):
+ act_quant_type = get_quant_type(abits)
+ min_val = -1.0
+ ishape = (1, 10)
+ b_act = QuantHardTanh(
+ bit_width=abits,
+ quant_type=act_quant_type,
+ max_val=max_val,
+ min_val=min_val,
+ restrict_scaling_type=RestrictValueType.LOG_FP,
+ scaling_impl_type=ScalingImplType.CONST,
+ narrow_range=narrow_range,
+ )
+ bo.export_finn_onnx(b_act, ishape, export_onnx_path)
+ model = ModelWrapper(export_onnx_path)
+ model = model.transform(InferShapes())
+ inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(
+ np.float32
+ )
+ idict = {model.graph.input[0].name: inp_tensor}
+ odict = oxe.execute_onnx(model, idict, True)
+ produced = odict[model.graph.output[0].name]
+ inp_tensor = torch.from_numpy(inp_tensor).float()
+ expected = b_act.forward(inp_tensor).detach().numpy()
+ assert np.isclose(produced, expected, atol=1e-3).all()
diff --git a/tests/brevitas/test_brevitas_cnv.py b/tests/brevitas/test_brevitas_cnv.py
index 3c9f8d08223ed57d5b7409093f39d1af9613be83..8d21a33f78ca6f1229bdc11e753fc17cdf170242 100644
--- a/tests/brevitas/test_brevitas_cnv.py
+++ b/tests/brevitas/test_brevitas_cnv.py
@@ -28,6 +28,7 @@
import os
import pkg_resources as pk
+import pytest
import brevitas.onnx as bo
import numpy as np
@@ -37,68 +38,34 @@ import finn.core.onnx_exec as oxe
from finn.core.modelwrapper import ModelWrapper
from finn.transformation.fold_constants import FoldConstants
from finn.transformation.infer_shapes import InferShapes
-from finn.util.test import get_test_model_trained, get_test_model_untrained
+from finn.transformation.general import GiveUniqueNodeNames
+from finn.transformation.double_to_single_float import DoubleToSingleFloat
+from finn.util.test import get_test_model_trained
export_onnx_path = "test_output_cnv.onnx"
-def test_brevitas_cnv_w1a1_export():
- cnv = get_test_model_untrained("CNV", 1, 1)
- bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path)
- model = ModelWrapper(export_onnx_path)
- assert model.graph.node[2].op_type == "Sign"
- assert model.graph.node[3].op_type == "Conv"
- conv0_wname = model.graph.node[3].input[1]
- assert list(model.get_initializer(conv0_wname).shape) == [64, 3, 3, 3]
- assert model.graph.node[4].op_type == "Mul"
- os.remove(export_onnx_path)
-
-
-def test_brevitas_cnv_w1a1_export_exec():
- cnv = get_test_model_trained("CNV", 1, 1)
+@pytest.mark.parametrize("abits", [1, 2])
+@pytest.mark.parametrize("wbits", [1, 2])
+def test_brevitas_cnv_export_exec(wbits, abits):
+ if wbits > abits:
+ pytest.skip("No wbits > abits cases at the moment")
+ cnv = get_test_model_trained("CNV", wbits, abits)
bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path)
model = ModelWrapper(export_onnx_path)
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(DoubleToSingleFloat())
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
- model.save(export_onnx_path)
fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
input_tensor = np.load(fn)["arr_0"].astype(np.float32)
assert input_tensor.shape == (1, 3, 32, 32)
# run using FINN-based execution
- input_dict = {"0": input_tensor}
- output_dict = oxe.execute_onnx(model, input_dict)
- produced = output_dict[list(output_dict.keys())[0]]
+ input_dict = {model.graph.input[0].name: input_tensor}
+ output_dict = oxe.execute_onnx(model, input_dict, True)
+ produced = output_dict[model.graph.output[0].name]
# do forward pass in PyTorch/Brevitas
input_tensor = torch.from_numpy(input_tensor).float()
expected = cnv.forward(input_tensor).detach().numpy()
assert np.isclose(produced, expected, atol=1e-3).all()
os.remove(export_onnx_path)
-
-
-def test_brevitas_cnv_w1a1_pytorch():
- # load pretrained weights into CNV-w1a1
- cnv = get_test_model_trained("CNV", 1, 1)
- fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
- input_tensor = np.load(fn)["arr_0"]
- input_tensor = torch.from_numpy(input_tensor).float()
- assert input_tensor.shape == (1, 3, 32, 32)
- # do forward pass in PyTorch/Brevitas
- produced = cnv.forward(input_tensor).detach().numpy()
- expected = np.asarray(
- [
- [
- 3.7939777,
- -2.3108773,
- 0.06898145,
- 0.55185133,
- 0.37939775,
- -1.9659703,
- -0.3104164,
- -2.828238,
- 2.6902752,
- 0.48286998,
- ]
- ],
- dtype=np.float32,
- )
- assert np.isclose(produced, expected, atol=1e-3).all()
diff --git a/tests/brevitas/test_brevitas_fc.py b/tests/brevitas/test_brevitas_fc.py
index 6be2c9a255ead2cd3f9cbcceaca60816060b19bf..db18d91e3590e896e111c9e38bdc4de43872a98c 100644
--- a/tests/brevitas/test_brevitas_fc.py
+++ b/tests/brevitas/test_brevitas_fc.py
@@ -45,13 +45,17 @@ from finn.util.test import get_test_model_trained
export_onnx_path = make_build_dir("test_brevitas_fc_")
-# activation: None or DataType
-@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
-# weight bits
-@pytest.mark.parametrize("wbits", [1])
# act bits
@pytest.mark.parametrize("abits", [1, 2])
+# weight bits
+@pytest.mark.parametrize("wbits", [1, 2])
+# network topology / size
+@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
def test_brevitas_fc_onnx_export_and_exec(size, wbits, abits):
+ if size == "LFC" and wbits == 2 and abits == 2:
+ pytest.skip("No LFC-w2a2 present at the moment")
+ if wbits > abits:
+ pytest.skip("No wbits > abits cases at the moment")
nname = "%s_%dW%dA" % (size, wbits, abits)
finn_onnx = export_onnx_path + "/%s.onnx" % nname
fc = get_test_model_trained(size, wbits, abits)
diff --git a/tests/core/test_custom_onnx_exec.py b/tests/core/test_custom_onnx_exec.py
index 29ef2ee560d498eba04845fc0a6051fd0cae14ab..086681dde0ff029ceaa7d3274bad4d3f15bd32fc 100644
--- a/tests/core/test_custom_onnx_exec.py
+++ b/tests/core/test_custom_onnx_exec.py
@@ -254,3 +254,24 @@ def test_execute_custom_node_multithreshold():
ex_cu_node.execute_custom_node(node_def, execution_context, graph_def)
outputs_scaled = 2.0 * outputs - 1.0
assert (execution_context["out"] == outputs_scaled).all()
+
+ # test the optional data layout option for MultiThreshold
+ node_def = helper.make_node(
+ "MultiThreshold",
+ ["v", "thresholds"],
+ ["out"],
+ domain="finn",
+ data_layout="NHWC",
+ )
+
+ v_nhwc = helper.make_tensor_value_info("v", TensorProto.FLOAT, [6, 2, 2, 3])
+ out_nhwc = helper.make_tensor_value_info("out", TensorProto.FLOAT, [6, 2, 2, 3])
+ inputs_nhwc = np.transpose(inputs, (0, 2, 3, 1)) # NCHW -> NHWC
+ outputs_nhwc = np.transpose(outputs, (0, 2, 3, 1)) # NCHW -> NHWC
+ execution_context["v"] = inputs_nhwc
+
+ graph_def = helper.make_graph(
+ [node_def], "test_model", [v_nhwc, thresholds], [out_nhwc]
+ )
+ ex_cu_node.execute_custom_node(node_def, execution_context, graph_def)
+ assert (execution_context["out"] == outputs_nhwc).all()
diff --git a/tests/core/test_modelwrapper.py b/tests/core/test_modelwrapper.py
index 5d18de2d18157383a3c7882febfa752d72774572..942eda19ca4c2cdbded9f906a5e7772f50acbd6e 100644
--- a/tests/core/test_modelwrapper.py
+++ b/tests/core/test_modelwrapper.py
@@ -43,17 +43,26 @@ def test_modelwrapper():
bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path)
model = ModelWrapper(export_onnx_path)
assert model.check_all_tensor_shapes_specified() is False
- inp_shape = model.get_tensor_shape("0")
+ inp_name = model.graph.input[0].name
+ inp_shape = model.get_tensor_shape(inp_name)
assert inp_shape == [1, 1, 28, 28]
- l0_mat_tensor_name = "33"
+ # find first matmul node
+ l0_mat_tensor_name = ""
+ l0_inp_tensor_name = ""
+ for node in model.graph.node:
+ if node.op_type == "MatMul":
+ l0_inp_tensor_name = node.input[0]
+ l0_mat_tensor_name = node.input[1]
+ break
+ assert l0_mat_tensor_name != ""
l0_weights = model.get_initializer(l0_mat_tensor_name)
assert l0_weights.shape == (784, 1024)
l0_weights_hist = Counter(l0_weights.flatten())
- assert l0_weights_hist[1.0] == 401311 and l0_weights_hist[-1.0] == 401505
+ assert (l0_weights_hist[1.0] + l0_weights_hist[-1.0]) == 784 * 1024
l0_weights_rand = np.random.randn(784, 1024)
model.set_initializer(l0_mat_tensor_name, l0_weights_rand)
assert (model.get_initializer(l0_mat_tensor_name) == l0_weights_rand).all()
- l0_inp_tensor_name = "32"
+ assert l0_inp_tensor_name != ""
inp_cons = model.find_consumer(l0_inp_tensor_name)
assert inp_cons.op_type == "MatMul"
out_prod = model.find_producer(l0_inp_tensor_name)
diff --git a/tests/custom_op/test_im2col.py b/tests/custom_op/test_im2col.py
new file mode 100644
index 0000000000000000000000000000000000000000..0b148145bd6f7d9819e4b72da5333d2556de94e4
--- /dev/null
+++ b/tests/custom_op/test_im2col.py
@@ -0,0 +1,320 @@
+import numpy as np
+from onnx import TensorProto, helper
+
+import finn.core.onnx_exec as oxe
+from finn.core.datatype import DataType
+from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.infer_datatypes import InferDataTypes
+from finn.transformation.infer_shapes import InferShapes
+from finn.custom_op.im2col import compute_conv_output_dim
+
+
+def check_two_dict_for_equality(dict1, dict2):
+ for key in dict1:
+ assert key in dict2, "Key: {} is not in both dictionaries".format(key)
+ assert (
+ dict1[key] == dict2[key]
+ ), """Values for key {} are not the same
+ in both dictionaries""".format(
+ key
+ )
+
+ return True
+
+
+def execution_im2col(x, idt, k, stride, ifm_ch, ifm_dim, pad_amt=0, pad_val=0):
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad_amt)
+
+ # set up onnx model
+ inp = helper.make_tensor_value_info(
+ "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]
+ )
+ outp = helper.make_tensor_value_info(
+ "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch]
+ )
+
+ Im2Col_node = helper.make_node(
+ "Im2Col",
+ ["inp"],
+ ["outp"],
+ domain="finn",
+ stride=stride,
+ kernel_size=k,
+ pad_amount=pad_amt,
+ pad_value=pad_val,
+ input_shape="(1,{},{},{})".format(ifm_dim, ifm_dim, ifm_ch),
+ )
+
+ graph = helper.make_graph(
+ nodes=[Im2Col_node], name="im2col_graph", inputs=[inp], outputs=[outp]
+ )
+
+ model = helper.make_model(graph, producer_name="im2col-model")
+ model = ModelWrapper(model)
+
+ model.set_tensor_datatype("inp", idt)
+
+ # test shape inference
+ model.transform(InferShapes())
+ assert model.get_tensor_shape("outp") == [1, ofm_dim, ofm_dim, k * k * ifm_ch]
+
+ # test datatype inference
+ assert model.get_tensor_datatype("outp") is DataType.FLOAT32
+ model = model.transform(InferDataTypes())
+ assert model.get_tensor_datatype("outp") is idt
+
+ # prepare input data
+ input_dict = {"inp": x}
+
+ # execute model
+ y_produced = oxe.execute_onnx(model, input_dict)["outp"]
+
+ return y_produced
+
+
+def test_im2col():
+ # bipolar inputs with following im2col parameters
+ idt = DataType.BIPOLAR
+ k = 2
+ stride = 1
+ ifm_ch = 1
+ ifm_dim = 4
+ pad_amt = 0
+ pad_val = 0
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad_amt)
+
+ x = np.asarray(
+ [
+ -1.0,
+ -1.0,
+ 1.0,
+ 1.0,
+ 1.0,
+ -1.0,
+ 1.0,
+ -1.0,
+ -1.0,
+ 1.0,
+ -1.0,
+ -1.0,
+ 1.0,
+ 1.0,
+ 1.0,
+ 1.0,
+ ],
+ dtype=np.float32,
+ ).reshape(1, ifm_dim, ifm_dim, ifm_ch)
+
+ expected = np.asarray(
+ [
+ -1.0,
+ -1.0,
+ 1.0,
+ -1.0,
+ -1.0,
+ 1.0,
+ -1.0,
+ 1.0,
+ 1.0,
+ 1.0,
+ 1.0,
+ -1.0,
+ 1.0,
+ -1.0,
+ -1.0,
+ 1.0,
+ -1.0,
+ 1.0,
+ 1.0,
+ -1.0,
+ 1.0,
+ -1.0,
+ -1.0,
+ -1.0,
+ -1.0,
+ 1.0,
+ 1.0,
+ 1.0,
+ 1.0,
+ -1.0,
+ 1.0,
+ 1.0,
+ -1.0,
+ -1.0,
+ 1.0,
+ 1.0,
+ ],
+ dtype=np.float32,
+ ).reshape(1, ofm_dim, ofm_dim, k * k * ifm_ch)
+
+ produced = execution_im2col(x, idt, k, stride, ifm_ch, ifm_dim, pad_amt, pad_val)
+ assert (produced == expected).all()
+
+ idt = DataType.INT8
+ k = 2
+ stride = 1
+ ifm_ch = 2
+ ifm_dim = 4
+ pad_amt = 0
+ pad_val = 0
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad_amt)
+
+ x = np.asarray(
+ [
+ [
+ [[1, -1], [2, -2], [3, -3], [4, -4]],
+ [[5, -5], [6, -6], [7, -7], [8, -8]],
+ [[9, -9], [10, -10], [11, -11], [12, -12]],
+ [[13, -13], [14, -14], [15, -15], [16, -16]],
+ ]
+ ],
+ dtype=np.float32,
+ )
+
+ expected = np.asarray(
+ [
+ [
+ [
+ [1.0, -1.0, 2.0, -2.0, 5.0, -5.0, 6.0, -6.0],
+ [2.0, -2.0, 3.0, -3.0, 6.0, -6.0, 7.0, -7.0],
+ [3.0, -3.0, 4.0, -4.0, 7.0, -7.0, 8.0, -8.0],
+ ],
+ [
+ [5.0, -5.0, 6.0, -6.0, 9.0, -9.0, 10.0, -10.0],
+ [6.0, -6.0, 7.0, -7.0, 10.0, -10.0, 11.0, -11.0],
+ [7.0, -7.0, 8.0, -8.0, 11.0, -11.0, 12.0, -12.0],
+ ],
+ [
+ [9.0, -9.0, 10.0, -10.0, 13.0, -13.0, 14.0, -14.0],
+ [10.0, -10.0, 11.0, -11.0, 14.0, -14.0, 15.0, -15.0],
+ [11.0, -11.0, 12.0, -12.0, 15.0, -15.0, 16.0, -16.0],
+ ],
+ ]
+ ],
+ dtype=np.float32,
+ )
+
+ produced = execution_im2col(x, idt, k, stride, ifm_ch, ifm_dim, pad_amt, pad_val)
+ assert (produced == expected).all()
+
+ idt = DataType.INT8
+ k = 2
+ stride = 1
+ ifm_ch = 2
+ ifm_dim = 4
+ pad_amt = 1
+ pad_val = 0
+ ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, pad_amt)
+
+ x = np.asarray(
+ [
+ [
+ [[1, -1], [2, -2], [3, -3], [4, -4]],
+ [[5, -5], [6, -6], [7, -7], [8, -8]],
+ [[9, -9], [10, -10], [11, -11], [12, -12]],
+ [[13, -13], [14, -14], [15, -15], [16, -16]],
+ ]
+ ],
+ dtype=np.float32,
+ )
+
+ expected = np.asarray(
+ [
+ [
+ [
+ [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, -1.0],
+ [0.0, 0.0, 0.0, 0.0, 1.0, -1.0, 2.0, -2.0],
+ [0.0, 0.0, 0.0, 0.0, 2.0, -2.0, 3.0, -3.0],
+ [0.0, 0.0, 0.0, 0.0, 3.0, -3.0, 4.0, -4.0],
+ [0.0, 0.0, 0.0, 0.0, 4.0, -4.0, 0.0, 0.0],
+ ],
+ [
+ [0.0, 0.0, 1.0, -1.0, 0.0, 0.0, 5.0, -5.0],
+ [1.0, -1.0, 2.0, -2.0, 5.0, -5.0, 6.0, -6.0],
+ [2.0, -2.0, 3.0, -3.0, 6.0, -6.0, 7.0, -7.0],
+ [3.0, -3.0, 4.0, -4.0, 7.0, -7.0, 8.0, -8.0],
+ [4.0, -4.0, 0.0, 0.0, 8.0, -8.0, 0.0, 0.0],
+ ],
+ [
+ [0.0, 0.0, 5.0, -5.0, 0.0, 0.0, 9.0, -9.0],
+ [5.0, -5.0, 6.0, -6.0, 9.0, -9.0, 10.0, -10.0],
+ [6.0, -6.0, 7.0, -7.0, 10.0, -10.0, 11.0, -11.0],
+ [7.0, -7.0, 8.0, -8.0, 11.0, -11.0, 12.0, -12.0],
+ [8.0, -8.0, 0.0, 0.0, 12.0, -12.0, 0.0, 0.0],
+ ],
+ [
+ [0.0, 0.0, 9.0, -9.0, 0.0, 0.0, 13.0, -13.0],
+ [9.0, -9.0, 10.0, -10.0, 13.0, -13.0, 14.0, -14.0],
+ [10.0, -10.0, 11.0, -11.0, 14.0, -14.0, 15.0, -15.0],
+ [11.0, -11.0, 12.0, -12.0, 15.0, -15.0, 16.0, -16.0],
+ [12.0, -12.0, 0.0, 0.0, 16.0, -16.0, 0.0, 0.0],
+ ],
+ [
+ [0.0, 0.0, 13.0, -13.0, 0.0, 0.0, 0.0, 0.0],
+ [13.0, -13.0, 14.0, -14.0, 0.0, 0.0, 0.0, 0.0],
+ [14.0, -14.0, 15.0, -15.0, 0.0, 0.0, 0.0, 0.0],
+ [15.0, -15.0, 16.0, -16.0, 0.0, 0.0, 0.0, 0.0],
+ [16.0, -16.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0],
+ ],
+ ]
+ ],
+ dtype=np.float32,
+ )
+
+ produced = execution_im2col(x, idt, k, stride, ifm_ch, ifm_dim, pad_amt, pad_val)
+ assert (produced == expected).all()
+
+
+def test_im2col_infer_shapes():
+ idt = DataType.BIPOLAR
+ k = 2
+ stride = 1
+ ifm_ch = 1
+ ifm_dim = 4
+ ofm_dim = int(((ifm_dim - k) / stride) + 1)
+
+ # set up onnx model
+ inp = helper.make_tensor_value_info(
+ "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]
+ )
+ outp = helper.make_tensor_value_info(
+ "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch]
+ )
+
+ abs_node = helper.make_node("Abs", inputs=["inp"], outputs=["abs"])
+
+ Im2Col_node = helper.make_node(
+ "Im2Col",
+ ["abs"],
+ ["im2col"],
+ domain="finn",
+ stride=stride,
+ kernel_size=k,
+ input_shape="(1,{},{},{})".format(ifm_dim, ifm_dim, ifm_ch),
+ )
+
+ abs1_node = helper.make_node("Abs", inputs=["im2col"], outputs=["outp"])
+
+ graph = helper.make_graph(
+ nodes=[abs_node, Im2Col_node, abs1_node],
+ name="shape_graph",
+ inputs=[inp],
+ outputs=[outp],
+ value_info=[
+ helper.make_tensor_value_info(
+ "abs", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]
+ ),
+ helper.make_tensor_value_info(
+ "im2col", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch]
+ ),
+ ],
+ )
+
+ model = helper.make_model(graph, producer_name="shape-model")
+ model = ModelWrapper(model)
+
+ model.set_tensor_datatype("inp", idt)
+
+ # test shape inference
+ model.transform(InferShapes())
+ assert model.get_tensor_shape("im2col") == [1, ofm_dim, ofm_dim, k * k * ifm_ch]
diff --git a/tests/custom_op/test_verify_custom_nodes.py b/tests/custom_op/test_verify_custom_nodes.py
deleted file mode 100644
index e9ea2da622c4f24be7c599a7a8071e859e14ee3d..0000000000000000000000000000000000000000
--- a/tests/custom_op/test_verify_custom_nodes.py
+++ /dev/null
@@ -1,184 +0,0 @@
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from onnx import TensorProto, helper
-
-from finn.analysis.verify_custom_nodes import verify_nodes
-from finn.core.modelwrapper import ModelWrapper
-
-
-def check_two_dict_for_equality(dict1, dict2):
- for key in dict1:
- assert key in dict2, "Key: {} is not in both dictionaries".format(key)
- assert (
- dict1[key] == dict2[key]
- ), """Values for key {} are not the same
- in both dictionaries""".format(
- key
- )
-
- return True
-
-
-def test_verify_custom_nodes():
- inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, 13, 64])
- outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, 1, 64])
-
- # MultiThreshold
- m_node = helper.make_node(
- "MultiThreshold",
- ["xnor_out", "threshs"],
- ["outp"],
- domain="finn",
- out_scale=2.0,
- out_bias=-1.0,
- out_dtype="",
- )
-
- # XnorPopcountMatMul
- xnor_node = helper.make_node(
- "XnorPopcountMatMul",
- ["fclayer_out0", "fclayer_out1"],
- ["xnor_out"],
- domain="finn",
- )
-
- # StreamingMaxPool_Batch
- MaxPool_batch_node = helper.make_node(
- "StreamingMaxPool_Batch",
- ["inp"],
- ["max_out"],
- domain="finn",
- backend="fpgadataflow",
- code_gen_dir="",
- executable_path="",
- ImgDim=4,
- PoolDim=2,
- NumChannels=2,
- )
-
- # StreamingFCLayer_Batch - no activation
- FCLayer0_node = helper.make_node(
- "StreamingFCLayer_Batch",
- ["max_out", "weights"],
- ["fclayer_out0"],
- domain="finn",
- backend="fpgadataflow",
- code_gen_dir="",
- executable_path="",
- resType="ap_resource_lut()",
- MW=8,
- MH=8,
- SIMD=4,
- PE=4,
- inputDataType="<FINN DataType>",
- weightDataType="<FINN DataType>",
- outputDataType="<FINN DataType>",
- ActVal=0,
- binaryXnorMode=1,
- noActivation=1,
- )
-
- # StreamingFCLayer_Batch - with activation
- FCLayer1_node = helper.make_node(
- "StreamingFCLayer_Batch",
- ["fclayer_out0", "weights", "threshs"],
- ["fclayer_out1"],
- domain="finn",
- backend="fpgadataflow",
- code_gen_dir="",
- executable_path="",
- resType="ap_resource_lut()",
- MW=8,
- MH=8,
- SIMD=4,
- PE=4,
- inputDataType="<FINN DataType>",
- weightDataType="<FINN DataType>",
- outputDataType="<FINN DataType>",
- ActVal=0,
- binaryXnorMode=1,
- noActivation=0,
- )
-
- graph = helper.make_graph(
- nodes=[MaxPool_batch_node, FCLayer0_node, FCLayer1_node, xnor_node, m_node],
- name="custom_op_graph",
- inputs=[inp],
- outputs=[outp],
- value_info=[
- helper.make_tensor_value_info("max_out", TensorProto.FLOAT, [1, 13, 64]),
- helper.make_tensor_value_info("weights", TensorProto.FLOAT, [64, 32, 416]),
- helper.make_tensor_value_info("threshs", TensorProto.FLOAT, [32, 32, 16]),
- helper.make_tensor_value_info("xnor_out", TensorProto.FLOAT, [1, 32, 32]),
- helper.make_tensor_value_info(
- "fclayer_out0", TensorProto.FLOAT, [1, 32, 32]
- ),
- helper.make_tensor_value_info(
- "fclayer_out1", TensorProto.FLOAT, [32, 64, 512]
- ),
- ],
- )
- model = helper.make_model(graph, producer_name="custom-op-model")
- model = ModelWrapper(model)
-
- produced = model.analysis(verify_nodes)
-
- expected = {
- "StreamingMaxPool_Batch": [
- "The number of attributes is correct",
- "Attribute domain is set correctly",
- "Attribute backend is set correctly",
- "All necessary attributes exist",
- "The number of inputs is correct",
- ],
- "StreamingFCLayer_Batch": [
- "The number of attributes is correct",
- "Attribute domain is set correctly",
- "Attribute backend is set correctly",
- "All necessary attributes exist",
- "The number of inputs is correct",
- ],
- "XnorPopcountMatMul": [
- "The number of attributes is correct",
- "Attribute domain is set correctly",
- "XnorPopcountMatMul should not have any attributes",
- "The number of inputs is correct",
- ],
- "MultiThreshold": [
- "The number of attributes is correct",
- "Attribute domain is set correctly",
- "All necessary attributes exist",
- "The number of inputs is correct",
- ],
- }
-
- assert check_two_dict_for_equality(
- produced, expected
- ), """The produced output of
- the verification analysis pass is not equal to the expected one"""
diff --git a/tests/end2end/test_end2end_cnv_w1a1.py b/tests/end2end/test_end2end_cnv_w1a1.py
new file mode 100644
index 0000000000000000000000000000000000000000..34e0df8402ea0d1b880781185cd17e3ccb1a0ae0
--- /dev/null
+++ b/tests/end2end/test_end2end_cnv_w1a1.py
@@ -0,0 +1,325 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+
+import numpy as np
+
+# as of Feb'20 there is a bug that segfaults ONNX shape inference if we
+# import pytorch before onnx, so we make sure to import onnx first
+import onnx # NOQA
+
+import pytest
+import pkg_resources as pk
+from finn.core.modelwrapper import ModelWrapper
+from finn.custom_op.registry import getCustomOp
+from finn.core.onnx_exec import execute_onnx
+from finn.transformation.double_to_single_float import DoubleToSingleFloat
+from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.move_reshape import MoveReshape
+from finn.transformation.fold_constants import FoldConstants
+from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
+from finn.transformation.streamline import Streamline
+from finn.transformation.lower_convs_to_matmul import LowerConvsToMatMul
+from finn.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount
+import finn.transformation.streamline.absorb as absorb
+from finn.transformation.streamline.reorder import MakeMaxPoolNHWC
+import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls
+from finn.transformation.fpgadataflow.create_dataflow_partition import (
+ CreateDataflowPartition,
+)
+from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
+from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
+from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
+ ReplaceVerilogRelPaths,
+)
+from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
+from finn.transformation.fpgadataflow.compile import Compile
+from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
+from finn.transformation.fpgadataflow.make_pynq_proj import MakePYNQProject
+from finn.transformation.fpgadataflow.synth_pynq_proj import SynthPYNQProject
+from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
+from finn.util.basic import pynq_part_map
+from finn.util.test import get_test_model_trained
+from finn.transformation.fpgadataflow.annotate_resources import AnnotateResources
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
+from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
+
+build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
+test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
+test_fpga_part = pynq_part_map[test_pynq_board]
+target_clk_ns = 5
+mem_mode = "decoupled"
+
+
+def test_end2end_cnv_w1a1_export():
+ import brevitas.onnx as bo
+
+ cnv = get_test_model_trained("CNV", 1, 1)
+ bo.export_finn_onnx(
+ cnv, (1, 3, 32, 32), build_dir + "/end2end_cnv_w1a1_export.onnx"
+ )
+
+
+def test_end2end_cnv_w1a1_import_and_tidy():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_export.onnx")
+ model = model.transform(DoubleToSingleFloat())
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(GiveReadableTensorNames())
+ model.save(build_dir + "/end2end_cnv_w1a1_tidy.onnx")
+
+
+def test_end2end_cnv_w1a1_streamline():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_tidy.onnx")
+ model = model.transform(Streamline())
+ model = model.transform(LowerConvsToMatMul())
+ model = model.transform(MakeMaxPoolNHWC())
+ model = model.transform(absorb.AbsorbTransposeIntoMultiThreshold())
+ model = model.transform(ConvertBipolarMatMulToXnorPopcount())
+ model = model.transform(Streamline())
+ model.save(build_dir + "/end2end_cnv_w1a1_streamlined.onnx")
+
+
+def test_end2end_cnv_w1a1_convert_to_hls_layers():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_streamlined.onnx")
+ model = model.transform(to_hls.InferBinaryStreamingFCLayer(mem_mode))
+ model = model.transform(to_hls.InferQuantizedStreamingFCLayer(mem_mode))
+ model = model.transform(to_hls.InferConvInpGen())
+ model = model.transform(to_hls.InferStreamingMaxPool())
+ model = model.transform(MoveReshape())
+ model.save(build_dir + "/end2end_cnv_w1a1_hls_layers.onnx")
+
+
+def test_end2end_cnv_w1a1_create_dataflow_partition():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_hls_layers.onnx")
+ parent_model = model.transform(CreateDataflowPartition())
+ parent_model.save(build_dir + "/end2end_cnv_w1a1_dataflow_parent.onnx")
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
+ dataflow_model_filename = sdp_node.get_nodeattr("model")
+ dataflow_model = ModelWrapper(dataflow_model_filename)
+ dataflow_model.save(build_dir + "/end2end_cnv_w1a1_dataflow_model.onnx")
+
+
+def test_end2end_cnv_w1a1_fold_and_tlastmarker():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_dataflow_model.onnx")
+ fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
+ # each tuple is (PE, SIMD, in_fifo_depth) for a layer
+ folding = [
+ (16, 3, 128),
+ (32, 32, 128),
+ (16, 32, 128),
+ (16, 32, 128),
+ (4, 32, 81),
+ (1, 32, 2),
+ (1, 4, 2),
+ (1, 8, 128),
+ (5, 1, 3),
+ ]
+ for fcl, (pe, simd, ififodepth) in zip(fc_layers, folding):
+ fcl_inst = getCustomOp(fcl)
+ fcl_inst.set_nodeattr("PE", pe)
+ fcl_inst.set_nodeattr("SIMD", simd)
+ fcl_inst.set_nodeattr("inFIFODepth", ififodepth)
+
+ swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator")
+ for i in range(len(swg_layers)):
+ swg_inst = getCustomOp(swg_layers[i])
+ simd = folding[i][1]
+ swg_inst.set_nodeattr("SIMD", simd)
+
+ model = model.transform(InsertDWC())
+ model = model.transform(InsertFIFO())
+ model = model.transform(InsertTLastMarker())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(AnnotateResources("estimate"))
+ model.save(build_dir + "/end2end_cnv_w1a1_folded.onnx")
+
+
+def test_end2end_cnv_w1a1_gen_hls_ip():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_folded.onnx")
+ model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(HLSSynth_IPGen())
+ model = model.transform(AnnotateResources("hls"))
+ model.save(build_dir + "/end2end_cnv_w1a1_ipgen.onnx")
+
+
+def test_end2end_cnv_w1a1_ip_stitch():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_ipgen.onnx")
+ model = model.transform(ReplaceVerilogRelPaths())
+ model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model.save(build_dir + "/end2end_cnv_w1a1_ipstitch.onnx")
+
+
+def test_end2end_cnv_w1a1_verify_dataflow_part():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_ipstitch.onnx")
+ x = np.zeros((1, 32, 32, 3), dtype=np.float32)
+ inp_name = model.graph.input[0].name
+ out_name = model.graph.output[0].name
+ inp_dict = {inp_name: x}
+ # npysim
+ model = model.transform(CodeGen_npysim())
+ model = model.transform(Compile())
+ model = model.transform(SetExecMode("npysim"))
+ model.save(build_dir + "/end2end_cnv_w1a1_ipgen_npysim.onnx")
+ ret_npysim = execute_onnx(model, inp_dict, True)
+ res_npysim = ret_npysim[out_name]
+ # node-by-node rtlsim
+ model = model.transform(SetExecMode("rtlsim"))
+ model = model.transform(PrepareRTLSim())
+ model.save(build_dir + "/end2end_cnv_w1a1_ipgen_nodebynode_rtlsim.onnx")
+ ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
+ res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
+ # whole-network (ip-stitched) rtlsim
+ model.set_metadata_prop("exec_mode", "rtlsim")
+ model.save(build_dir + "/end2end_cnv_w1a1_ipstitch_whole_rtlsim.onnx")
+ # this is a particularly long-running test, set liveness thr. to unlimited
+ os.environ["LIVENESS_THRESHOLD"] = "-1"
+ ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
+ res_rtlsim_whole = ret_rtlsim_whole[out_name]
+ assert np.isclose(res_npysim, res_rtlsim_nodebynode).all()
+ assert np.isclose(res_npysim, res_rtlsim_whole).all()
+
+
+def test_end2end_cnv_w1a1_verify_all():
+ # use the streamlined model as the "golden" model for right answers
+ golden = ModelWrapper(build_dir + "/end2end_cnv_w1a1_streamlined.onnx")
+ iname = golden.graph.input[0].name
+ oname = golden.graph.output[0].name
+ # load one of the test vectors
+ fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
+ input_tensor = np.load(fn)["arr_0"].astype(np.float32)
+ assert input_tensor.shape == (1, 3, 32, 32)
+ x = input_tensor
+ # x = np.zeros(ishape, dtype=np.float32)
+ ret_golden = execute_onnx(golden, {iname: x}, True)
+ y_golden = ret_golden[oname]
+ # set up parent+child graph to test
+ # we'll use models from the previous step as the child model
+ parent_model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_dataflow_parent.onnx")
+ iname = parent_model.graph.input[0].name
+ oname = parent_model.graph.output[0].name
+ # produce results with npysim
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
+ sdp_node.set_nodeattr("model", build_dir + "/end2end_cnv_w1a1_ipgen_npysim.onnx")
+ ret_npysim = execute_onnx(parent_model, {iname: x}, True)
+ y_npysim = ret_npysim[oname]
+ # produce results with node-by-node rtlsim
+ sdp_node.set_nodeattr(
+ "model", build_dir + "/end2end_cnv_w1a1_ipgen_nodebynode_rtlsim.onnx"
+ )
+ ret_nodebynode_rtlsim = execute_onnx(parent_model, {iname: x}, True)
+ y_nodebynode_rtlsim = ret_nodebynode_rtlsim[oname]
+ # produce results with whole-network (stitched ip) rtlsim
+ sdp_node.set_nodeattr(
+ "model", build_dir + "/end2end_cnv_w1a1_ipstitch_whole_rtlsim.onnx"
+ )
+ # this is a particularly long-running test, set liveness thr. to unlimited
+ os.environ["LIVENESS_THRESHOLD"] = "-1"
+ ret_whole_rtlsim = execute_onnx(parent_model, {iname: x}, True)
+ y_whole_rtlsim = ret_whole_rtlsim[oname]
+ assert np.isclose(y_golden, y_npysim).all()
+ assert np.isclose(y_golden, y_nodebynode_rtlsim).all()
+ assert np.isclose(y_golden, y_whole_rtlsim).all()
+
+
+def test_end2end_cnv_w1a1_make_pynq_proj():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_ipstitch.onnx")
+ model = model.transform(MakePYNQProject(test_pynq_board))
+ model.save(build_dir + "/end2end_cnv_w1a1_pynq_project.onnx")
+
+
+def test_end2end_cnv_w1a1_synth_pynq_project():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_pynq_project.onnx")
+ model = model.transform(SynthPYNQProject())
+ model = model.transform(AnnotateResources("synth"))
+ model.save(build_dir + "/end2end_cnv_w1a1_synth.onnx")
+
+
+def test_end2end_cnv_w1a1_make_driver():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_synth.onnx")
+ model = model.transform(MakePYNQDriver())
+ model.save(build_dir + "/end2end_cnv_w1a1_pynq_driver.onnx")
+
+
+def test_end2end_cnv_w1a1_deploy_on_pynq():
+ model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_pynq_driver.onnx")
+ try:
+ ip = os.environ["PYNQ_IP"] # no fault for this one; skip if not defined
+ if ip == "":
+ pytest.skip("PYNQ board IP address not specified")
+ username = os.getenv("PYNQ_USERNAME", "xilinx")
+ password = os.getenv("PYNQ_PASSWORD", "xilinx")
+ port = os.getenv("PYNQ_PORT", 22)
+ target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
+ model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))
+ # save the model to be able to link it to the parent
+ model.save(build_dir + "/end2end_cnv_w1a1_pynq_deploy.onnx")
+ except KeyError:
+ pytest.skip("PYNQ board IP address not specified")
+
+
+def test_end2end_cnv_w1a1_run_on_pynq():
+ # use the streamlined model as the "golden" model for right answers
+ golden = ModelWrapper(build_dir + "/end2end_cnv_w1a1_streamlined.onnx")
+ iname = golden.graph.input[0].name
+ oname = golden.graph.output[0].name
+ # load one of the test vectors
+ fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
+ input_tensor = np.load(fn)["arr_0"].astype(np.float32)
+ assert input_tensor.shape == (1, 3, 32, 32)
+ x = input_tensor
+ # run using FINN-based execution
+ ret_golden = execute_onnx(golden, {iname: x}, True)
+ y_golden = ret_golden[oname]
+ # set up parent+child graph to test
+ # we'll use models from the previous step as the child model
+ parent_model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_dataflow_parent.onnx")
+ iname = parent_model.graph.input[0].name
+ oname = parent_model.graph.output[0].name
+ try:
+ ip = os.environ["PYNQ_IP"] # NOQA
+ if ip == "":
+ pytest.skip("PYNQ board IP address not specified")
+ # produce results with npysim
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
+ sdp_node.set_nodeattr("model", build_dir + "/end2end_cnv_w1a1_pynq_deploy.onnx")
+ ret = execute_onnx(parent_model, {iname: x}, True)
+ y = ret[oname]
+ assert np.isclose(y, y_golden).all()
+
+ except KeyError:
+ pytest.skip("PYNQ board IP address not specified")
diff --git a/tests/end2end/test_end2end_tfc_w1a1.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
similarity index 83%
rename from tests/end2end/test_end2end_tfc_w1a1.py
rename to tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index 1c2a3b799d423cb0779da3388e71f5ac8cb1b380..ded0bd107ab9f15a72018137c79eac640e09d3a2 100644
--- a/tests/end2end/test_end2end_tfc_w1a1.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -42,6 +42,7 @@ import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls
import finn.transformation.streamline.absorb as absorb
from finn.core.modelwrapper import ModelWrapper
from finn.core.onnx_exec import execute_onnx
+from finn.core.throughput_test import throughput_test
from finn.custom_op.registry import getCustomOp
from finn.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount
from finn.transformation.fold_constants import FoldConstants
@@ -53,7 +54,9 @@ from finn.transformation.fpgadataflow.create_dataflow_partition import (
CreateDataflowPartition,
)
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
+from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
from finn.transformation.fpgadataflow.make_pynq_proj import MakePYNQProject
@@ -69,11 +72,14 @@ from finn.transformation.streamline import Streamline
from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds
from finn.util.basic import pynq_part_map
from finn.util.test import get_test_model_trained
+from finn.transformation.fpgadataflow.annotate_resources import AnnotateResources
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 5
+target_clk_ns = 10
+mem_mode = "decoupled"
def test_end2end_tfc_w1a1_export():
@@ -107,7 +113,7 @@ def test_end2end_tfc_w1a1_convert_to_hls_layers():
model = model.transform(absorb.AbsorbAddIntoMultiThreshold())
model = model.transform(absorb.AbsorbMulIntoMultiThreshold())
model = model.transform(RoundAndClipThresholds())
- model = model.transform(to_hls.InferBinaryStreamingFCLayer())
+ model = model.transform(to_hls.InferBinaryStreamingFCLayer(mem_mode))
model.save(build_dir + "/end2end_tfc_w1a1_hls_layers.onnx")
@@ -115,7 +121,8 @@ def test_end2end_tfc_w1a1_create_dataflow_partition():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_hls_layers.onnx")
parent_model = model.transform(CreateDataflowPartition())
parent_model.save(build_dir + "/end2end_tfc_w1a1_dataflow_parent.onnx")
- sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
dataflow_model_filename = sdp_node.get_nodeattr("model")
dataflow_model = ModelWrapper(dataflow_model_filename)
dataflow_model.save(build_dir + "/end2end_tfc_w1a1_dataflow_model.onnx")
@@ -123,36 +130,56 @@ def test_end2end_tfc_w1a1_create_dataflow_partition():
def test_end2end_tfc_w1a1_fold_and_tlastmarker():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_dataflow_model.onnx")
- fc0 = model.graph.node[0]
- fc1 = model.graph.node[1]
- fc2 = model.graph.node[2]
- fc3 = model.graph.node[3]
- fc0w = getCustomOp(fc0)
- fc1w = getCustomOp(fc1)
- fc2w = getCustomOp(fc2)
- fc3w = getCustomOp(fc3)
- fc0w.set_nodeattr("inFIFODepth", 50)
- fc0w.set_nodeattr("SIMD", 16)
+ fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
+ fc0w = getCustomOp(fc_layers[0])
+ fc1w = getCustomOp(fc_layers[1])
+ fc2w = getCustomOp(fc_layers[2])
+ fc3w = getCustomOp(fc_layers[3])
+ fc0w.set_nodeattr("inFIFODepth", 256)
+ fc0w.set_nodeattr("SIMD", 196)
fc0w.set_nodeattr("PE", 16)
- fc0w.set_nodeattr("outFIFODepth", 4)
+ fc0w.set_nodeattr("outFIFODepth", 64)
+ fc1w.set_nodeattr("inFIFODepth", 64)
+ fc0w.set_nodeattr("ram_style", "block")
fc1w.set_nodeattr("SIMD", 16)
fc1w.set_nodeattr("PE", 16)
- fc1w.set_nodeattr("outFIFODepth", 4)
+ fc1w.set_nodeattr("outFIFODepth", 64)
+ fc2w.set_nodeattr("inFIFODepth", 64)
fc2w.set_nodeattr("SIMD", 16)
fc2w.set_nodeattr("PE", 16)
- fc2w.set_nodeattr("outFIFODepth", 4)
+ fc2w.set_nodeattr("outFIFODepth", 64)
+ fc3w.set_nodeattr("inFIFODepth", 64)
fc3w.set_nodeattr("SIMD", 16)
fc3w.set_nodeattr("PE", 10)
- fc3w.set_nodeattr("outFIFODepth", 50)
+ fc3w.set_nodeattr("outFIFODepth", 10)
+ fc3w.set_nodeattr("ram_style", "distributed")
+ model = model.transform(InsertDWC())
+ model = model.transform(InsertFIFO())
model = model.transform(InsertTLastMarker())
+ model = model.transform(GiveUniqueNodeNames())
+ fifos = []
+ for n in model.graph.node:
+ if n.op_type == "StreamingFIFO":
+ fifos.append(n)
+ fifo0 = getCustomOp(fifos[0])
+ fifo1 = getCustomOp(fifos[1])
+ fifo2 = getCustomOp(fifos[2])
+ fifo3 = getCustomOp(fifos[3])
+ fifo4 = getCustomOp(fifos[4])
+ fifo0.set_nodeattr("depth", 256)
+ fifo1.set_nodeattr("depth", 64)
+ fifo2.set_nodeattr("depth", 64)
+ fifo3.set_nodeattr("depth", 64)
+ fifo4.set_nodeattr("depth", 10)
+ model = model.transform(AnnotateResources("estimate"))
model.save(build_dir + "/end2end_tfc_w1a1_folded.onnx")
def test_end2end_tfc_w1a1_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_folded.onnx")
- model = model.transform(GiveUniqueNodeNames())
model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynth_IPGen())
+ model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
@@ -178,16 +205,12 @@ def test_end2end_tfc_w1a1_verify_dataflow_part():
res_npysim = ret_npysim[out_name]
# node-by-node rtlsim
model = model.transform(SetExecMode("rtlsim"))
- getCustomOp(model.graph.node[0]).set_nodeattr("rtlsim_trace", "default")
- getCustomOp(model.graph.node[1]).set_nodeattr("rtlsim_trace", "default")
- getCustomOp(model.graph.node[2]).set_nodeattr("rtlsim_trace", "default")
- getCustomOp(model.graph.node[3]).set_nodeattr("rtlsim_trace", "default")
+ model = model.transform(PrepareRTLSim())
model.save(build_dir + "/end2end_tfc_w1a1_ipstitch_nodebynode_rtlsim.onnx")
ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
# whole-network (ip-stitched) rtlsim
model.set_metadata_prop("exec_mode", "rtlsim")
- model.set_metadata_prop("rtlsim_trace", "whole_trace.vcd")
model.save(build_dir + "/end2end_tfc_w1a1_ipstitch_whole_rtlsim.onnx")
ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
res_rtlsim_whole = ret_rtlsim_whole[out_name]
@@ -212,7 +235,8 @@ def test_end2end_tfc_w1a1_verify_all():
iname = parent_model.graph.input[0].name
oname = parent_model.graph.output[0].name
# produce results with npysim
- sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w1a1_ipstitch_npysim.onnx")
ret_npysim = execute_onnx(parent_model, {iname: x}, True)
y_npysim = ret_npysim[oname]
@@ -242,6 +266,7 @@ def test_end2end_tfc_w1a1_make_pynq_proj():
def test_end2end_tfc_w1a1_synth_pynq_project():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_pynq_project.onnx")
model = model.transform(SynthPYNQProject())
+ model = model.transform(AnnotateResources("synth"))
model.save(build_dir + "/end2end_tfc_w1a1_synth.onnx")
@@ -259,8 +284,9 @@ def test_end2end_tfc_w1a1_deploy_on_pynq():
pytest.skip("PYNQ board IP address not specified")
username = os.getenv("PYNQ_USERNAME", "xilinx")
password = os.getenv("PYNQ_PASSWORD", "xilinx")
+ port = os.getenv("PYNQ_PORT", 22)
target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
- model = model.transform(DeployToPYNQ(ip, username, password, target_dir))
+ model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))
# save the model to be able to link it to the parent
model.save(build_dir + "/end2end_tfc_w1a1_pynq_deploy.onnx")
except KeyError:
@@ -289,11 +315,15 @@ def test_end2end_tfc_w1a1_run_on_pynq():
if ip == "":
pytest.skip("PYNQ board IP address not specified")
# produce results with npysim
- sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w1a1_pynq_deploy.onnx")
ret = execute_onnx(parent_model, {iname: x}, True)
y = ret[oname]
assert np.isclose(y, y_golden).all()
+ child_model = ModelWrapper(sdp_node.get_nodeattr("model"))
+ res = throughput_test(child_model)
+ assert res is not None
except KeyError:
pytest.skip("PYNQ board IP address not specified")
diff --git a/tests/end2end/test_end2end_tfc_w1a2.py b/tests/end2end/test_end2end_tfc_w1a2.py
index 6e2505c78cf3e32e99b5d798323b20d558312ee3..52771e6d149810d70f908ac2af07e1d81f8f46ec 100644
--- a/tests/end2end/test_end2end_tfc_w1a2.py
+++ b/tests/end2end/test_end2end_tfc_w1a2.py
@@ -66,11 +66,14 @@ from finn.transformation.infer_shapes import InferShapes
from finn.transformation.streamline import Streamline
from finn.util.basic import pynq_part_map
from finn.util.test import get_test_model_trained
+from finn.transformation.fpgadataflow.annotate_resources import AnnotateResources
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
-target_clk_ns = 5
+target_clk_ns = 10
+mem_mode = "decoupled"
def test_end2end_tfc_w1a2_export():
@@ -100,12 +103,7 @@ def test_end2end_tfc_w1a2_streamline():
def test_end2end_tfc_w1a2_convert_to_hls_layers():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_streamlined.onnx")
- # model = model.transform(ConvertBipolarMatMulToXnorPopcount())
- # model = model.transform(absorb.AbsorbAddIntoMultiThreshold())
- # model = model.transform(absorb.AbsorbMulIntoMultiThreshold())
- # model = model.transform(RoundAndClipThresholds())
- # model = model.transform(to_hls.InferBinaryStreamingFCLayer())
- model = model.transform(to_hls.InferQuantizedStreamingFCLayer())
+ model = model.transform(to_hls.InferQuantizedStreamingFCLayer(mem_mode))
model.save(build_dir + "/end2end_tfc_w1a2_hls_layers.onnx")
@@ -113,7 +111,8 @@ def test_end2end_tfc_w1a2_create_dataflow_partition():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_hls_layers.onnx")
parent_model = model.transform(CreateDataflowPartition())
parent_model.save(build_dir + "/end2end_tfc_w1a2_dataflow_parent.onnx")
- sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
dataflow_model_filename = sdp_node.get_nodeattr("model")
dataflow_model = ModelWrapper(dataflow_model_filename)
dataflow_model.save(build_dir + "/end2end_tfc_w1a2_dataflow_model.onnx")
@@ -121,14 +120,11 @@ def test_end2end_tfc_w1a2_create_dataflow_partition():
def test_end2end_tfc_w1a2_fold_and_tlastmarker():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_dataflow_model.onnx")
- fc0 = model.graph.node[0]
- fc1 = model.graph.node[1]
- fc2 = model.graph.node[2]
- fc3 = model.graph.node[3]
- fc0w = getCustomOp(fc0)
- fc1w = getCustomOp(fc1)
- fc2w = getCustomOp(fc2)
- fc3w = getCustomOp(fc3)
+ fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
+ fc0w = getCustomOp(fc_layers[0])
+ fc1w = getCustomOp(fc_layers[1])
+ fc2w = getCustomOp(fc_layers[2])
+ fc3w = getCustomOp(fc_layers[3])
fc0w.set_nodeattr("inFIFODepth", 50)
fc0w.set_nodeattr("SIMD", 8)
fc0w.set_nodeattr("PE", 16)
@@ -143,14 +139,16 @@ def test_end2end_tfc_w1a2_fold_and_tlastmarker():
fc3w.set_nodeattr("PE", 10)
fc3w.set_nodeattr("outFIFODepth", 50)
model = model.transform(InsertTLastMarker())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(AnnotateResources("estimate"))
model.save(build_dir + "/end2end_tfc_w1a2_folded.onnx")
def test_end2end_tfc_w1a2_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_folded.onnx")
- model = model.transform(GiveUniqueNodeNames())
model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynth_IPGen())
+ model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w1a2_ipgen.onnx")
@@ -176,16 +174,12 @@ def test_end2end_tfc_w1a2_verify_dataflow_part():
res_npysim = ret_npysim[out_name]
# node-by-node rtlsim
model = model.transform(SetExecMode("rtlsim"))
- getCustomOp(model.graph.node[0]).set_nodeattr("rtlsim_trace", "default")
- getCustomOp(model.graph.node[1]).set_nodeattr("rtlsim_trace", "default")
- getCustomOp(model.graph.node[2]).set_nodeattr("rtlsim_trace", "default")
- getCustomOp(model.graph.node[3]).set_nodeattr("rtlsim_trace", "default")
+ model = model.transform(PrepareRTLSim())
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_nodebynode_rtlsim.onnx")
ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
# whole-network (ip-stitched) rtlsim
model.set_metadata_prop("exec_mode", "rtlsim")
- model.set_metadata_prop("rtlsim_trace", "whole_trace.vcd")
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_whole_rtlsim.onnx")
ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
res_rtlsim_whole = ret_rtlsim_whole[out_name]
@@ -210,7 +204,8 @@ def test_end2end_tfc_w1a2_verify_all():
iname = parent_model.graph.input[0].name
oname = parent_model.graph.output[0].name
# produce results with npysim
- sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w1a2_ipstitch_npysim.onnx")
ret_npysim = execute_onnx(parent_model, {iname: x}, True)
y_npysim = ret_npysim[oname]
@@ -240,6 +235,7 @@ def test_end2end_tfc_w1a2_make_pynq_proj():
def test_end2end_tfc_w1a2_synth_pynq_project():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_pynq_project.onnx")
model = model.transform(SynthPYNQProject())
+ model = model.transform(AnnotateResources("synth"))
model.save(build_dir + "/end2end_tfc_w1a2_synth.onnx")
@@ -257,8 +253,9 @@ def test_end2end_tfc_w1a2_deploy_on_pynq():
pytest.skip("PYNQ board IP address not specified")
username = os.getenv("PYNQ_USERNAME", "xilinx")
password = os.getenv("PYNQ_PASSWORD", "xilinx")
+ port = os.getenv("PYNQ_PORT", 22)
target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
- model = model.transform(DeployToPYNQ(ip, username, password, target_dir))
+ model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))
# save the model to be able to link it to the parent
model.save(build_dir + "/end2end_tfc_w1a2_pynq_deploy.onnx")
except KeyError:
@@ -287,7 +284,8 @@ def test_end2end_tfc_w1a2_run_on_pynq():
if ip == "":
pytest.skip("PYNQ board IP address not specified")
# produce results with npysim
- sdp_node = getCustomOp(parent_model.graph.node[2])
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w1a2_pynq_deploy.onnx")
ret = execute_onnx(parent_model, {iname: x}, True)
y = ret[oname]
diff --git a/tests/end2end/test_end2end_tfc_w2a2.py b/tests/end2end/test_end2end_tfc_w2a2.py
new file mode 100644
index 0000000000000000000000000000000000000000..67111da400d475311cc29b45bb24573128981958
--- /dev/null
+++ b/tests/end2end/test_end2end_tfc_w2a2.py
@@ -0,0 +1,295 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+from pkgutil import get_data
+
+import pytest
+
+import numpy as np
+
+# as of Feb'20 there is a bug that segfaults ONNX shape inference if we
+# import pytorch before onnx, so we make sure to import onnx first
+import onnx # NOQA
+import onnx.numpy_helper as nph
+
+import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls
+from finn.core.modelwrapper import ModelWrapper
+from finn.core.onnx_exec import execute_onnx
+from finn.custom_op.registry import getCustomOp
+from finn.transformation.fold_constants import FoldConstants
+from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
+from finn.transformation.fpgadataflow.compile import Compile
+from finn.transformation.fpgadataflow.create_dataflow_partition import (
+ CreateDataflowPartition,
+)
+from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
+from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
+from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
+from finn.transformation.fpgadataflow.make_pynq_proj import MakePYNQProject
+from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
+ ReplaceVerilogRelPaths,
+)
+from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.transformation.fpgadataflow.synth_pynq_proj import SynthPYNQProject
+from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
+from finn.transformation.infer_datatypes import InferDataTypes
+from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.streamline import Streamline
+from finn.util.basic import pynq_part_map
+from finn.util.test import get_test_model_trained
+from finn.transformation.fpgadataflow.annotate_resources import AnnotateResources
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
+
+build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
+test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
+test_fpga_part = pynq_part_map[test_pynq_board]
+target_clk_ns = 10
+mem_mode = "decoupled"
+
+
+def test_end2end_tfc_w2a2_export():
+ import brevitas.onnx as bo
+
+ tfc = get_test_model_trained("TFC", 2, 2)
+ bo.export_finn_onnx(
+ tfc, (1, 1, 28, 28), build_dir + "/end2end_tfc_w2a2_export.onnx"
+ )
+
+
+def test_end2end_tfc_w2a2_import_and_tidy():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_export.onnx")
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(GiveReadableTensorNames())
+ model = model.transform(InferDataTypes())
+ model.save(build_dir + "/end2end_tfc_w2a2_tidy.onnx")
+
+
+def test_end2end_tfc_w2a2_streamline():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_tidy.onnx")
+ model = model.transform(Streamline())
+ model.save(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+
+
+def test_end2end_tfc_w2a2_convert_to_hls_layers():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+ model = model.transform(to_hls.InferQuantizedStreamingFCLayer(mem_mode))
+ model.save(build_dir + "/end2end_tfc_w2a2_hls_layers.onnx")
+
+
+def test_end2end_tfc_w2a2_create_dataflow_partition():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_hls_layers.onnx")
+ parent_model = model.transform(CreateDataflowPartition())
+ parent_model.save(build_dir + "/end2end_tfc_w2a2_dataflow_parent.onnx")
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
+ dataflow_model_filename = sdp_node.get_nodeattr("model")
+ dataflow_model = ModelWrapper(dataflow_model_filename)
+ dataflow_model.save(build_dir + "/end2end_tfc_w2a2_dataflow_model.onnx")
+
+
+def test_end2end_tfc_w2a2_fold_and_tlastmarker():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_dataflow_model.onnx")
+ fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
+ fc0w = getCustomOp(fc_layers[0])
+ fc1w = getCustomOp(fc_layers[1])
+ fc2w = getCustomOp(fc_layers[2])
+ fc3w = getCustomOp(fc_layers[3])
+ fc0w.set_nodeattr("inFIFODepth", 50)
+ fc0w.set_nodeattr("SIMD", 8)
+ fc0w.set_nodeattr("PE", 16)
+ fc0w.set_nodeattr("outFIFODepth", 4)
+ fc1w.set_nodeattr("SIMD", 16)
+ fc1w.set_nodeattr("PE", 16)
+ fc1w.set_nodeattr("outFIFODepth", 4)
+ fc2w.set_nodeattr("SIMD", 16)
+ fc2w.set_nodeattr("PE", 16)
+ fc2w.set_nodeattr("outFIFODepth", 4)
+ fc3w.set_nodeattr("SIMD", 16)
+ fc3w.set_nodeattr("PE", 10)
+ fc3w.set_nodeattr("outFIFODepth", 50)
+ model = model.transform(InsertTLastMarker())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(AnnotateResources("estimate"))
+ model.save(build_dir + "/end2end_tfc_w2a2_folded.onnx")
+
+
+def test_end2end_tfc_w2a2_gen_hls_ip():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_folded.onnx")
+ model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(HLSSynth_IPGen())
+ model = model.transform(AnnotateResources("hls"))
+ model.save(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
+
+
+def test_end2end_tfc_w2a2_ip_stitch():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
+ model = model.transform(ReplaceVerilogRelPaths())
+ model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
+
+
+def test_end2end_tfc_w2a2_verify_dataflow_part():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
+ x = np.zeros((1, 784), dtype=np.float32)
+ inp_name = model.graph.input[0].name
+ out_name = model.graph.output[0].name
+ inp_dict = {inp_name: x}
+ # npysim
+ model = model.transform(CodeGen_npysim())
+ model = model.transform(Compile())
+ model = model.transform(SetExecMode("npysim"))
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch_npysim.onnx")
+ ret_npysim = execute_onnx(model, inp_dict, True)
+ res_npysim = ret_npysim[out_name]
+ # node-by-node rtlsim
+ model = model.transform(SetExecMode("rtlsim"))
+ model = model.transform(PrepareRTLSim())
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch_nodebynode_rtlsim.onnx")
+ ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
+ res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
+ # whole-network (ip-stitched) rtlsim
+ model.set_metadata_prop("exec_mode", "rtlsim")
+ model.save(build_dir + "/end2end_tfc_w2a2_ipstitch_whole_rtlsim.onnx")
+ ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
+ res_rtlsim_whole = ret_rtlsim_whole[out_name]
+ assert np.isclose(res_npysim, res_rtlsim_nodebynode).all()
+ assert np.isclose(res_npysim, res_rtlsim_whole).all()
+
+
+def test_end2end_tfc_w2a2_verify_all():
+ # use the streamlined model as the "golden" model for right answers
+ golden = ModelWrapper(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+ iname = golden.graph.input[0].name
+ oname = golden.graph.output[0].name
+ raw_i = get_data("finn", "data/onnx/mnist-conv/test_data_set_0/input_0.pb")
+ input_tensor = onnx.load_tensor_from_string(raw_i)
+ x = nph.to_array(input_tensor)
+ # x = np.zeros(ishape, dtype=np.float32)
+ ret_golden = execute_onnx(golden, {iname: x}, True)
+ y_golden = ret_golden[oname]
+ # set up parent+child graph to test
+ # we'll use models from the previous step as the child model
+ parent_model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_dataflow_parent.onnx")
+ iname = parent_model.graph.input[0].name
+ oname = parent_model.graph.output[0].name
+ # produce results with npysim
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
+ sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w2a2_ipstitch_npysim.onnx")
+ ret_npysim = execute_onnx(parent_model, {iname: x}, True)
+ y_npysim = ret_npysim[oname]
+ # produce results with node-by-node rtlsim
+ sdp_node.set_nodeattr(
+ "model", build_dir + "/end2end_tfc_w2a2_ipstitch_nodebynode_rtlsim.onnx"
+ )
+ ret_nodebynode_rtlsim = execute_onnx(parent_model, {iname: x}, True)
+ y_nodebynode_rtlsim = ret_nodebynode_rtlsim[oname]
+ # produce results with whole-network (stitched ip) rtlsim
+ sdp_node.set_nodeattr(
+ "model", build_dir + "/end2end_tfc_w2a2_ipstitch_whole_rtlsim.onnx"
+ )
+ ret_whole_rtlsim = execute_onnx(parent_model, {iname: x}, True)
+ y_whole_rtlsim = ret_whole_rtlsim[oname]
+ assert np.isclose(y_golden, y_npysim).all()
+ assert np.isclose(y_golden, y_nodebynode_rtlsim).all()
+ assert np.isclose(y_golden, y_whole_rtlsim).all()
+
+
+def test_end2end_tfc_w2a2_make_pynq_proj():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
+ model = model.transform(MakePYNQProject(test_pynq_board))
+ model.save(build_dir + "/end2end_tfc_w2a2_pynq_project.onnx")
+
+
+def test_end2end_tfc_w2a2_synth_pynq_project():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_pynq_project.onnx")
+ model = model.transform(SynthPYNQProject())
+ model = model.transform(AnnotateResources("synth"))
+ model.save(build_dir + "/end2end_tfc_w2a2_synth.onnx")
+
+
+def test_end2end_tfc_w2a2_make_driver():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_synth.onnx")
+ model = model.transform(MakePYNQDriver())
+ model.save(build_dir + "/end2end_tfc_w2a2_pynq_driver.onnx")
+
+
+def test_end2end_tfc_w2a2_deploy_on_pynq():
+ model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_pynq_driver.onnx")
+ try:
+ ip = os.environ["PYNQ_IP"] # no fault for this one; skip if not defined
+ if ip == "":
+ pytest.skip("PYNQ board IP address not specified")
+ username = os.getenv("PYNQ_USERNAME", "xilinx")
+ password = os.getenv("PYNQ_PASSWORD", "xilinx")
+ port = os.getenv("PYNQ_PORT", 22)
+ target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
+ model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))
+ # save the model to be able to link it to the parent
+ model.save(build_dir + "/end2end_tfc_w2a2_pynq_deploy.onnx")
+ except KeyError:
+ pytest.skip("PYNQ board IP address not specified")
+
+
+def test_end2end_tfc_w2a2_run_on_pynq():
+ # use the streamlined model as the "golden" model for right answers
+ golden = ModelWrapper(build_dir + "/end2end_tfc_w2a2_streamlined.onnx")
+ iname = golden.graph.input[0].name
+ oname = golden.graph.output[0].name
+ raw_i = get_data("finn", "data/onnx/mnist-conv/test_data_set_0/input_0.pb")
+ input_tensor = onnx.load_tensor_from_string(raw_i)
+ x = nph.to_array(input_tensor)
+ # x = np.zeros(ishape, dtype=np.float32)
+ # run using FINN-based execution
+ ret_golden = execute_onnx(golden, {iname: x}, True)
+ y_golden = ret_golden[oname]
+ # set up parent+child graph to test
+ # we'll use models from the previous step as the child model
+ parent_model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_dataflow_parent.onnx")
+ iname = parent_model.graph.input[0].name
+ oname = parent_model.graph.output[0].name
+ try:
+ ip = os.environ["PYNQ_IP"] # NOQA
+ if ip == "":
+ pytest.skip("PYNQ board IP address not specified")
+ # produce results with npysim
+ sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]
+ sdp_node = getCustomOp(sdp_node)
+ sdp_node.set_nodeattr("model", build_dir + "/end2end_tfc_w2a2_pynq_deploy.onnx")
+ ret = execute_onnx(parent_model, {iname: x}, True)
+ y = ret[oname]
+ assert np.isclose(y, y_golden).all()
+
+ except KeyError:
+ pytest.skip("PYNQ board IP address not specified")
diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py
new file mode 100644
index 0000000000000000000000000000000000000000..4effc0da9702850565d2651819d64f1ab3489877
--- /dev/null
+++ b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py
@@ -0,0 +1,122 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import pkg_resources as pk
+
+import brevitas.onnx as bo
+import numpy as np
+
+import finn.core.onnx_exec as oxe
+import finn.transformation.streamline.absorb as absorb
+from finn.transformation.streamline.reorder import MakeMaxPoolNHWC
+from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.fold_constants import FoldConstants
+from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
+from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.streamline import Streamline
+from finn.util.test import get_test_model_trained
+from finn.transformation.double_to_single_float import DoubleToSingleFloat
+from finn.transformation.lower_convs_to_matmul import LowerConvsToMatMul
+from finn.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount
+import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls
+from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
+from finn.transformation.fpgadataflow.compile import Compile
+from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.custom_op.registry import getCustomOp
+
+export_onnx_path_cnv = "test_output_cnv.onnx"
+
+
+def test_convert_to_hls_layers_cnv_w1a1():
+ cnv = get_test_model_trained("CNV", 1, 1)
+ bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path_cnv)
+ model = ModelWrapper(export_onnx_path_cnv)
+ model = model.transform(DoubleToSingleFloat())
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(GiveReadableTensorNames())
+ model = model.transform(Streamline())
+ model = model.transform(LowerConvsToMatMul())
+ model = model.transform(MakeMaxPoolNHWC())
+ model = model.transform(absorb.AbsorbTransposeIntoMultiThreshold())
+ model = model.transform(ConvertBipolarMatMulToXnorPopcount())
+ model = model.transform(Streamline())
+ # model.save("golden.onnx")
+ # load one of the test vectors
+ fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
+ input_tensor = np.load(fn)["arr_0"].astype(np.float32)
+ assert input_tensor.shape == (1, 3, 32, 32)
+ # generate expected value from streamlined net
+ input_dict = {"global_in": input_tensor}
+ expected_ctx = oxe.execute_onnx(model, input_dict, True)
+ expected = expected_ctx[model.graph.output[0].name]
+
+ model = model.transform(to_hls.InferBinaryStreamingFCLayer())
+ model = model.transform(to_hls.InferQuantizedStreamingFCLayer())
+ for node in model.graph.node:
+ if node.op_type == "StreamingFCLayer_Batch":
+ inst = getCustomOp(node)
+ inst.set_nodeattr("mem_mode", "decoupled")
+ mw = inst.get_nodeattr("MW")
+ mh = inst.get_nodeattr("MH")
+ if mh % 4 == 0:
+ pe = mh // 4
+ else:
+ pe = mh
+ inst.set_nodeattr("PE", pe)
+ if mw % 16 == 0:
+ simd = mw // 16
+ else:
+ simd = mw
+ inst.set_nodeattr("SIMD", simd)
+ model = model.transform(to_hls.InferConvInpGen())
+ model = model.transform(to_hls.InferStreamingMaxPool())
+ # check topology status
+ finn_nodes = model.get_finn_nodes()
+ assert len(finn_nodes) == 18
+ non_finn_nodes = model.get_non_finn_nodes()
+ assert len(non_finn_nodes) == 4
+ exp_non_finn_nodes = ["Transpose", "Reshape", "Mul", "Add"]
+ assert [x.op_type for x in non_finn_nodes] == exp_non_finn_nodes
+ fc_nodes = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
+ assert len(fc_nodes) == 9
+ swg_nodes = model.get_nodes_by_op_type("ConvolutionInputGenerator")
+ assert len(swg_nodes) == 6
+ mp_nodes = model.get_nodes_by_op_type("StreamingMaxPool_Batch")
+ assert len(mp_nodes) == 2
+ # model.save("cnv-pre-compile.onnx")
+ model = model.transform(CodeGen_npysim())
+ model = model.transform(Compile())
+ model = model.transform(SetExecMode("npysim"))
+ # model.save("cnv-post-compile.onnx")
+ produced_ctx = oxe.execute_onnx(model, input_dict, True)
+ produced = produced_ctx[model.graph.output[0].name]
+ assert np.isclose(expected, produced, atol=1e-3).all()
+ os.remove(export_onnx_path_cnv)
diff --git a/tests/fpgadataflow/test_convert_to_hls_layers.py b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py
similarity index 99%
rename from tests/fpgadataflow/test_convert_to_hls_layers.py
rename to tests/fpgadataflow/test_convert_to_hls_layers_fc.py
index cc9b9515b46ca9d51045560b70baaab4fe9f66f3..1a2d65de001a484fc41dbe63a38194a254ac8490 100644
--- a/tests/fpgadataflow/test_convert_to_hls_layers.py
+++ b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py
@@ -51,7 +51,9 @@ from finn.transformation.streamline import Streamline
from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds
from finn.util.test import get_test_model_trained
+
export_onnx_path = "test_output_tfc.onnx"
+export_onnx_path_cnv = "test_output_cnv.onnx"
def test_convert_to_hls_layers_tfc_w1a1():
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
index d2740feb662faddf0286e46688cbfc48c36c6bd0..7c19ebbfaeed09cb1e367cf6567e5b149aa4236c 100644
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py
@@ -28,7 +28,6 @@
import pytest
-import numpy as np
from onnx import TensorProto, helper
import finn.core.onnx_exec as oxe
@@ -39,79 +38,54 @@ from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
from finn.transformation.fpgadataflow.compile import Compile
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
from finn.transformation.general import GiveUniqueNodeNames
from finn.util.basic import gen_finn_dt_tensor
-def get_im2col_indices(x_shape, k, stride):
- # First figure out what the size of the output should be
- N, C, H, W = x_shape
- assert H == W
- assert (W - k) % stride == 0
- ofm_dim = int((W - k) / stride + 1)
-
- i0 = np.repeat(np.arange(k), k)
- i0 = np.tile(i0, C)
- i1 = stride * np.repeat(np.arange(ofm_dim), ofm_dim)
- j0 = np.tile(np.arange(k), k * C)
- j1 = stride * np.tile(np.arange(ofm_dim), ofm_dim)
- i = i0.reshape(-1, 1) + i1.reshape(1, -1)
- j = j0.reshape(-1, 1) + j1.reshape(1, -1)
-
- k = np.repeat(np.arange(C), k * k).reshape(-1, 1)
-
- return (k, i, j)
-
-
-def im2col_indices(x, k, stride):
- """ An implementation of im2col based on some fancy indexing """
-
- l, i, j = get_im2col_indices(x.shape, k, stride)
+def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, simd, stride, idt):
+ odt = idt
+ inp = helper.make_tensor_value_info(
+ "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]
+ )
+ outp = helper.make_tensor_value_info(
+ "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch]
+ )
- cols = x[:, l, i, j]
- C = x.shape[1]
- cols = cols.transpose(1, 2, 0).reshape(k * k * C, -1)
- cols = cols.transpose(1, 0)
+ im2col_node = helper.make_node(
+ "Im2Col",
+ ["inp"],
+ ["outp"],
+ domain="finn",
+ backend="fpgadataflow",
+ stride=stride,
+ kernel_size=k,
+ input_shape=str((1, ifm_dim, ifm_dim, ifm_ch)),
+ pad_amount=0,
+ pad_value=0,
+ )
+ graph = helper.make_graph(
+ nodes=[im2col_node], name="im2col_graph", inputs=[inp], outputs=[outp]
+ )
- # rearranging the output so it matches with finn-hlslib function
- # swapping the columns according to the input channel
- # if C > 1 :
- parts = {}
- for ch in range(C):
- parts[ch] = []
+ model = helper.make_model(graph, producer_name="im2col-model")
+ model = ModelWrapper(model)
- for i in range(cols.shape[1]):
- if i % C == 0:
- parts[0].append(i)
- elif (i + (C - 1)) % C == 0:
- parts[1].append(i)
- elif (i + (C - 2)) % C == 0:
- parts[2].append(i)
- elif (i + (C - 3)) % C == 0:
- parts[3].append(i)
- permutation = []
- for i in parts:
- for num in parts[i]:
- permutation.append(num)
+ model.set_tensor_datatype("inp", idt)
+ model.set_tensor_datatype("outp", odt)
- i = np.argsort(permutation)
- cols = cols[:, i]
- return cols
+ return model
def make_single_slidingwindow_modelwrapper(
k, ifm_ch, ifm_dim, ofm_dim, simd, stride, idt
):
-
- ip = idt.bitwidth()
odt = idt
- out_pix = ofm_dim * ofm_dim
-
inp = helper.make_tensor_value_info(
- "inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim, ifm_dim]
+ "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]
)
outp = helper.make_tensor_value_info(
- "outp", TensorProto.FLOAT, [1, out_pix, k * k * ifm_ch]
+ "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch]
)
SlidingWindow_node = helper.make_node(
@@ -122,7 +96,6 @@ def make_single_slidingwindow_modelwrapper(
backend="fpgadataflow",
ConvKernelDim=k,
IFMChannels=ifm_ch,
- Input_precision=ip,
IFMDim=ifm_dim,
OFMDim=ofm_dim,
SIMD=simd,
@@ -146,12 +119,8 @@ def make_single_slidingwindow_modelwrapper(
return model
-def prepare_inputs(input_tensor, idt):
- if idt == DataType.BIPOLAR:
- # convert bipolar to binary
- return {"inp": (input_tensor + 1) / 2}
- else:
- return {"inp": input_tensor}
+def prepare_inputs(input_tensor):
+ return {"inp": input_tensor}
# input datatype
@@ -161,36 +130,42 @@ def prepare_inputs(input_tensor, idt):
# input dimension
@pytest.mark.parametrize("ifm_dim", [4, 6, 8])
# input channels
-@pytest.mark.parametrize("ifm_ch", [1]) # , 2, 3, 4])
+@pytest.mark.parametrize("ifm_ch", [2, 4]) # , 2, 3, 4])
# Stride
@pytest.mark.parametrize("stride", [1, 2])
-def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride):
- simd = ifm_ch
+# execution mode
+@pytest.mark.parametrize("exec_mode", ["npysim", "rtlsim"])
+# input channel parallelism ("SIMD")
+@pytest.mark.parametrize("simd", [1, 2])
+def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, exec_mode, simd):
ofm_dim = int(((ifm_dim - k) / stride) + 1)
- x = gen_finn_dt_tensor(idt, (1, ifm_ch, ifm_dim, ifm_dim))
+ x = gen_finn_dt_tensor(idt, (1, ifm_dim, ifm_dim, ifm_ch))
model = make_single_slidingwindow_modelwrapper(
k, ifm_ch, ifm_dim, ofm_dim, simd, stride, idt
)
- model = model.transform(SetExecMode("npysim"))
- model = model.transform(CodeGen_npysim())
- model = model.transform(Compile())
- # prepare input data
- input_dict = prepare_inputs(x, idt)
+ if exec_mode == "npysim":
+ model = model.transform(SetExecMode("npysim"))
+ model = model.transform(CodeGen_npysim())
+ model = model.transform(Compile())
+ elif exec_mode == "rtlsim":
+ model = model.transform(SetExecMode("rtlsim"))
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(HLSSynth_IPGen())
+ model = model.transform(PrepareRTLSim())
+ else:
+ raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow")
+ # prepare input data
+ input_dict = prepare_inputs(x)
# execute model
y_produced = oxe.execute_onnx(model, input_dict)["outp"]
- y_expected = im2col_indices(x, k, stride)
- # reshape expected output to match node output
- oshape = y_produced.shape
- y_expected = y_expected.reshape(oshape)
-
- assert (y_produced == y_expected).all(), "npysim failed"
-
- model = model.transform(SetExecMode("rtlsim"))
- model = model.transform(GiveUniqueNodeNames())
- model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
- model = model.transform(HLSSynth_IPGen())
- y_produced = oxe.execute_onnx(model, input_dict)["outp"]
- assert (y_produced == y_expected).all(), "rtlsim failed"
+ golden = make_single_im2col_modelwrapper(
+ k, ifm_ch, ifm_dim, ofm_dim, simd, stride, idt
+ )
+ y_expected = oxe.execute_onnx(golden, input_dict)["outp"]
+ # if idt == DataType.BIPOLAR:
+ # y_expected = 2 * y_expected - 1
+ assert (y_produced == y_expected).all()
diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py
new file mode 100644
index 0000000000000000000000000000000000000000..1465881830b4fec61d1b1aa6e8465a41766fd9de
--- /dev/null
+++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py
@@ -0,0 +1,77 @@
+import pytest
+
+from onnx import TensorProto, helper
+
+from finn.core.datatype import DataType
+from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
+from finn.transformation.general import GiveUniqueNodeNames
+from finn.util.basic import gen_finn_dt_tensor
+import finn.core.onnx_exec as oxe
+
+
+def make_single_dwc_modelwrapper(Shape, INWidth, OUTWidth, finn_dtype):
+
+ inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, Shape)
+ outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, Shape)
+
+ DWC_node = helper.make_node(
+ "StreamingDataWidthConverter_Batch",
+ ["inp"],
+ ["outp"],
+ domain="finn",
+ backend="fpgadataflow",
+ shape=Shape,
+ inWidth=INWidth,
+ outWidth=OUTWidth,
+ dataType=str(finn_dtype.name),
+ )
+
+ graph = helper.make_graph(
+ nodes=[DWC_node], name="dwc_graph", inputs=[inp], outputs=[outp]
+ )
+
+ model = helper.make_model(graph, producer_name="dwc-model")
+ model = ModelWrapper(model)
+
+ model.set_tensor_datatype("inp", finn_dtype)
+ model.set_tensor_datatype("outp", finn_dtype)
+
+ return model
+
+
+def prepare_inputs(input_tensor, dt):
+ return {"inp": input_tensor}
+
+
+# shape
+@pytest.mark.parametrize("Shape", [[1, 4], [1, 2, 8]])
+# inWidth
+@pytest.mark.parametrize("INWidth", [2, 4])
+# outWidth
+@pytest.mark.parametrize("OUTWidth", [2, 4])
+# finn_dtype
+@pytest.mark.parametrize("finn_dtype", [DataType.BIPOLAR, DataType.INT2])
+def test_fpgadataflow_dwc_rtlsim(Shape, INWidth, OUTWidth, finn_dtype):
+
+ # generate input data
+ x = gen_finn_dt_tensor(finn_dtype, Shape)
+ input_dict = prepare_inputs(x, finn_dtype)
+
+ model = make_single_dwc_modelwrapper(Shape, INWidth, OUTWidth, finn_dtype)
+
+ model = model.transform(SetExecMode("rtlsim"))
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(HLSSynth_IPGen())
+ model = model.transform(PrepareRTLSim())
+ y = oxe.execute_onnx(model, input_dict)["outp"]
+
+ assert (
+ y == x
+ ).all(), """The output values are not the same as the
+ input values anymore."""
+ assert y.shape == tuple(Shape), """The output shape is incorrect."""
diff --git a/tests/fpgadataflow/test_fpgadataflow_fclayer.py b/tests/fpgadataflow/test_fpgadataflow_fclayer.py
index 93bf0750776331af236154d8f2a005913cbb1c33..7552fecd85ee0e36216f6c934d454f057a2a41ce 100644
--- a/tests/fpgadataflow/test_fpgadataflow_fclayer.py
+++ b/tests/fpgadataflow/test_fpgadataflow_fclayer.py
@@ -31,6 +31,7 @@ import pytest
import numpy as np
from onnx import TensorProto, helper
+from finn.custom_op.registry import getCustomOp
import finn.core.onnx_exec as oxe
import finn.custom_op.xnorpopcount as xp
from finn.analysis.fpgadataflow.hls_synth_res_estimation import hls_synth_res_estimation
@@ -43,7 +44,11 @@ from finn.transformation.fpgadataflow.compile import Compile
from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.general import GiveUniqueNodeNames
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
from finn.util.basic import calculate_signed_dot_prod_range, gen_finn_dt_tensor
+from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
+ ReplaceVerilogRelPaths,
+)
def make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T=None, tdt=None):
@@ -128,21 +133,23 @@ def prepare_inputs(input_tensor, idt, wdt):
return {"inp": input_tensor}
+# mem_mode: const or decoupled
+@pytest.mark.parametrize("mem_mode", ["const", "decoupled"])
# activation: None or DataType
-@pytest.mark.parametrize("act", [None, DataType.BIPOLAR, DataType.INT2])
+@pytest.mark.parametrize("act", [None, DataType.BIPOLAR, DataType.INT4])
# weight datatype
-@pytest.mark.parametrize("wdt", [DataType.BIPOLAR, DataType.INT2])
+@pytest.mark.parametrize("wdt", [DataType.BIPOLAR, DataType.INT4])
# input datatype
-@pytest.mark.parametrize("idt", [DataType.BIPOLAR, DataType.INT2])
+@pytest.mark.parametrize("idt", [DataType.BIPOLAR, DataType.INT4])
# neuron folding, -1 is maximum possible
-@pytest.mark.parametrize("nf", [-1, 1])
+@pytest.mark.parametrize("nf", [-1, 2, 1])
# synapse folding, -1 is maximum possible
-@pytest.mark.parametrize("sf", [-1, 1])
+@pytest.mark.parametrize("sf", [-1, 2, 1])
# HLS matrix width (input features)
-@pytest.mark.parametrize("mw", [4])
+@pytest.mark.parametrize("mw", [16])
# HLS matrix height (output features)
-@pytest.mark.parametrize("mh", [4])
-def test_fpgadataflow_fclayer_npysim(idt, wdt, act, nf, sf, mw, mh):
+@pytest.mark.parametrize("mh", [16])
+def test_fpgadataflow_fclayer_npysim(mem_mode, idt, wdt, act, nf, sf, mw, mh):
if nf == -1:
nf = mh
if sf == -1:
@@ -179,6 +186,10 @@ def test_fpgadataflow_fclayer_npysim(idt, wdt, act, nf, sf, mw, mh):
else:
tdt = DataType.INT32
model = make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T, tdt)
+ for node in model.graph.node:
+ # lookup op_type in registry of CustomOps
+ inst = getCustomOp(node)
+ inst.set_nodeattr("mem_mode", mem_mode)
model = model.transform(SetExecMode("npysim"))
model = model.transform(CodeGen_npysim())
model = model.transform(Compile())
@@ -201,24 +212,29 @@ def test_fpgadataflow_fclayer_npysim(idt, wdt, act, nf, sf, mw, mh):
y_expected = y.reshape(oshape)
# execute model
y_produced = oxe.execute_onnx(model, input_dict)["outp"]
- assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "npysim failed"
+ y_produced = y_produced.reshape(y_expected.shape)
+
+ assert (y_produced == y_expected).all(), "npysim failed"
+
+# mem_mode: const or decoupled
+@pytest.mark.parametrize("mem_mode", ["const", "decoupled"])
# activation: None or DataType
-@pytest.mark.parametrize("act", [None, DataType.BIPOLAR, DataType.INT2])
+@pytest.mark.parametrize("act", [None, DataType.BIPOLAR, DataType.INT4])
# weight datatype
-@pytest.mark.parametrize("wdt", [DataType.BIPOLAR, DataType.INT2])
+@pytest.mark.parametrize("wdt", [DataType.BIPOLAR, DataType.INT4])
# input datatype
-@pytest.mark.parametrize("idt", [DataType.BIPOLAR, DataType.INT2])
+@pytest.mark.parametrize("idt", [DataType.BIPOLAR, DataType.INT4])
# neuron folding, -1 is maximum possible
@pytest.mark.parametrize("nf", [-1, 2, 1])
# synapse folding, -1 is maximum possible
@pytest.mark.parametrize("sf", [-1, 2, 1])
# HLS matrix width (input features)
-@pytest.mark.parametrize("mw", [4])
+@pytest.mark.parametrize("mw", [16])
# HLS matrix height (output features)
-@pytest.mark.parametrize("mh", [4])
-def test_fpgadataflow_fclayer_rtlsim(idt, wdt, act, nf, sf, mw, mh):
+@pytest.mark.parametrize("mh", [16])
+def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh):
if nf == -1:
nf = mh
if sf == -1:
@@ -255,6 +271,103 @@ def test_fpgadataflow_fclayer_rtlsim(idt, wdt, act, nf, sf, mw, mh):
else:
tdt = DataType.INT32
model = make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T, tdt)
+ for node in model.graph.node:
+ # lookup op_type in registry of CustomOps
+ inst = getCustomOp(node)
+ inst.set_nodeattr("mem_mode", mem_mode)
+
+ # prepare input data
+ input_dict = prepare_inputs(x, idt, wdt)
+ if wdt == DataType.BIPOLAR and idt == DataType.BIPOLAR:
+ # convert inputs to binary and use xnorpopcountmatmul
+ y = xp.xnorpopcountmatmul((x + 1) / 2, (W + 1) / 2)
+ else:
+ y = np.matmul(x, W)
+ if T is not None:
+ y = multithreshold(y, T)
+ if act == DataType.BIPOLAR:
+ # binary to bipolar
+ y = 2 * y - 1
+ else:
+ # signed offset
+ y += act.min()
+ oshape = model.get_tensor_shape("outp")
+ y_expected = y.reshape(oshape)
+ # TODO split up into several dependent tests -- need to check how this
+ # works for parametrized tests...
+ model = model.transform(SetExecMode("rtlsim"))
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(HLSSynth_IPGen())
+ model = model.transform(ReplaceVerilogRelPaths())
+ model = model.transform(PrepareRTLSim())
+ y_produced = oxe.execute_onnx(model, input_dict)["outp"]
+ assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed"
+
+ hls_synt_res_est = model.analysis(hls_synth_res_estimation)
+ assert "StreamingFCLayer_Batch_0" in hls_synt_res_est
+
+
+# mem_mode: const or decoupled
+@pytest.mark.parametrize("mem_mode", ["decoupled"])
+# activation: None or DataType
+@pytest.mark.parametrize("act", [DataType.INT4])
+# weight datatype
+@pytest.mark.parametrize("wdt", [DataType.INT4])
+# input datatype
+@pytest.mark.parametrize("idt", [DataType.INT4])
+# neuron folding, -1 is maximum possible
+@pytest.mark.parametrize("nf", [-1])
+# synapse folding, -1 is maximum possible
+@pytest.mark.parametrize("sf", [-1])
+# HLS matrix width (input features)
+@pytest.mark.parametrize("mw", [128])
+# HLS matrix height (output features)
+@pytest.mark.parametrize("mh", [128])
+def test_fpgadataflow_fclayer_large_depth_decoupled_mode(
+ mem_mode, idt, wdt, act, nf, sf, mw, mh
+):
+ if nf == -1:
+ nf = mh
+ if sf == -1:
+ sf = mw
+ pe = mh // nf
+ simd = mw // sf
+ assert mh % pe == 0
+ assert mw % sf == 0
+ # generate weights
+ W = gen_finn_dt_tensor(wdt, (mw, mh))
+ # generate input data
+ x = gen_finn_dt_tensor(idt, (1, mw))
+ if act is None:
+ # no activation, produce accumulators
+ T = None
+ tdt = None
+ if wdt == DataType.BIPOLAR and idt == DataType.BIPOLAR:
+ odt = DataType.UINT32
+ else:
+ odt = DataType.INT32
+ else:
+ odt = act
+ (min, max) = calculate_signed_dot_prod_range(idt, wdt, mw)
+ n_steps = act.get_num_possible_values() - 1
+ T = np.random.randint(min, max - 1, (mh, n_steps)).astype(np.float32)
+ # provide non-decreasing thresholds
+ T = np.sort(T, axis=1)
+ # generate thresholds for activation
+ if wdt == DataType.BIPOLAR and idt == DataType.BIPOLAR:
+ tdt = DataType.UINT32
+ # bias thresholds to be positive
+ T = np.ceil((T + mw) / 2)
+ assert (T >= 0).all()
+ else:
+ tdt = DataType.INT32
+ model = make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T, tdt)
+ for node in model.graph.node:
+ # lookup op_type in registry of CustomOps
+ inst = getCustomOp(node)
+ inst.set_nodeattr("mem_mode", mem_mode)
+
# prepare input data
input_dict = prepare_inputs(x, idt, wdt)
if wdt == DataType.BIPOLAR and idt == DataType.BIPOLAR:
@@ -278,6 +391,8 @@ def test_fpgadataflow_fclayer_rtlsim(idt, wdt, act, nf, sf, mw, mh):
model = model.transform(GiveUniqueNodeNames())
model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
model = model.transform(HLSSynth_IPGen())
+ model = model.transform(ReplaceVerilogRelPaths())
+ model = model.transform(PrepareRTLSim())
y_produced = oxe.execute_onnx(model, input_dict)["outp"]
assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed"
diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py
new file mode 100644
index 0000000000000000000000000000000000000000..8ab4809928d91d8456b7720f897763b206c4e5f5
--- /dev/null
+++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py
@@ -0,0 +1,124 @@
+import pytest
+import os
+
+from onnx import TensorProto, helper
+
+from finn.core.datatype import DataType
+from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
+from finn.transformation.fpgadataflow.codegen_ipstitch import CodeGen_ipstitch
+
+from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
+
+from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.transformation.general import GiveUniqueNodeNames
+
+from finn.util.basic import gen_finn_dt_tensor
+
+import finn.core.onnx_exec as oxe
+from finn.transformation.fpgadataflow.insert_tlastmarker import InsertTLastMarker
+from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
+from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
+from finn.transformation.fpgadataflow.make_pynq_proj import MakePYNQProject
+from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
+ ReplaceVerilogRelPaths,
+)
+from finn.transformation.fpgadataflow.synth_pynq_proj import SynthPYNQProject
+from finn.util.basic import pynq_part_map
+from finn.core.throughput_test import throughput_test
+
+
+build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
+test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
+test_fpga_part = pynq_part_map[test_pynq_board]
+target_clk_ns = 10
+
+
+def make_single_fifo_modelwrapper(Shape, Depth, fld_shape, finn_dtype):
+
+ inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, Shape)
+ outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, Shape)
+
+ FIFO_node = helper.make_node(
+ "StreamingFIFO",
+ ["inp"],
+ ["outp"],
+ domain="finn",
+ backend="fpgadataflow",
+ depth=Depth,
+ folded_shape=fld_shape,
+ dataType=str(finn_dtype.name),
+ )
+
+ graph = helper.make_graph(
+ nodes=[FIFO_node], name="fifo_graph", inputs=[inp], outputs=[outp]
+ )
+
+ model = helper.make_model(graph, producer_name="fifo-model")
+ model = ModelWrapper(model)
+
+ model.set_tensor_datatype("inp", finn_dtype)
+ model.set_tensor_datatype("outp", finn_dtype)
+
+ return model
+
+
+def prepare_inputs(input_tensor, dt):
+ return {"inp": input_tensor}
+
+
+# shape
+@pytest.mark.parametrize("Shape", [[1, 128]])
+# inWidth
+@pytest.mark.parametrize("folded_shape", [[1, 1, 128]])
+# outWidth
+@pytest.mark.parametrize("depth", [16])
+# finn_dtype
+@pytest.mark.parametrize("finn_dtype", [DataType.BIPOLAR]) # , DataType.INT2])
+def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
+
+ # generate input data
+ x = gen_finn_dt_tensor(finn_dtype, Shape)
+ input_dict = prepare_inputs(x, finn_dtype)
+
+ model = make_single_fifo_modelwrapper(Shape, depth, folded_shape, finn_dtype)
+
+ model = model.transform(SetExecMode("rtlsim"))
+ model = model.transform(InsertTLastMarker())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(CodeGen_ipgen(test_fpga_part, target_clk_ns))
+ model = model.transform(HLSSynth_IPGen())
+ model = model.transform(PrepareRTLSim())
+ y = oxe.execute_onnx(model, input_dict)["outp"]
+ assert (
+ y == x
+ ).all(), """The output values are not the same as the
+ input values anymore."""
+ assert y.shape == tuple(Shape), """The output shape is incorrect."""
+
+ model = model.transform(ReplaceVerilogRelPaths())
+ model = model.transform(CodeGen_ipstitch(test_fpga_part))
+ model = model.transform(MakePYNQProject(test_pynq_board))
+ model = model.transform(SynthPYNQProject())
+ model = model.transform(MakePYNQDriver())
+ ip = os.environ["PYNQ_IP"]
+ username = os.getenv("PYNQ_USERNAME", "xilinx")
+ password = os.getenv("PYNQ_PASSWORD", "xilinx")
+ port = os.getenv("PYNQ_PORT", 22)
+ target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
+ model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))
+
+ res = throughput_test(model)
+ expected_dict = {}
+ expected_dict["runtime[ms]"] = []
+ expected_dict["throughput[images/s]"] = []
+ expected_dict["DRAM_in_bandwidth[Mb/s]"] = []
+ expected_dict["DRAM_out_bandwidth[Mb/s]"] = []
+ for key in expected_dict:
+ assert (
+ key in res
+ ), """Throughput test not successful, no value for {}
+ in result dictionary""".format(
+ key
+ )
diff --git a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
index eeff14c4d7c4aa8213f8673d9dd6a4745ececb1a..af0c7b0755c7aad5dd145ea5ea8ace59941dd74a 100644
--- a/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
+++ b/tests/fpgadataflow/test_fpgadataflow_ip_stitch.py
@@ -48,12 +48,9 @@ from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ
from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver
from finn.transformation.fpgadataflow.make_pynq_proj import MakePYNQProject
from finn.transformation.fpgadataflow.synth_pynq_proj import SynthPYNQProject
+import finn.transformation.fpgadataflow.replace_verilog_relpaths as rvp
from finn.transformation.general import GiveUniqueNodeNames
-from finn.util.basic import (
- calculate_signed_dot_prod_range,
- gen_finn_dt_tensor,
- pynq_part_map,
-)
+from finn.util.basic import gen_finn_dt_tensor, pynq_part_map
from finn.util.fpgadataflow import pyverilate_stitched_ip
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
@@ -66,14 +63,14 @@ def create_one_fc_model():
# create a model with a StreamingFCLayer instance with no activation
# the wider range of the full accumulator makes debugging a bit easier
wdt = DataType.INT2
- idt = DataType.INT2
+ idt = DataType.INT32
odt = DataType.INT32
m = 4
no_act = 1
binary_xnor_mode = 0
actval = 0
- simd = 2
- pe = 2
+ simd = 4
+ pe = 4
inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, m])
outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, m])
@@ -119,13 +116,11 @@ def create_one_fc_model():
def create_two_fc_model():
# create a model with two StreamingFCLayer instances
wdt = DataType.INT2
- idt = DataType.INT2
- odt = DataType.INT2
- act = DataType.INT2
+ idt = DataType.INT32
+ odt = DataType.INT32
m = 4
- tdt = DataType.INT32
- actval = odt.min()
- no_act = 0
+ actval = 0
+ no_act = 1
binary_xnor_mode = 0
pe = 2
simd = 2
@@ -136,7 +131,7 @@ def create_two_fc_model():
fc0 = helper.make_node(
"StreamingFCLayer_Batch",
- ["inp", "w0", "t0"],
+ ["inp", "w0"],
["mid"],
domain="finn",
backend="fpgadataflow",
@@ -151,11 +146,12 @@ def create_two_fc_model():
ActVal=actval,
binaryXnorMode=binary_xnor_mode,
noActivation=no_act,
+ mem_mode="decoupled",
)
fc1 = helper.make_node(
"StreamingFCLayer_Batch",
- ["mid", "w1", "t1"],
+ ["mid", "w1"],
["outp"],
domain="finn",
backend="fpgadataflow",
@@ -170,6 +166,7 @@ def create_two_fc_model():
ActVal=actval,
binaryXnorMode=binary_xnor_mode,
noActivation=no_act,
+ mem_mode="decoupled",
)
graph = helper.make_graph(
@@ -190,24 +187,12 @@ def create_two_fc_model():
model.set_tensor_datatype("w1", wdt)
# generate weights
- w0 = gen_finn_dt_tensor(wdt, (m, m))
- w1 = gen_finn_dt_tensor(wdt, (m, m))
+ w0 = np.eye(m, dtype=np.float32)
+ w1 = np.eye(m, dtype=np.float32)
model.set_initializer("w0", w0)
model.set_initializer("w1", w1)
- # generate thresholds
- (min, max) = calculate_signed_dot_prod_range(idt, wdt, m)
- n_steps = act.get_num_possible_values() - 1
- t0 = np.random.randint(min, max - 1, (m, n_steps)).astype(np.float32)
- t1 = np.random.randint(min, max - 1, (m, n_steps)).astype(np.float32)
- # provide non-decreasing thresholds
- t0 = np.sort(t0, axis=1)
- t1 = np.sort(t1, axis=1)
-
- model.set_initializer("t0", t0)
- model.set_initializer("t1", t1)
- model.set_tensor_datatype("t0", tdt)
- model.set_tensor_datatype("t1", tdt)
+ model = model.transform(CreateDataflowPartition())
return model
@@ -234,6 +219,7 @@ def test_fpgadataflow_ipstitch_do_stitch():
model = ModelWrapper(
ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model.onnx"
)
+ model = model.transform(rvp.ReplaceVerilogRelPaths())
model = model.transform(CodeGen_ipstitch(test_fpga_part))
vivado_stitch_proj_dir = model.get_metadata_prop("vivado_stitch_proj")
assert vivado_stitch_proj_dir is not None
@@ -247,6 +233,7 @@ def test_fpgadataflow_ipstitch_do_stitch():
def test_fpgadataflow_ipstitch_rtlsim():
model = ModelWrapper(ip_stitch_model_dir + "/test_fpgadataflow_ip_stitch.onnx")
+ model.set_metadata_prop("rtlsim_trace", "whole_trace.vcd")
sim = pyverilate_stitched_ip(model)
exp_io = [
"ap_clk_0",
@@ -259,12 +246,31 @@ def test_fpgadataflow_ipstitch_rtlsim():
"out_r_0_tlast",
"out_r_0_tready",
"out_r_0_tvalid",
+ "s_axi_control_0_araddr",
+ "s_axi_control_0_arready",
+ "s_axi_control_0_arvalid",
+ "s_axi_control_0_awaddr",
+ "s_axi_control_0_awready",
+ "s_axi_control_0_awvalid",
+ "s_axi_control_0_bready",
+ "s_axi_control_0_bresp",
+ "s_axi_control_0_bvalid",
+ "s_axi_control_0_rdata",
+ "s_axi_control_0_rready",
+ "s_axi_control_0_rresp",
+ "s_axi_control_0_rvalid",
+ "s_axi_control_0_wdata",
+ "s_axi_control_0_wready",
+ "s_axi_control_0_wstrb",
+ "s_axi_control_0_wvalid",
]
assert dir(sim.io) == exp_io
model.set_metadata_prop("exec_mode", "rtlsim")
idt = model.get_tensor_datatype("inp")
ishape = model.get_tensor_shape("inp")
x = gen_finn_dt_tensor(idt, ishape)
+ # x = np.zeros(ishape, dtype=np.float32)
+ # x = np.asarray([[-2, -1, 0, 1]], dtype=np.float32)
rtlsim_res = execute_onnx(model, {"inp": x})["outp"]
assert (rtlsim_res == x).all()
@@ -297,17 +303,18 @@ def test_fpgadataflow_ipstitch_pynq_driver():
def test_fpgadataflow_ipstitch_pynq_deployment_folder():
- model = ModelWrapper(
- ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_pynq_driver.onnx"
- )
try:
ip = os.environ["PYNQ_IP"] # no default for this one; skip if not defined
if ip == "":
pytest.skip("PYNQ board IP address not specified")
+ model = ModelWrapper(
+ ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_pynq_driver.onnx"
+ )
username = os.getenv("PYNQ_USERNAME", "xilinx")
password = os.getenv("PYNQ_PASSWORD", "xilinx")
+ port = os.getenv("PYNQ_PORT", 22)
target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
- model = model.transform(DeployToPYNQ(ip, username, password, target_dir))
+ model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))
pynq_ip = model.get_metadata_prop("pynq_ip")
pynq_username = model.get_metadata_prop("pynq_username")
pynq_password = model.get_metadata_prop("pynq_password")
@@ -330,15 +337,17 @@ def test_fpgadataflow_ipstitch_pynq_deployment_folder():
def test_fpgadataflow_ipstitch_remote_execution():
- model = ModelWrapper(
- ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_pynq_deployment.onnx"
- )
try:
ip = os.environ["PYNQ_IP"] # NOQA
if ip == "":
pytest.skip("PYNQ board IP address not specified")
- idt = DataType.INT2
- x = gen_finn_dt_tensor(idt, (1, 4))
+ model = ModelWrapper(
+ ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_pynq_deployment.onnx"
+ )
+ iname = "inp"
+ idt = model.get_tensor_datatype(iname)
+ ishape = model.get_tensor_shape(iname)
+ x = gen_finn_dt_tensor(idt, ishape)
input_dict = {"inp": x}
outp = execute_onnx(model, input_dict)
assert np.isclose(outp["outp"], x).all()
diff --git a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py
index 0dd3fd7a9fefaaad9777ac98a35806a9eaa35188..38f792ed3cdd52044b28b4c19ac0603da4e502e6 100644
--- a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py
+++ b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py
@@ -92,7 +92,7 @@ def test_res_estimate():
model = model.transform(GiveUniqueNodeNames())
prod_resource_estimation = model.analysis(res_estimation)
expect_resource_estimation = {
- "StreamingFCLayer_Batch_0": ["BRAMs: 1", "LUTs: 304.4"]
+ "StreamingFCLayer_Batch_0": {"BRAM_18K": 1, "LUT": 304.4}
}
assert check_two_dict_for_equality(
diff --git a/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py b/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
index 67bb38640a4004569e43876d525eb0952e784128..a7a731aaa5593a9fd680061d2b8ad3fc47e9f490 100644
--- a/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
+++ b/tests/fpgadataflow/test_layer_streaming_maxpool_batch.py
@@ -26,122 +26,129 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-import numpy as np
+import pytest
+
from onnx import TensorProto, helper
import finn.core.onnx_exec as oxe
from finn.core.datatype import DataType
from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.fpgadataflow.codegen_ipgen import CodeGen_ipgen
from finn.transformation.fpgadataflow.codegen_npysim import CodeGen_npysim
from finn.transformation.fpgadataflow.compile import Compile
+from finn.transformation.fpgadataflow.hlssynth_ipgen import HLSSynth_IPGen
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
+from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
+from finn.transformation.general import GiveUniqueNodeNames
+from finn.util.basic import gen_finn_dt_tensor
+
+
+def make_single_maxpoolnhwc_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt):
+ odt = idt
+ inp = helper.make_tensor_value_info(
+ "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]
+ )
+ outp = helper.make_tensor_value_info(
+ "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, ifm_ch]
+ )
+
+ mp_node = helper.make_node(
+ "MaxPoolNHWC",
+ ["inp"],
+ ["outp"],
+ domain="finn",
+ kernel_shape=[k, k],
+ strides=[k, k],
+ pads=[0, 0, 0, 0],
+ )
+ graph = helper.make_graph(
+ nodes=[mp_node], name="mp_graph", inputs=[inp], outputs=[outp]
+ )
+
+ model = helper.make_model(graph, producer_name="mp-model")
+ model = ModelWrapper(model)
+
+ model.set_tensor_datatype("inp", idt)
+ model.set_tensor_datatype("outp", odt)
+
+ return model
-def test_layer_streaming_maxpool_batch():
- inp = helper.make_tensor_value_info("in", TensorProto.FLOAT, [2, 2, 4, 4])
- outp = helper.make_tensor_value_info("out", TensorProto.FLOAT, [2, 2, 2, 2])
+def make_single_streamingmaxpool_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt):
+ odt = idt
+ inp = helper.make_tensor_value_info(
+ "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]
+ )
+ outp = helper.make_tensor_value_info(
+ "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, ifm_ch]
+ )
- MaxPool_batch_node = helper.make_node(
+ smp_node = helper.make_node(
"StreamingMaxPool_Batch",
- ["in"],
- ["out"],
+ ["inp"],
+ ["outp"],
domain="finn",
backend="fpgadataflow",
- ImgDim=4,
- PoolDim=2,
- NumChannels=2,
+ PoolDim=k,
+ NumChannels=ifm_ch,
+ ImgDim=ifm_dim,
+ dataType=idt.name,
)
-
graph = helper.make_graph(
- nodes=[MaxPool_batch_node],
- name="max_pool_batch_graph",
- inputs=[inp],
- outputs=[outp],
+ nodes=[smp_node], name="smp_graph", inputs=[inp], outputs=[outp]
)
- model = helper.make_model(graph, producer_name="finn-hls-onnx-model")
+
+ model = helper.make_model(graph, producer_name="smp-model")
model = ModelWrapper(model)
- # set the tensor datatypes (in this case: all to bipolar)
- for tensor in graph.input:
- model.set_tensor_datatype(tensor.name, DataType["BIPOLAR"])
- for tensor in graph.output:
- model.set_tensor_datatype(tensor.name, DataType["BIPOLAR"])
-
- # onnx.save(model.model, "max-pool-model.onnx")
-
- input_tensor = np.asarray(
- [
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- 1,
- ],
- dtype=np.float32,
- ).reshape(2, 2, 4, 4)
-
- model = model.transform(SetExecMode("npysim"))
- model = model.transform(CodeGen_npysim())
- model = model.transform(Compile())
-
- input_dict = {"in": input_tensor}
- output_dict = oxe.execute_onnx(model, input_dict) # NOQA
+ model.set_tensor_datatype("inp", idt)
+ model.set_tensor_datatype("outp", odt)
+
+ return model
+
+
+def prepare_inputs(input_tensor):
+ return {"inp": input_tensor}
+
+
+# input datatype
+@pytest.mark.parametrize("idt", [DataType.BIPOLAR, DataType.INT2])
+# kernel size
+@pytest.mark.parametrize("k", [2, 4])
+# input dimension
+@pytest.mark.parametrize("ifm_dim", [4, 6, 8])
+# input channels
+@pytest.mark.parametrize("ifm_ch", [1, 2]) # , 2, 3, 4])
+# execution mode
+@pytest.mark.parametrize("exec_mode", ["rtlsim", "npysim"])
+def test_fpgadataflow_streamingmaxpool(idt, k, ifm_dim, ifm_ch, exec_mode):
+ stride = k
+ ofm_dim = int(((ifm_dim - k) / stride) + 1)
+ if ifm_dim % k != 0:
+ pytest.skip("Skipping StreamingMaxPool test w/ ImgDim % PoolDim != 0")
+
+ x = gen_finn_dt_tensor(idt, (1, ifm_dim, ifm_dim, ifm_ch))
+ # prepare input data
+ input_dict = prepare_inputs(x)
+
+ golden = make_single_maxpoolnhwc_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt)
+ y_expected = oxe.execute_onnx(golden, input_dict)["outp"]
+
+ model = make_single_streamingmaxpool_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt)
+
+ if exec_mode == "npysim":
+ model = model.transform(SetExecMode("npysim"))
+ model = model.transform(CodeGen_npysim())
+ model = model.transform(Compile())
+ elif exec_mode == "rtlsim":
+ model = model.transform(SetExecMode("rtlsim"))
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(CodeGen_ipgen("xc7z020clg400-1", 5))
+ model = model.transform(HLSSynth_IPGen())
+ model = model.transform(PrepareRTLSim())
+ else:
+ raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow")
+
+ # execute model
+ y_produced = oxe.execute_onnx(model, input_dict)["outp"]
+ assert (y_produced == y_expected).all()
diff --git a/tests/transformation/streamline/test_streamline_cnv.py b/tests/transformation/streamline/test_streamline_cnv.py
new file mode 100644
index 0000000000000000000000000000000000000000..ec5bf441b736b5faed0024749b5b77f213949029
--- /dev/null
+++ b/tests/transformation/streamline/test_streamline_cnv.py
@@ -0,0 +1,79 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import brevitas.onnx as bo
+import numpy as np
+import pytest
+import pkg_resources as pk
+
+import finn.core.onnx_exec as oxe
+from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.fold_constants import FoldConstants
+from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
+from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.streamline import Streamline
+from finn.util.test import get_test_model_trained
+from finn.util.basic import make_build_dir
+from finn.transformation.double_to_single_float import DoubleToSingleFloat
+
+export_onnx_path = make_build_dir("test_streamline_cnv_")
+
+# act bits
+@pytest.mark.parametrize("abits", [1])
+# weight bits
+@pytest.mark.parametrize("wbits", [1])
+# network topology / size
+@pytest.mark.parametrize("size", ["CNV"])
+def test_streamline_cnv(size, wbits, abits):
+ if wbits > abits:
+ pytest.skip("No wbits > abits cases at the moment")
+ nname = "%s_%dW%dA" % (size, wbits, abits)
+ finn_onnx = export_onnx_path + "/%s.onnx" % nname
+ fc = get_test_model_trained(size, wbits, abits)
+ bo.export_finn_onnx(fc, (1, 3, 32, 32), finn_onnx)
+ model = ModelWrapper(finn_onnx)
+ model = model.transform(DoubleToSingleFloat())
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(GiveReadableTensorNames())
+ # load one of the test vectors
+ fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
+ input_tensor = np.load(fn)["arr_0"].astype(np.float32)
+ assert input_tensor.shape == (1, 3, 32, 32)
+ # run using FINN-based execution
+ input_dict = {"global_in": input_tensor}
+ expected_ctx = oxe.execute_onnx(model, input_dict, True)
+ expected = expected_ctx[model.graph.output[0].name]
+ model.save("orig_cnv.onnx")
+ model = model.transform(Streamline())
+ model.save("streamlined_cnv.onnx")
+ produced_ctx = oxe.execute_onnx(model, input_dict, True)
+ produced = produced_ctx[model.graph.output[0].name]
+ assert np.isclose(expected, produced, atol=1e-3).all()
+ assert model.graph.node[0].op_type == "MultiThreshold"
diff --git a/tests/transformation/streamline/test_streamline_fc.py b/tests/transformation/streamline/test_streamline_fc.py
index b287ab65265448983fcfe4f7d94d595cd5ac5343..c68561239b7c30973856fa282d20cd2afaa168ae 100644
--- a/tests/transformation/streamline/test_streamline_fc.py
+++ b/tests/transformation/streamline/test_streamline_fc.py
@@ -45,13 +45,17 @@ from finn.util.basic import make_build_dir
export_onnx_path = make_build_dir("test_streamline_fc_")
-# activation: None or DataType
-@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
-# weight bits
-@pytest.mark.parametrize("wbits", [1])
# act bits
@pytest.mark.parametrize("abits", [1, 2])
+# weight bits
+@pytest.mark.parametrize("wbits", [1, 2])
+# network topology / size
+@pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"])
def test_streamline_fc(size, wbits, abits):
+ if size == "LFC" and wbits == 2 and abits == 2:
+ pytest.skip("No LFC-w2a2 present at the moment")
+ if wbits > abits:
+ pytest.skip("No wbits > abits cases at the moment")
nname = "%s_%dW%dA" % (size, wbits, abits)
finn_onnx = export_onnx_path + "/%s.onnx" % nname
fc = get_test_model_trained(size, wbits, abits)
diff --git a/tests/transformation/test_batchnorm_to_affine.py b/tests/transformation/test_batchnorm_to_affine.py
index 8728707589ade72fb1b21ca0333c4d0757ac7df0..997ca5ab110bf3612a4db1152ac844180daf7d43 100644
--- a/tests/transformation/test_batchnorm_to_affine.py
+++ b/tests/transformation/test_batchnorm_to_affine.py
@@ -28,10 +28,12 @@
import os
from pkgutil import get_data
+import pkg_resources as pk
import brevitas.onnx as bo
import onnx
import onnx.numpy_helper as nph
+import numpy as np
import finn.core.onnx_exec as oxe
from finn.core.modelwrapper import ModelWrapper
@@ -39,10 +41,34 @@ from finn.transformation.batchnorm_to_affine import BatchNormToAffine
from finn.transformation.fold_constants import FoldConstants
from finn.transformation.infer_shapes import InferShapes
from finn.util.test import get_test_model_trained
+from finn.transformation.double_to_single_float import DoubleToSingleFloat
export_onnx_path = "test_output_bn2affine.onnx"
+def test_batchnorm_to_affine_cnv_w1a1():
+ lfc = get_test_model_trained("CNV", 1, 1)
+ bo.export_finn_onnx(lfc, (1, 3, 32, 32), export_onnx_path)
+ model = ModelWrapper(export_onnx_path)
+ model = model.transform(DoubleToSingleFloat())
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
+ input_tensor = np.load(fn)["arr_0"].astype(np.float32)
+ assert input_tensor.shape == (1, 3, 32, 32)
+ input_dict = {"0": input_tensor}
+ output_dict = oxe.execute_onnx(model, input_dict)
+ expected = output_dict[list(output_dict.keys())[0]]
+ new_model = model.transform(BatchNormToAffine())
+ # check that there are no BN nodes left
+ op_types = list(map(lambda x: x.op_type, new_model.graph.node))
+ assert "BatchNormalization" not in op_types
+ output_dict_p = oxe.execute_onnx(new_model, input_dict)
+ produced = output_dict_p[list(output_dict_p.keys())[0]]
+ assert np.isclose(expected, produced).all()
+ os.remove(export_onnx_path)
+
+
def test_batchnorm_to_affine_lfc_w1a1():
lfc = get_test_model_trained("LFC", 1, 1)
bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path)
@@ -56,20 +82,3 @@ def test_batchnorm_to_affine_lfc_w1a1():
input_dict = {"0": nph.to_array(input_tensor)}
assert oxe.compare_execution(model, new_model, input_dict)
os.remove(export_onnx_path)
-
-
-# cnv batchnorm to affine not yet supported
-
-# def test_batchnorm_to_affine_cnv_w1a1():
-# lfc = get_test_model_trained("CNV", 1, 1)
-# bo.export_finn_onnx(lfc, (1, 3, 32, 32), export_onnx_path)
-# model = ModelWrapper(export_onnx_path)
-# model = model.transform(InferShapes())
-# model = model.transform(FoldConstants())
-# # TODO shape inference failing on transformed model below -- needs debug
-# new_model = model.transform(BatchNormToAffine())
-# # check that there are no BN nodes left
-# # TODO replace this with execution test
-# op_types = list(map(lambda x: x.op_type, new_model.graph.node))
-# assert "BatchNormalization" not in op_types
-# os.remove(export_onnx_path)
diff --git a/tests/transformation/test_conv_lowering.py b/tests/transformation/test_conv_lowering.py
new file mode 100644
index 0000000000000000000000000000000000000000..647a2b454a1a609c41707707e7fc9cf90dadd59c
--- /dev/null
+++ b/tests/transformation/test_conv_lowering.py
@@ -0,0 +1,65 @@
+# Copyright (c) 2020, Xilinx
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import pkg_resources as pk
+import brevitas.onnx as bo
+import numpy as np
+
+
+from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.fold_constants import FoldConstants
+from finn.transformation.infer_shapes import InferShapes
+from finn.util.test import get_test_model_trained
+from finn.transformation.lower_convs_to_matmul import LowerConvsToMatMul
+from finn.transformation.double_to_single_float import DoubleToSingleFloat
+import finn.core.onnx_exec as oxe
+
+export_onnx_path = "test_output_cnv.onnx"
+
+
+def test_conv_lowering_cnv_w1a1():
+ cnv = get_test_model_trained("CNV", 1, 1)
+ bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path)
+ model = ModelWrapper(export_onnx_path)
+ model = model.transform(DoubleToSingleFloat())
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ fn = pk.resource_filename("finn", "data/cifar10/cifar10-test-data-class3.npz")
+ input_tensor = np.load(fn)["arr_0"].astype(np.float32)
+ assert input_tensor.shape == (1, 3, 32, 32)
+ # execute imported model to get expected answer
+ input_dict = {"0": input_tensor}
+ output_dict_e = oxe.execute_onnx(model, input_dict)
+ expected = output_dict_e[list(output_dict_e.keys())[0]]
+ # execute transformed model and compare
+ model = model.transform(LowerConvsToMatMul())
+ output_dict_p = oxe.execute_onnx(model, input_dict)
+ produced = output_dict_p[list(output_dict_p.keys())[0]]
+ assert np.isclose(produced, expected).all()
+ os.remove(export_onnx_path)
diff --git a/tests/transformation/test_fold_constants.py b/tests/transformation/test_fold_constants.py
index cd1c346593e3666ce8a89bd4248fa8436423de6d..685c14a98b9031096aaf5b244c4f484d4f308bca 100644
--- a/tests/transformation/test_fold_constants.py
+++ b/tests/transformation/test_fold_constants.py
@@ -65,7 +65,8 @@ def test_const_folding_shapes():
model = ModelWrapper(export_onnx_path)
model = model.transform(InferShapes())
model = model.transform(FoldConstants())
- assert model.graph.node[0].op_type == "Reshape"
- assert list(model.get_tensor_shape("0")) == [1, 1, 28, 28]
- assert list(model.get_tensor_shape("27")) == [1, 784]
+ reshape_node = model.graph.node[0]
+ assert reshape_node.op_type == "Reshape"
+ assert list(model.get_tensor_shape(reshape_node.input[0])) == [1, 1, 28, 28]
+ assert list(model.get_tensor_shape(reshape_node.output[0])) == [1, 784]
os.remove(export_onnx_path)
diff --git a/tests/transformation/test_topk_insert.py b/tests/transformation/test_topk_insert.py
new file mode 100644
index 0000000000000000000000000000000000000000..ac32c30edbbf466b2b441bcc92975a7d50f42bda
--- /dev/null
+++ b/tests/transformation/test_topk_insert.py
@@ -0,0 +1,58 @@
+import onnx
+from finn.util.test import get_test_model_trained
+import brevitas.onnx as bo
+import numpy as np
+import onnx.numpy_helper as nph
+import torch
+
+from finn.core.modelwrapper import ModelWrapper
+from finn.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames
+from finn.transformation.infer_shapes import InferShapes
+from finn.transformation.infer_datatypes import InferDataTypes
+from finn.transformation.fold_constants import FoldConstants
+from finn.transformation.insert_topk import InsertTopK
+
+import finn.core.onnx_exec as oxe
+from pkgutil import get_data
+
+import pytest
+
+export_onnx_path = "test_output_lfc.onnx"
+
+
+@pytest.mark.parametrize("k", [1, 5, 10])
+def test_topk_insert(k):
+ tfc = get_test_model_trained("TFC", 1, 1)
+ bo.export_finn_onnx(tfc, (1, 1, 28, 28), export_onnx_path)
+ model = ModelWrapper(export_onnx_path)
+
+ # do transformations (no topk)
+ model = model.transform(InferShapes())
+ model = model.transform(FoldConstants())
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(GiveReadableTensorNames())
+ model = model.transform(InferDataTypes())
+
+ # verification: generate random input, run through net, streamline,
+ # run again, check that output is top-k
+ raw_i = get_data("finn", "data/onnx/mnist-conv/test_data_set_0/input_0.pb")
+ input_tensor = onnx.load_tensor_from_string(raw_i)
+ input_brevitas = torch.from_numpy(nph.to_array(input_tensor)).float()
+ output_golden = tfc.forward(input_brevitas).detach().numpy()
+ output_golden_topk = np.flip(output_golden.flatten().argsort())[:k]
+ output_golden_topk = output_golden_topk.flatten()
+
+ input_dict = {"global_in": nph.to_array(input_tensor)}
+
+ # insert top-k
+ model = model.transform(InsertTopK(k))
+ model = model.transform(GiveUniqueNodeNames())
+ model = model.transform(GiveReadableTensorNames())
+ model = model.transform(InferShapes())
+
+ # verify output of top-k
+ output_dict_topk = oxe.execute_onnx(model, input_dict)
+ output_pysim_topk = output_dict_topk[list(output_dict_topk.keys())[0]]
+ output_pysim_topk = output_pysim_topk.astype(np.int).flatten()
+
+ assert np.array_equal(output_golden_topk, output_pysim_topk)
diff --git a/tests/travis_install.sh b/tests/travis_install.sh
deleted file mode 100644
index 05ff95a6a2205d90a5813b41504e2105e36e2f92..0000000000000000000000000000000000000000
--- a/tests/travis_install.sh
+++ /dev/null
@@ -1,89 +0,0 @@
-#!/bin/bash
-# Copyright (c) 2020, Xilinx
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# * Neither the name of FINN nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-# This script is meant to be called by the "install" step defined in
-# .travis.yml. See http://docs.travis-ci.com/ for more details.
-# The behavior of the script is controlled by environment variabled defined
-# in the .travis.yml in the top level folder of the project.
-#
-# This script is inspired by Scikit-Learn (http://scikit-learn.org/)
-#
-# THIS SCRIPT IS SUPPOSED TO BE AN EXAMPLE. MODIFY IT ACCORDING TO YOUR NEEDS!
-
-set -e
-
-if [[ "$DISTRIB" == "conda" ]]; then
- # Deactivate the travis-provided virtual environment and setup a
- # conda-based environment instead
- deactivate
-
- if [[ -f "$HOME/miniconda/bin/conda" ]]; then
- echo "Skip install conda [cached]"
- else
- # By default, travis caching mechanism creates an empty dir in the
- # beginning of the build, but conda installer aborts if it finds an
- # existing folder, so let's just remove it:
- rm -rf "$HOME/miniconda"
-
- # Use the miniconda installer for faster download / install of conda
- # itself
- wget http://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh \
- -O miniconda.sh
- chmod +x miniconda.sh && ./miniconda.sh -b -p $HOME/miniconda
- fi
- export PATH=$HOME/miniconda/bin:$PATH
- # Make sure to use the most updated version
- conda update --yes conda
-
- # Configure the conda environment and put it in the path using the
- # provided versions
- # (prefer local venv, since the miniconda folder is cached)
- conda create -p ./.venv --yes python=${PYTHON_VERSION} pip virtualenv
- source activate ./.venv
-fi
-
-# for all
-pip install -U pip setuptools
-pip install tox
-
-if [[ "$COVERAGE" == "true" ]]; then
- pip install -U pytest-cov pytest-virtualenv coverage coveralls flake8 pre-commit
-fi
-
-
-travis-cleanup() {
- printf "Cleaning up environments ... " # printf avoids new lines
- if [[ "$DISTRIB" == "conda" ]]; then
- # Force the env to be recreated next time, for build consistency
- source deactivate
- conda remove -p ./.venv --all --yes
- rm -rf ./.venv
- fi
- echo "DONE"
-}
diff --git a/tests/util/test_data_packing.py b/tests/util/test_data_packing.py
index 495ec60966ef67f3bf7b99c63cc70e133859d087..28f1d56d0dbc5451ccad3d36b4b1d4c6bed4f63e 100644
--- a/tests/util/test_data_packing.py
+++ b/tests/util/test_data_packing.py
@@ -104,6 +104,8 @@ g++ -o test_npy2apintstream test.cpp /workspace/cnpy/cnpy.cpp \
["sh", "compile.sh"], stdout=subprocess.PIPE, cwd=test_dir
)
(stdout, stderr) = compile.communicate()
+ # make copy before saving the array
+ ndarray = ndarray.copy()
np.save(npy_in, ndarray)
execute = subprocess.Popen(
"./test_npy2apintstream", stdout=subprocess.PIPE, cwd=test_dir