From a8d3fb6cd503721cdb444cefe07a7aca9f97477e Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Mon, 26 Sep 2022 16:16:46 +0200
Subject: [PATCH] [FIFO] SystemVerilog -> Verilog fix in Q_srl.v
---
finn-rtllib/memstream/hdl/Q_srl.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/finn-rtllib/memstream/hdl/Q_srl.v b/finn-rtllib/memstream/hdl/Q_srl.v
index 3c884770e..2f3d81350 100644
--- a/finn-rtllib/memstream/hdl/Q_srl.v
+++ b/finn-rtllib/memstream/hdl/Q_srl.v
@@ -143,7 +143,7 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
addr_full <= 0;
o_v_reg <= 0;
i_b_reg <= 1;
- maxcount_reg <= '0;
+ maxcount_reg <= 0;
end
else begin
state <= state_;
--
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