From a5bde9f55629ce973ce051dbddbee5455110fdf3 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Thu, 3 Sep 2020 12:51:35 +0200
Subject: [PATCH] [Test] make end2end rtlsim trace optional
---
tests/end2end/test_end2end.py | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/end2end/test_end2end.py b/tests/end2end/test_end2end.py
index 2813a2bc2..5f782e11c 100644
--- a/tests/end2end/test_end2end.py
+++ b/tests/end2end/test_end2end.py
@@ -89,6 +89,7 @@ test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
test_fpga_part = pynq_part_map[test_pynq_board]
target_clk_ns = 10
mem_mode = "decoupled"
+rtlsim_trace = False
def get_trained_network_and_ishape(topology, wbits, abits):
@@ -345,10 +346,11 @@ class TestEnd2End:
model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
model = model.transform(PrepareRTLSim())
model.set_metadata_prop("exec_mode", "rtlsim")
- model.set_metadata_prop(
- "rtlsim_trace", "%s_w%da%d.vcd" % (topology, wbits, abits)
- )
- os.environ["RTLSIM_TRACE_DEPTH"] = "3"
+ if rtlsim_trace:
+ model.set_metadata_prop(
+ "rtlsim_trace", "%s_w%da%d.vcd" % (topology, wbits, abits)
+ )
+ os.environ["RTLSIM_TRACE_DEPTH"] = "3"
rtlsim_chkpt = get_checkpoint_name(topology, wbits, abits, "ipstitch_rtlsim")
model.save(rtlsim_chkpt)
parent_chkpt = get_checkpoint_name(topology, wbits, abits, "dataflow_parent")
--
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