From a0b2141f762cd6929ff95dac0995bfb17e1203cd Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Fri, 23 Jun 2023 17:53:15 +0100
Subject: [PATCH] [Tranform] Enable rtlsim to utilize swg package
---
.../custom_op/fpgadataflow/convolutioninputgenerator_rtl.py | 5 +++++
src/finn/util/pyverilator.py | 6 +++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
index a1a32ba6a..c54c4ac1c 100755
--- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
+++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py
@@ -1064,6 +1064,9 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
shutil.copy2(
os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir
)
+ shutil.copy2(
+ os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv", code_gen_dir
+ )
# set ipgen_path and ip_path so that HLS-Synth transformation
# and stich_ip transformation do not complain
@@ -1082,6 +1085,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
verilog_paths = [code_gen_dir]
verilog_files = [
+ "swg_pkg.sv",
self.get_nodeattr("gen_top_module") + "_wrapper.v",
self.get_nodeattr("gen_top_module") + "_impl.sv",
"swg_common.sv",
@@ -1106,6 +1110,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
sourcefiles = [
+ "swg_pkg.sv",
self.get_nodeattr("gen_top_module") + "_wrapper.v",
self.get_nodeattr("gen_top_module") + "_impl.sv",
"swg_common.sv",
diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py
index 8d1885856..745239452 100644
--- a/src/finn/util/pyverilator.py
+++ b/src/finn/util/pyverilator.py
@@ -118,6 +118,8 @@ def prepare_stitched_ip_for_verilator(model):
if not remove_entry:
filtered_verilog_files.append(vfile)
remove_entry = True
+ elif "swg_pkg" in vfile:
+ continue
else:
filtered_verilog_files.append(vfile)
@@ -315,8 +317,10 @@ def pyverilate_stitched_ip(
xpm_cdc = f"{vivado_path}/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv"
xpm_fifo = f"{vivado_path}/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv"
+ swg_pkg = os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv"
+
sim = PyVerilator.build(
- [top_module_file_name, xpm_fifo, xpm_memory, xpm_cdc],
+ [swg_pkg, top_module_file_name, xpm_fifo, xpm_memory, xpm_cdc],
verilog_path=[vivado_stitch_proj_dir, verilog_header_dir],
build_dir=build_dir,
trace_depth=get_rtlsim_trace_depth(),
--
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