From a09e86ccbd2bc2468c250fd867c6688388b95750 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Sun, 16 Feb 2020 20:20:57 +0000
Subject: [PATCH] [Util] add pyverilate_stitched_ip helper
---
src/finn/util/fpgadataflow.py | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py
index 9434b16ec..f11192a12 100644
--- a/src/finn/util/fpgadataflow.py
+++ b/src/finn/util/fpgadataflow.py
@@ -1,12 +1,8 @@
-import subprocess
import os
-import numpy as np
+import subprocess
+
+from pyverilator import PyVerilator
-from finn.core.datatype import DataType
-from finn.util.data_packing import (
- pack_innermost_dim_as_hex_string,
- unpack_innermost_dim_from_hex_string,
-)
class IPGenBuilder:
def __init__(self):
@@ -34,3 +30,18 @@ class IPGenBuilder:
bash_command = ["bash", self.ipgen_script]
process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE)
process_compile.communicate()
+
+
+def pyverilate_stitched_ip(model):
+ "Given a model with stitched IP, return a PyVerilator sim object."
+ vivado_stitch_proj_dir = model.get_metadata_prop("vivado_stitch_proj")
+ with open(vivado_stitch_proj_dir + "/all_verilog_srcs.txt", "r") as f:
+ all_verilog_srcs = f.read().split()
+
+ def file_to_dir(x):
+ return os.path.dirname(os.path.realpath(x))
+
+ all_verilog_dirs = list(map(file_to_dir, all_verilog_srcs))
+ top_verilog = model.get_metadata_prop("wrapper_filename")
+ sim = PyVerilator.build(top_verilog, verilog_path=all_verilog_dirs)
+ return sim
--
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