From 9ec289c1566c01e2917e4ebd11fc9a50204e5345 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Mon, 23 May 2022 10:26:02 +0100
Subject: [PATCH] [Checksum] Expose axilite interface for checksum to the
outside
---
src/finn/custom_op/fpgadataflow/checksum.py | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/checksum.py b/src/finn/custom_op/fpgadataflow/checksum.py
index dffc90a9e..0c264fcce 100644
--- a/src/finn/custom_op/fpgadataflow/checksum.py
+++ b/src/finn/custom_op/fpgadataflow/checksum.py
@@ -179,7 +179,12 @@ class checksum(HLSCustomOp):
)
super().reset_rtlsim(sim)
super().toggle_clk(sim)
- output = self.rtlsim(sim, inp)
+ io_dict = {
+ "inputs": {"in0": inp},
+ "outputs": {"out": []},
+ }
+ self.rtlsim_multi_io(sim, io_dict)
+ output = io_dict["outputs"]["out"]
odt = self.get_output_datatype()
target_bits = odt.bitwidth()
packed_bits = self.get_outstream_width()
@@ -241,18 +246,22 @@ class checksum(HLSCustomOp):
]
def pragmas(self):
- self.code_gen_dict["$PRAGMAS$"] = ["#pragma HLS interface port=in0 axis"]
- self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS interface port=out axis")
+ self.code_gen_dict["$PRAGMAS$"] = [
+ "#pragma HLS interface axis port=in0 name=in0_" + self.hls_sname()
+ ]
+ self.code_gen_dict["$PRAGMAS$"].append(
+ "#pragma HLS interface axis port=out name=out_" + self.hls_sname()
+ )
self.code_gen_dict["$PRAGMAS$"].append(
- "#pragma HLS interface port=chk s_axilite"
+ "#pragma HLS interface s_axilite port=chk"
)
self.code_gen_dict["$PRAGMAS$"].append(
- "#pragma HLS interface port=return ap_ctrl_none"
+ "#pragma HLS interface ap_ctrl_none port=return"
)
self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS dataflow")
def get_verilog_top_module_intf_names(self):
intf_names = super().get_verilog_top_module_intf_names()
# expose axilite interface
- intf_names["axilite"] = ["s_axilite"]
+ intf_names["axilite"] = ["s_axi_control"]
return intf_names
--
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