diff --git a/finn-rtllib/memstream/hdl/Q_srl.v b/finn-rtllib/memstream/hdl/Q_srl.v
index 13bd2b6ead805a62b0ef13f6f94a9b28665f985f..80b015f6d4eb69df36831b25262cda3539ac8ae9 100644
--- a/finn-rtllib/memstream/hdl/Q_srl.v
+++ b/finn-rtllib/memstream/hdl/Q_srl.v
@@ -69,7 +69,7 @@
 `define Q_srl
 
 
-module Q_srl (clock, reset, i_d, i_v, i_b, o_d, o_v, o_b, count);
+module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count);
 
    parameter depth = 16;   // - greatest #items in queue  (2 <= depth <= 256)
    parameter width = 16;   // - width of data (i_d, o_d)
@@ -105,11 +105,13 @@ module Q_srl (clock, reset, i_d, i_v, i_b, o_d, o_v, o_b, count);
 
    input  [width-1:0] i_d;	// - input  stream data (concat data + eos)
    input              i_v;	// - input  stream valid
-   output             i_b;	// - input  stream back-pressure
+   output             i_r;	// - input  stream ready
+   wire               i_b;  // - input  stream back-pressure
 
    output [width-1:0] o_d;	// - output stream data (concat data + eos)
    output             o_v;	// - output stream valid
-   input              o_b;	// - output stream back-pressure
+   input              o_r;	// - output stream ready
+   wire               o_b;	// - output stream back-pressure
 
    output [addrwidth:0] count;  // - output number of elems in queue
 
@@ -147,6 +149,9 @@ module Q_srl (clock, reset, i_d, i_v, i_b, o_d, o_v, o_b, count);
    assign o_v = o_v_reg;			// - output valid if non-empty
    assign i_b = i_b_reg;			// - input bp if full
 
+   assign i_r = !i_b;
+   assign o_b = !o_r;
+
    assign count = (state==state_more ? addr+2 : (state==state_one ? 1 : 0));
 
    // - ''always'' block with both FFs and SRL16 does not work,
diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py
index e58d5fe24f882649dc5b4bcd09dbd39470c7f3d4..6b75570c9d4cc90bbb645159cffb73204b1afeaf 100644
--- a/src/finn/custom_op/fpgadataflow/templates.py
+++ b/src/finn/custom_op/fpgadataflow/templates.py
@@ -134,7 +134,7 @@ wire [31:0] config_q0;
 
 //multiple wire AXI Streams
 reg m_axis_0_afull = 0;
-reg m_axis_0_tready_inv;
+reg m_axis_0_tready;
 wire m_axis_0_tvalid;
 wire $WEIGHT_RANGE$ m_axis_0_tdata;
 
@@ -217,7 +217,7 @@ mem
 
 //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
 .m_axis_0_afull(m_axis_0_afull),
-.m_axis_0_tready(!m_axis_0_tready_inv),
+.m_axis_0_tready(m_axis_0_tready),
 .m_axis_0_tvalid(m_axis_0_tvalid),
 .m_axis_0_tdata(m_axis_0_tdata),
 
@@ -260,10 +260,10 @@ $LAYER_NAME$_w_fifo
  .reset(!ap_rst_n),
  .i_d(m_axis_0_tdata),
  .i_v(m_axis_0_tvalid),
- .i_b(m_axis_0_tready_inv),
+ .i_r(m_axis_0_tready),
  .o_d(m_axis_0_tdata_q),
  .o_v(m_axis_0_tvalid_q),
- .o_b(!m_axis_0_tready_q)
+ .o_r(m_axis_0_tready_q)
 );
 
 //MVA_Stream_Unit