From 9cfc9b1d137eb2fca583dd229c533ea5e27e4203 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Sat, 27 Nov 2021 00:16:26 +0100
Subject: [PATCH] [Concat] fix stitching for Vitis HLS
---
src/finn/custom_op/fpgadataflow/concat.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/finn/custom_op/fpgadataflow/concat.py b/src/finn/custom_op/fpgadataflow/concat.py
index 3d61d3abc..dd18e0623 100644
--- a/src/finn/custom_op/fpgadataflow/concat.py
+++ b/src/finn/custom_op/fpgadataflow/concat.py
@@ -362,9 +362,10 @@ class StreamingConcat(HLSCustomOp):
def get_verilog_top_module_intf_names(self):
intf_names = super().get_verilog_top_module_intf_names()
n_inputs = self.get_n_inputs()
+ sname = self.hls_sname()
intf_names["s_axis"] = []
for i in range(n_inputs):
intf_names["s_axis"].append(
- ("in%d_V_V" % i, self.get_instream_width_padded(i))
+ ("in%d_%s" % (i, sname), self.get_instream_width_padded(i))
)
return intf_names
--
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