From 97f93c854b6ac2caafbb93f942bc7c4bf594966f Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 27 May 2020 23:57:38 +0100
Subject: [PATCH] [Test] add rtlsim throughput test in end2end_tfc_w1a1
---
tests/end2end/test_end2end_tfc_w1a1.py | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/tests/end2end/test_end2end_tfc_w1a1.py b/tests/end2end/test_end2end_tfc_w1a1.py
index 15c1c41b0..354e8d889 100644
--- a/tests/end2end/test_end2end_tfc_w1a1.py
+++ b/tests/end2end/test_end2end_tfc_w1a1.py
@@ -72,6 +72,7 @@ from finn.util.basic import pynq_part_map
from finn.util.test import get_test_model_trained, load_test_checkpoint_or_skip
from finn.transformation.fpgadataflow.annotate_resources import AnnotateResources
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
+from finn.core.throughput_test import throughput_test_rtlsim
build_dir = "/tmp/" + os.environ["FINN_INST_NAME"]
test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
@@ -204,6 +205,21 @@ def test_end2end_tfc_w1a1_verify_dataflow_part():
assert np.isclose(res_cppsim, res_rtlsim_whole).all()
+@pytest.mark.vivado
+def test_end2end_tfc_w1a1_throughput_test_rtlsim():
+ model = load_test_checkpoint_or_skip(
+ build_dir + "/end2end_tfc_w1a1_ipstitch_whole_rtlsim.onnx"
+ )
+ # run through IP-stitched rtlsim with increasing batch sizes and
+ # check the number of cycles it takes to execute
+ ret = throughput_test_rtlsim(model, 1)
+ assert ret["cycles"] == 206
+ ret = throughput_test_rtlsim(model, 10)
+ assert ret["cycles"] == 845
+ ret = throughput_test_rtlsim(model, 100)
+ assert ret["cycles"] == 71135
+
+
@pytest.mark.vivado
def test_end2end_tfc_w1a1_verify_all():
# use the streamlined model as the "golden" model for right answers
--
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