From 9731267fee0729c99289218e0df235587743a102 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Tue, 21 Dec 2021 14:44:14 +0100
Subject: [PATCH] [Test] make fpga_part configurable for 1D SWG test, default
to z7020
---
tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py
index f2be24185..4d8fa2584 100644
--- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py
+++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py
@@ -46,6 +46,8 @@ from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.general import GiveUniqueNodeNames
from finn.util.basic import gen_finn_dt_tensor
+fpga_part = "xc7z020clg400-1"
+
def make_single_im2col_modelwrapper(
k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt
@@ -232,7 +234,7 @@ def test_fpgadataflow_slidingwindow_1d(
elif exec_mode == "rtlsim":
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(GiveUniqueNodeNames())
- model = model.transform(PrepareIP("xcu250-figd2104-2L-e", 5))
+ model = model.transform(PrepareIP(fpga_part, 5))
model = model.transform(HLSSynthIP())
model = model.transform(PrepareRTLSim())
else:
--
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